CN101650548A - Time setting device for digital substation - Google Patents

Time setting device for digital substation Download PDF

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Publication number
CN101650548A
CN101650548A CN 200910034664 CN200910034664A CN101650548A CN 101650548 A CN101650548 A CN 101650548A CN 200910034664 CN200910034664 CN 200910034664 CN 200910034664 A CN200910034664 A CN 200910034664A CN 101650548 A CN101650548 A CN 101650548A
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CN
China
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module
processing unit
central processing
at91rm9200
ethernet
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CN 200910034664
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Chinese (zh)
Inventor
吴在军
黄伟
汪祺航
李澄
窦晓波
胡敏强
杜炎森
王伏亮
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江苏方天电力技术有限公司
东南大学
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Priority to CN 200910034664 priority Critical patent/CN101650548A/en
Publication of CN101650548A publication Critical patent/CN101650548A/en

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    • Y02E60/723

Abstract

The invention discloses a time comparing device for a digital substation, comprising a core processing module and a PTP event processing module, an Ethernet communication interface module, a serial communication interface module and a discrete input/output module, which communicate with the core processing module. The device is characterized in that the core processing module comprises a central processing unit (CPU) AT91RM9200 which forms a basic embedded system with a synchronous dynamic random access memory, parallel flash, a real-time clock, a watchdog timer and a JTAG debug port, which are connected with the CPU AT91RM9200. The PTP event processing module, an Ethernet transceiver DP83640 and protocol stack software/hardware supporting the IEEE1588 standard are combined to realize thehigh-precision time comparing function of the substation device. The device realizes the high-precision time comparing supporting the IEEE1588 standard and the time synchronization requirement of thedigital substation device.

Description

Digital transformer substation to the time device
Technical field
The present invention relates to a kind of realize the digital transformer substation clock synchronization to the time device, belong to the power system transformer substation technical field of automation.
Background technology
Along with the development of digital transformer substation technology, digital transformer substation monitors control, and fault analysis and operational management all need to be based upon on the unified time benchmark.Digital transformer substation extensively adopts the electronic type voltage current transformer and based on the uniform communication agreement of IEC61850 standard, realized that on-the-spot service data is in each intelligent electronic device (Intelligent Electronic Device, IED) information sharing between.The process that the is digitized as layer sampled data of information acquisition shared provides condition, simultaneously, has also brought the problem of each electronic type voltage current transformer sample-synchronous.In transformer station, general second protection equipment and watch-dog all need to gather a plurality of electric weight.The collection of this all tittles all needs strict clock synchronization.
Transformer station's Clock Synchronization Technology of present stage China's widespread use have GPS, IRIG-B and SNTP to the time.But since GPS, IRIG-B to the time need arrange that separate cable is connected to each IED, make the reliability of full station arrangement reduce.And the secondary hardwire is replaced by serial communication bus in the digital transformer substation.Therefore need to select a kind of and higher technological means of substation communication network compatibility.SNTP to the time can with transformer station's Web-compatible, but to realize that the sampled value synchronous accuracy of IEC61850 defined also has very big difficulty.
The IEEE1588 standard as a kind of precision clock agreement (Precise Time Protocol, PTP), the mode that adopts software and hardware to combine, can reach the submicrosecond level to the time precision, can satisfy IEC61850 to the requirement of high sampling precision.And, IEEE1588 standard and ethernet communication protocol compatibility, the communication network of support digital transformer substation.Present stage in theoretical research stage, still lacks relevant matured product for the research many places of the application of IEEE1588 in digital transformer substation.
Therefore, at the digital transformer substation application requirements, be necessary to design a kind of can realize PTP to the time function, and the high precision that has flexibly configuration and a good extendability to the time device.This device both can be used as independent device and provided clock reference for peripherals, again can as to the time module insert among the IED put into operation its PTP of expansion to the time function, save the cost of transformer station in upgrading.
Summary of the invention
Technical matters to be solved by this invention provides a kind of IEEE1588 of support standard, high precision, high reliability, digital transformer substation clock synchronization apparatus cheaply.
For solving the problems of the technologies described above, the invention provides a kind of digital transformer substation to the time device, comprise core processing module and the PTP event processing module that communicates with core processing module, the ethernet interface module, serial communication interface module and switching value input/output module, it is characterized in that: described core processing module comprises central processing unit AT91RM9200, the coupled Synchronous Dynamic Random Access Memory of described central processing unit AT91RM9200, paralleling flash memory, real-time clock, WatchDog Timer and JTAG debug port primordial embedded system originally; The debug serial port end USART0 of described central processing unit AT91RM9200, serial ports 1 end USART1, serial ports 2 end USART3 join with the serial communication interface module respectively, ethernet controller end EMAC, data line end DB:0 and the PTP event processing module of central processing unit AT91RM9200 join, and GPIO mouth and the switching value input/output module of described central processing unit AT91RM9200 are joined.
As preferably, the central processing unit AT91RM9200 in the described core processing module joins by address bus, data bus and control bus and Synchronous Dynamic Random Access Memory, paralleling flash memory; Join by address bus, data bus and control bus and real-time clock WatchDog Timer, join by RESET pin and WatchDog Timer.
As preferably, described PTP event processing module and ethernet interface module are that same hardware is formed, comprise Ethernet first passage and Ethernet second channel, described Ethernet first passage comprises the port RJ45 of built-in isolating transformer, the port RJ45 of described built-in isolating transformer links to each other with FDX Ethernet transceiver DP83640, the transmitting terminal ETX of the ethernet controller EMAC that described central processing unit AT91RM9200 is embedded, receiving end ERX, control end ECON meets the transmitting terminal ETX of the first FDX Ethernet transceiver DP83640 respectively, receiving end ERX, control end ECON; Described Ethernet second channel comprises fiber optical transceiver, described fiber optical transceiver is connected successively with the second FDX Ethernet transceiver DP8364 and ethernet controller LAN9215, and described central processing unit AT91RM9200 data bus DB, address bus AB and control bus CON meet data bus DB, address bus AB and the control bus CON of ethernet controller LAN9215 respectively.
As preferably, the serial communication controller SCC1 that described serial communication interface module is carried by central processing unit AT91RM9200, RS485 level shifting circuit MAX485, bipod socket constitute one road RS485 serial-port, the Extended Capabilities Port that keeps as the user; Serial communication controller SCC3, RS485 level shifting circuit MAX485, bipod socket constitute another road RS485 serial-port, also the Extended Capabilities Port that keeps as the user; Central processing unit AT91RM9200 has one road UDP controller, USB device port constitutes the USB serial-port, also as user's reserved port; Road debug serial port SCCO that central processing unit AT91RM9200 has and RS232 level shifting circuit MAX203, standard nine kinds of needles socket DB9 are configured to three-wire system RS232 serial ports as the field adjustable passage; Be provided with the high-speed light isolator between the level shifting circuit of described serial communication controller SCC3 and correspondence.
As preferably, described switching value input/output module comprises that altogether 19 the tunnel open into leaving passage; Open into leave signal by light every linking to each other with row's pin of circuit board.Wherein the AT91RM9200 chip provides 5 the tunnel to open into leaving passage, and the DP83640 chip provides 14 the tunnel to open into leaving passage.
In addition, have the system initialization functional module in described central processing unit and paralleling flash memory, be used for when system start-up, central processing unit is carried out the initialization boot that paralleling flash memory provides, the function of each module initialization of realization system.
Have the system configuration functional module in described central processing unit and paralleling flash memory, be used for behind system initialization, central processing unit imports stored configuration parameters in the paralleling flash memory, realizes the functional configuration and the operational factor setting of each module.
In described central processing unit, have GOOSE and SAV message processing capacity module, be used for behind the GOOSE and SAV message of the standard of receiving, utilizing central processing unit to handle or transmit; Perhaps send the GOOSE and the SAV message of standard to communication interface by central processing unit 11.
In described central processing unit, have to the time message processing capacity module, be used for sending or receiving the PTP message, the markers that handling PTP time processing module provides is come the time deviation between calculation element, and determines the state of device by the best master clock algorithm.If be major clock, then send sync message to network, if be, then receive sync message, and revise the time value of real-time clock from clock, reach synchronous with master clock device.
Described GOOSE and SAV message processing capacity module and to the time comprise in the message processing capacity module and interrupt and interrupt the task program that driven.
In described paralleling flash memory, have the database management function module, be used to preserve and manage the operation information and the state configuration information of whole device.
The beneficial effect that the present invention reached: the present invention is by making rational planning for hardware resource, provide high-performance, high open, high reliability and cheaply the digital transformer substation high precision to the time device, and based on special hardware chip, adopt unified network and stipulations system, cooperate corresponding program to realize the clock synchronization requirement of substation equipment.
(1) solved the problem of substation equipment clock synchronization
This device can receive accurate synchronous clock source signal by serial communication interface, and clock source signals is transmitted to other equipment on the digital transformer substation process bus by ethernet port, with the unified clock signal of full station clock, provide clock reference for full station as full station owner's clock apparatus to this device.
(2) solved the transmission problem of substation equipment precise synchronization clock signal source signal
Can adapt to the existing various communication medias of transformer station (comprising RS-232/RS-485 serial ports, RJ45 and fiber optic network interface etc.), can effectively, easily the clock synchronization compliant with precision time protocol port be managed and operate, realize that substation equipment is interconnected and synchronous.And equipment and main process chip provide clock synchronization compliant with precision time protocol signal and PPS signal to the periphery.In order to the expanding peripherals function.
(3) open system, flexible configuration
Kept a lot of communication interfaces during the hardware configuration design, can be according to user's request flexible configuration hardware resource.For the user, open system, configuration flexibly will help utilizing existing software and hardware resources, reduce investment outlay and the convenience of long-term using system.Moreover, since transformer station to the time system very huge, form reasonable configuration on the basis of satisfying reliability, can further reduce cost.
(4) extensive applicability
Though the precision clock synchronous device is developed at the demand of transformer station's clock system at first, but because the dirigibility of its structure, self powerful data-handling capacity and communication capacity, can also have extensive applicability as the hardware platform of systems such as distributed control, network observing and controlling.
Description of drawings
Fig. 1 is a hardware circuit principle block diagram of the present invention;
Fig. 2 is the schematic block circuit diagram of Ethernet first passage of the present invention;
Fig. 3 is the schematic block circuit diagram of Ethernet second channel of the present invention;
Fig. 4 is the schematic block circuit diagram of serial communication interface module of the present invention;
Fig. 5 is the schematic block circuit diagram of switching value input/output module of the present invention;
Fig. 6 is that software function module of the present invention is divided synoptic diagram;
Fig. 7 is a software system data flow graph of the present invention.
Embodiment
The present invention is further illustrated below in conjunction with accompanying drawing.
A kind of digital transformer substation provided by the invention to the time device, comprise core processing module 1 and the PTP event processing module 2 that communicates with core processing module, ethernet interface module 3, serial communication interface module 4 and switching value input/output module 5, it is characterized in that: described core processing module 1 comprises central processing unit AT91RM920011, the Synchronous Dynamic Random Access Memory 12 that described central processing unit AT91RM920011 is coupled, paralleling flash memory 13, real-time clock, WatchDog Timer 14 and JTAG debug port 15 primordials embedded system originally; The debug serial port end USART0 of described central processing unit AT91RM920011, serial ports 1 end USART1, serial ports 2 end USART3 join with serial communication interface module 4 respectively, the ethernet controller end EMAC of central processing unit AT91RM9200, data line end DB 31:0 and PTP event processing module 2 join, and GPIO mouth and the switching value input/output module 5 of described central processing unit AT91RM920011 are joined.
As preferably, the central processing unit AT91RM920011 in the described core processing module 1 joins by address bus, data bus and control bus and Synchronous Dynamic Random Access Memory 12, paralleling flash memory 13; Join by address bus, data bus and control bus and real-time clock WatchDog Timer 14, join by RESET pin and WatchDog Timer 15.
As preferably, described PTP event processing module 2 is that same hardware is formed with ethernet interface module 3, comprise Ethernet first passage and Ethernet second channel, described Ethernet first passage comprises the port RJ45 23 of built-in isolating transformer, the port RJ45 23 of described built-in isolating transformer links to each other with FDX Ethernet transceiver DP83640 22, the transmitting terminal ETX of the 10/100Mbps ethernet controller EMAC 21 that described central processing unit AT91RM920011 is embedded, receiving end ERX, control end ECON meets the transmitting terminal ETX of the first FDX Ethernet transceiver DP83640 22 respectively, receiving end ERX, control end ECON; Described Ethernet second channel comprises fiber optical transceiver 26, described fiber optical transceiver 26 is connected successively with the second FDX Ethernet transceiver DP83640 25 and ethernet controller LAN9215 24, and described central processing unit AT91RM920011 data bus DB, address bus AB and control bus CON meet data bus DB, address bus AB and the control bus CON of ethernet controller LAN9215 24 respectively.
As preferably, the serial communication controller SCC1 43 that described serial communication interface module 4 is carried by central processing unit AT91RM920011, RS485 level shifting circuit MAX485 430, bipod socket 431 constitute one road RS485 serial-port, as the Extended Capabilities Port of user's reservation; Serial communication controller SCC 344, RS485 level shifting circuit MAX485 440, bipod socket 441 constitute another road RS485 serial-port, also the Extended Capabilities Port that keeps as the user; Central processing unit AT91RM920011 has one road UDP controller 42, USB device port 420 constitutes the USB serial-port, also as user's reserved port; The road debugging string SCC0 41 that central processing unit AT91RM920011 has, RS232 level shifting circuit MAX203 410, standard nine kinds of needles socket DB9 411 are configured to simple three-wire system RS232 serial ports as the field adjustable passage in addition; Be provided with high-speed light isolator 50 between the level shifting circuit of described serial communication controller SCC3 and correspondence.
Fig. 1 is a hardware circuit principle block diagram of the present invention.Comprise in the present embodiment with lower module: core processing module 1, ethernet interface module 2, PTP event processing module 3, serial communication interface module 4 and switching value input/output module 5.
1. central processing unit AT91RM9200
The core processing module 1 of embedded transformer station information integrated server comprises peripheral auxiliary circuits such as central processing unit AT91RM9200, Synchronous Dynamic Random Access Memory, paralleling flash memory, real-time clock and WatchDog Timer, their common primordials embedded system originally.
2.PTP event processing module
Fig. 2 is the schematic block circuit diagram of Ethernet first passage of the present invention; Fig. 3 is the schematic block circuit diagram of Ethernet second channel of the present invention.PTP event processing module Ethernet first passage is made up of the RJ45 port and the embedded 10/100Mbps ethernet controller EMAC of AT91RM9200 of the first FDX Ethernet transceiver DP83640 chip, integrated isolating transformer.The Ethernet second channel is made up of the second FDX Ethernet transceiver DP83640 chip, LAN9215 chip and HFBR5803 optical fiber interface.
The DP8364 chip is the 10/100Mbps ethernet transceiver of technical grade, adopts the 3.3V power supply, can directly be connected with AT91RM9200 and need not level conversion, but the active crystal oscillator of need employing 25MHz provide time-base signal for it.The embedded EMAC module of AT91RM9200 can be connected with DP83640 easily, as long as the ETX in the EMAC module (transmission) pin, ERX (reception) pin and ECON (control pin) are connected with ETX (transmission) pin, ERX (reception) pin and the ECON (control pin) of DP83640 respectively accordingly.FDX Ethernet transceiver DP83640 directly links to each other with RJ45, connects each type shielding or unshielded twisted pair by RJ45.The DP83640 chip provides 3 signal lamp pins, and this device is configured as SPEED, LINK, ACTIVE signal, represents speed, connection, received signal respectively.But the DP83640 chip is the incoming fiber optic circuit also, and in the Ethernet second channel, the DP83640 chip directly connects fiber optical transceiver, only reception/transmission signal need be connected with fiber optical transceiver to get final product.
LAN9215 also is the 3.3V power supply, and its data line/address wire can directly be connected with AT91RM9200.The reading and writing of LAN9215, interrupt control pin directly connect the respective pin of AT91RM9200, and AT91RM9200 connects the reset pin (must reset earlier) of LAN9215 before LAN9215 is operated by an I/O pin.The order of LAN9215 sends by identical data line with data, is distinguished by different addresses and format information.
3. ethernet interface module
The hardware circuit of PTP event processing module and ethernet interface module is in full accord.PTP message and substation data message are handled by same ethernet communication channel multiplexing.Only doing different functions on software divides.
4. serial communication interface module
Fig. 4 is the schematic block circuit diagram of serial communication interface module of the present invention, and serial communication controller UDP, the USB port that the serial communication interface module 4 of embedded transformer station information integrated server is carried by AT91RM9200 constitutes one road USB serial-port; Standard serial communication controler SCC0, RS232 level shifting circuit MAX203, standard nine kinds of needles socket DB9 constitute one road RS232 standard serial passage; Serial communication controller SCC1 and SCC3, RS485 level shifting circuit MAX485, bipod socket constitute two-way RS485 serial-port; In order to strengthen antijamming capability, between serial communication controller and corresponding level shifting circuit, all design high-speed light every.
5. switching value input/output module
Fig. 5 is the schematic block circuit diagram of switching value input/output module of the present invention; The AT91RM9200 chip provides 5 the tunnel to open into leaving passage, and the DP83640 chip provides 14 the tunnel to open into leaving passage.Can be used for information interaction, Event triggered and clock signal input and output for peripherals and device, device core processing module and PTP event processing module.
Fig. 6 is that software function module of the present invention is divided synoptic diagram; On the software function, precision clock to the time device mainly finish the reception and the transmission of IEEE1588 standard message, the clock synchronization compliant with precision time protocol port of device is set to ordinary clock, the clock synchronization function of implement device.Simultaneously, device is also supported the IEC61850 communication protocol, can be to finishing transmission, reception and simple processing the to GOOSE message and SAV message.
By the modular design cardinal rule of " function is independent ", the clock synchronization apparatus software architecture comprises following modules: system initialization module, system configuration module, PTP event request and processing module, data processing module, database management module etc.Wherein having encapsulated interruption in PTP event request and processing module and the data processing module and having interrupted being driven of task.
Fig. 7 is a software system data flow graph of the present invention.The module of " function is independent " can reduce the cost in stages such as exploitation, test, maintenance." but function is independent " also do not mean that absolute the isolating of maintenance between the module.System will finish a certain task, and needing each module to cooperatively interact could realize, will carry out information interchange between the module this moment.After system initialization, each modules configured parameter can be configured according to the state of switching value input/output module 5.In system's operational process, information and data in PTP event processing module 2, the ethernet communication module 3 are handled by core processing module 1.Core processing module 1 sends to host computer by serial communication module 4 with real-time information and data.The user can be handed down to core processing module 1 with steering order by serial communication module 4, and core processing module 1 changes the duty of the state of switching value input/output module 5 and PTP event processing module 2, ethernet communication module 3 by steering order.
Below announce the present invention with preferred embodiment, so it is not in order to restriction the present invention, and all technical schemes that mode obtained of taking to be equal to replacement or equivalent transformation all drop in protection scope of the present invention.

Claims (6)

  1. A digital transformer substation to the time device, comprise core processing module and the PTP event processing module that communicates with core processing module, ethernet interface module, serial communication interface module and switching value input/output module, it is characterized in that: described core processing module comprises central processing unit AT91RM9200, Synchronous Dynamic Random Access Memory, paralleling flash memory, real-time clock, WatchDog Timer and the JTAG debug port primordial embedded system originally that described central processing unit AT91RM9200 is coupled; The debug serial port end USART0 of described central processing unit AT91RM9200, serial ports 1 end USART1, serial ports 2 end USART3 join with the serial communication interface module respectively, ethernet controller end EMAC, data line end DB:0 and the PTP event processing module of central processing unit AT91RM9200 join, and GPIO mouth and the switching value input/output module of described central processing unit AT91RM9200 are joined.
  2. 2. digital transformer substation according to claim 1 to the time device, it is characterized in that: the central processing unit AT91RM9200 in the described core processing module joins by address bus, data bus and control bus and Synchronous Dynamic Random Access Memory, paralleling flash memory; Join by address bus, data bus and control bus and real-time clock, WatchDog Timer, join by RESET pin and WatchDog Timer.
  3. 3. digital transformer substation according to claim 1 to the time device, it is characterized in that: described PTP event processing module and ethernet interface module are that same hardware is formed, comprise Ethernet first passage and Ethernet second channel, described Ethernet first passage comprises the port RJ45 of built-in isolating transformer, the port RJ45 of described built-in isolating transformer links to each other with FDX Ethernet transceiver DP83640, the transmitting terminal ETX of the ethernet controller EMAC that described central processing unit AT91RM9200 is embedded, receiving end ERX, control end ECON meets the transmitting terminal ETX of the first FDX Ethernet transceiver DP83640 respectively, receiving end ERX, control end ECON; Described Ethernet second channel comprises fiber optical transceiver, described fiber optical transceiver is connected successively with the second FDX Ethernet transceiver DP8364 and ethernet controller LAN9215, and described central processing unit AT91RM9200 data bus DB, address bus AB and control bus CON meet data bus DB, address bus AB and the control bus CON of ethernet controller LAN9215 respectively.
  4. According to claim 1 or 2 or 3 described digital transformer substations to the time device, it is characterized in that: the serial communication controller SCC1 that described serial communication interface module is carried by central processing unit AT91RM9200, RS485 level shifting circuit MAX485, bipod socket constitute one road RS485 serial-port, as the Extended Capabilities Port of user's reservation; Serial communication controller SCC3, RS485 level shifting circuit MAX485, bipod socket constitute another road RS485 serial-port, also the Extended Capabilities Port that keeps as the user; Central processing unit AT91RM9200 has one road UDP controller, USB device port constitutes the USB serial-port, also as user's reserved port; Road debug serial port SCC0 that central processing unit AT91RM9200 has and RS232 level shifting circuit MAX203, standard nine kinds of needles socket DB9 are configured to three-wire system RS232 serial ports as the field adjustable passage; Be provided with the high-speed light isolator between the level shifting circuit of described serial communication controller SCC3 and correspondence.
  5. According to claim 1 or 2 or 3 described digital transformer substations to the time device, it is characterized in that: described switching value input/output module comprises that altogether 19 the tunnel open into leaving passage; Wherein the AT91RM9200 chip provides 5 the tunnel to open into leaving passage, and the DP83640 chip provides 14 the tunnel to open into leaving passage, open into leave signal by light every linking to each other with row's pin of circuit board.
  6. According to claim 1 or 2 or 3 described digital transformer substations to the time device, it is characterized in that: in described central processing unit and paralleling flash memory, have the system initialization functional module, be used for when system start-up, central processing unit is carried out the initialization boot that paralleling flash memory provides, the function of each module initialization of realization system;
    Have the system configuration functional module in described central processing unit and paralleling flash memory, be used for behind system initialization, central processing unit imports stored configuration parameters in the paralleling flash memory, realizes the functional configuration and the operational factor setting of each module;
    In described central processing unit, have GOOSE and SAV message processing capacity module, be used for behind the GOOSE and SAV message of the standard of receiving, utilizing the AT91RM9200 chip to handle or transmit; Perhaps send the GOOSE and the SAV message of standard to communication interface by the AT91RM9200 chip;
    In described central processing unit, have to the time message processing capacity module, be used for sending or receiving the PTP message, the markers that handling PTP time processing module provides is come the time deviation between calculation element, and determine the state of device by the best master clock algorithm, if be major clock, then send sync message to network, if be from clock, then receive sync message, and revise the time value of real-time clock, reach with master clock device synchronously;
    Described GOOSE and SAV message processing capacity module and to the time comprise in the message processing capacity module and interrupt and interrupt the task program that driven;
    In described paralleling flash memory, have the database management function module, be used to preserve and manage the operation information and the state configuration information of whole device.
CN 200910034664 2009-08-31 2009-08-31 Time setting device for digital substation CN101650548A (en)

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101951024A (en) * 2010-08-18 2011-01-19 国电南瑞科技股份有限公司 Digital data acquisition device
CN102361348A (en) * 2011-09-28 2012-02-22 江苏方天电力技术有限公司 Method for monitoring time setting state of secondary equipment of intelligent converting station
WO2012075881A1 (en) * 2010-12-08 2012-06-14 江苏省电力公司 Ieee1588-based sampled value multi-interface synchronization system for multiple slave clocks
CN102621954A (en) * 2012-03-22 2012-08-01 上海许继电气有限公司 Self-adaptive multi-signal-source time synchronization card device for smart grid and message analysis system
CN103209137A (en) * 2013-03-21 2013-07-17 国家电网公司 Configurable high-accuracy control system of time interval frame release Ethernet interface
CN103281171A (en) * 2013-05-10 2013-09-04 国家电网公司 Multi-clock synchronization method of distributed type sampling value network
CN103532235A (en) * 2013-10-18 2014-01-22 广州南方电力集团科技发展有限公司 Power distribution terminal based on ColdFire architecture
CN106094496A (en) * 2016-06-27 2016-11-09 柳州电器科学研究所有限公司 Transformer station's clock synchronization system
CN108873668A (en) * 2018-08-30 2018-11-23 新华三技术有限公司 Time calibrating method, processor and time calibration system
CN110504758A (en) * 2019-09-18 2019-11-26 国网湖北省电力有限公司电力科学研究院 A kind of substation equipment detection device based on ethernet physical layer
CN111711983A (en) * 2020-05-27 2020-09-25 南方电网数字电网研究院有限公司 Wireless time synchronization method and system

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101951024A (en) * 2010-08-18 2011-01-19 国电南瑞科技股份有限公司 Digital data acquisition device
CN101951024B (en) * 2010-08-18 2013-04-10 国电南瑞科技股份有限公司 Digital data acquisition device
WO2012075881A1 (en) * 2010-12-08 2012-06-14 江苏省电力公司 Ieee1588-based sampled value multi-interface synchronization system for multiple slave clocks
CN102361348A (en) * 2011-09-28 2012-02-22 江苏方天电力技术有限公司 Method for monitoring time setting state of secondary equipment of intelligent converting station
CN102621954A (en) * 2012-03-22 2012-08-01 上海许继电气有限公司 Self-adaptive multi-signal-source time synchronization card device for smart grid and message analysis system
CN103209137A (en) * 2013-03-21 2013-07-17 国家电网公司 Configurable high-accuracy control system of time interval frame release Ethernet interface
WO2014146455A1 (en) * 2013-03-21 2014-09-25 国家电网公司 System and method for controlling ethernet interface
CN103209137B (en) * 2013-03-21 2016-01-20 国家电网公司 Configurable high precision time interval frame issues Ethernet interface control system
CN103281171B (en) * 2013-05-10 2016-05-04 国家电网公司 The multi-clock synchronization method of distributed sample value networking
CN103281171A (en) * 2013-05-10 2013-09-04 国家电网公司 Multi-clock synchronization method of distributed type sampling value network
CN103532235A (en) * 2013-10-18 2014-01-22 广州南方电力集团科技发展有限公司 Power distribution terminal based on ColdFire architecture
CN106094496A (en) * 2016-06-27 2016-11-09 柳州电器科学研究所有限公司 Transformer station's clock synchronization system
CN108873668A (en) * 2018-08-30 2018-11-23 新华三技术有限公司 Time calibrating method, processor and time calibration system
CN110504758A (en) * 2019-09-18 2019-11-26 国网湖北省电力有限公司电力科学研究院 A kind of substation equipment detection device based on ethernet physical layer
CN111711983A (en) * 2020-05-27 2020-09-25 南方电网数字电网研究院有限公司 Wireless time synchronization method and system

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Application publication date: 20100217