CN108873668B - Time calibration method, processor and time calibration system - Google Patents
Time calibration method, processor and time calibration system Download PDFInfo
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- CN108873668B CN108873668B CN201811005223.1A CN201811005223A CN108873668B CN 108873668 B CN108873668 B CN 108873668B CN 201811005223 A CN201811005223 A CN 201811005223A CN 108873668 B CN108873668 B CN 108873668B
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Abstract
The embodiment of the invention relates to the technical field of communication, and provides a time calibration method, a processor and a time calibration system, when a logic device of electronic equipment needs to be started, a time calibration module integrated in the logic device reads first time recorded in a CMOS circuit and writes the first time into an external storage medium; when the logic device is started, the time calibration module reads first time from an external storage medium, and acquires the signal duration of an information clearing signal sent to the CMOS circuit by an external logic circuit and second time recorded after the CMOS circuit receives the enable clearing signal; finally, the time calibration module writes back the sum of the first time, the signal duration and the second time to the CMOS circuit, so that the time information in the CMOS circuit can be accurately recovered. The embodiment of the invention can automatically calibrate the time information of the CMOS circuit after the equipment is restarted, meets the time precision requirement of the electronic equipment and has good reliability.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a time calibration method, a processor and a time calibration system.
Background
With the development of science and technology, more and more electronic devices are applied to the life and work of people. Generally, time information of an electronic device is stored in a Complementary Metal Oxide Semiconductor (CMOS) therein, and when the electronic device is restarted, the CMOS information is erased, which may cause the time information of the electronic device to be lost, and further cause time-related services and even the whole electronic device to be inoperable. In order to solve the problem, manual time calibration is required each time after the device is restarted, and the time precision requirement of the electronic device cannot be met.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a time calibration method, a processor, and a time calibration system, so as to solve the problem of time information loss caused by restarting a device.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in a first aspect, an embodiment of the present invention provides a time calibration method, which is applied to a logic device of an electronic device, where the electronic device further includes an external storage medium, the logic device is electrically connected to the external storage medium, a CMOS circuit and a time calibration module are integrated in the logic device, and the method includes: when the logic device needs to be started, the time calibration module reads the first time recorded in the CMOS circuit and writes the first time into the external storage medium; when the logic device starts, the time calibration module reads a first time stored in the external storage medium; the time calibration module acquires the signal duration of an information clearing signal sent to the CMOS circuit by an external logic circuit electrically connected with the logic device, wherein the signal duration is the time interval between an enable clearing signal and a disable clearing signal sent to the CMOS circuit by the external logic circuit; the time calibration module acquires second time, wherein the second time is recorded after the CMOS circuit receives the de-enable clearing signal; the time calibration module writes back the sum of the first time, the signal duration, and the second time into the CMOS circuit.
In a second aspect, an embodiment of the present invention further provides a processor, which is applied to an electronic device, where the electronic device further includes an external storage medium, the processor is electrically connected to the external storage medium, a processor core, an internal memory, and a CMOS circuit are integrated in the processor, and the processor core is electrically connected to the CMOS circuit and the internal memory; the internal memory is to store machine-readable instructions; the processor core is to read the machine-readable instructions to perform: when the processor needs to be started, reading the first time recorded in the CMOS circuit and writing the first time into the external storage medium; reading a first time stored in the external storage medium when the processor is started; acquiring the signal duration of an information clearing signal sent to the CMOS circuit by an external logic circuit electrically connected with the processor, wherein the signal duration is the time interval between an enable clearing signal and a disable clearing signal sent to the CMOS circuit by the external logic circuit; acquiring second time, wherein the second time is recorded after the CMOS circuit receives the de-enable clearing signal; writing back the sum of the first time, the signal duration, and the second time into the CMOS circuit.
In a third aspect, an embodiment of the present invention further provides a time calibration system applied to an electronic device, where the time calibration system includes a processor and an external storage medium, the processor is electrically connected to the external storage medium, and a CMOS circuit and a processor core are integrated in the processor; the processor core is used for reading the first time recorded in the CMOS circuit and writing the first time into the external storage medium when the processor needs to be started; the external storage medium is used for storing a first time written by the processor core; the CMOS circuit is used for clearing the CMOS information after receiving an information clearing signal sent by an external logic circuit electrically connected with the processor, and retiming after receiving an enable-removing signal sent by the external logic circuit; the processor core is further configured to read a first time stored in the external storage medium when the processor is started, obtain a second time recorded by the CMOS circuit after receiving the enable removal signal, and write back a sum of the first time, a signal duration of the information removal signal, and the second time to the CMOS circuit.
Compared with the prior art, according to the time calibration method, the processor and the time calibration system provided by the embodiment of the invention, when the logic device of the electronic equipment needs to be started, the time calibration module integrated in the logic device reads the first time recorded in the CMOS circuit and writes the first time into the external storage medium; then, when the logic device is started, the time calibration module reads first time from an external storage medium, and acquires the signal duration of an information clearing signal sent to the CMOS circuit by the external logic circuit and second time recorded after the CMOS circuit receives the enable clearing signal; finally, the time calibration module writes back the sum of the first time, the signal duration and the second time to the CMOS circuit, so that the time information in the CMOS circuit can be accurately recovered. According to the embodiment of the invention, the logic device is externally connected with the external storage medium and the internal integrated time calibration module, so that the time information of the CMOS circuit can be automatically calibrated after the equipment is restarted, the time precision requirement of the electronic equipment is met, and the reliability is good.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a block diagram illustrating a time calibration system according to an embodiment of the present invention.
Fig. 2 shows a flowchart of a time calibration method provided by an embodiment of the present invention.
Fig. 3 shows a block schematic diagram of an electronic device provided by an embodiment of the present invention.
Icon: 10-time calibration system; 100-a processor; 101-CMOS circuits; 102-a processor core; 103-internal memory; 20-an external storage medium; 30-an external power supply; 200-a logic device; 201-time calibration module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
First embodiment
Referring to fig. 1, fig. 1 is a block diagram illustrating a time calibration system 10 according to an embodiment of the invention. The time calibration system 10 is applied to an electronic device, and the time calibration system 10 includes a processor 100, an external storage medium 20 and an external power supply 30, where the external storage medium 20 and the external power supply 30 are electrically connected to the processor 100.
In the embodiment of the present invention, the processor 100 is integrated with a CMOS circuit 101, a processor core 102 and an internal memory 103, the processor core 102 is electrically connected to the CMOS circuit 101, the internal memory 103 and the external storage medium 20, and the CMOS circuit 101 is electrically connected to the external power supply 30.
In an embodiment of the present invention, the CMOS circuit 101 may store device information of the processor 100, for example, hardware parameters, time information, and the like of the processor 100. The external power supply 30 is used to power the CMOS circuit 101 when the processor 100 is powered off to drive the CMOS circuit 101 to start timing after receiving the disable clear signal. As one embodiment, the external power source 30 may be a battery.
In an embodiment of the present invention, the internal memory 103 is used for storing machine readable instructions, and the machine readable instructions include at least one software functional module which can be stored in the internal memory 103 in a form of software or firmware (firmware) or solidified in an Operating System (OS) of the electronic device. Processor core 102 may read and execute the machine readable instructions.
The electronic device may be, but is not limited to, a server, a computer, a switch, a router, and the like. The processor 100 may be a Central Processing Unit (CPU), such as an X86CPU, which is currently commercially available. The internal Memory 103 may be a storage unit integrated into the processor 100, for example, a ROM (Read Only Memory), a RAM (Random Access Memory), a Cache Memory (Cache), and the like, and the processor core 102 may be a CPU core.
In the embodiment of the present invention, the processor core 102 is configured to read a first time recorded in the CMOS circuit 101 and write the first time into the external storage medium 20 when the processor 100 needs to be started. The time when the processor 100 needs to be started may be when the processor 100 receives a restart instruction, before the information clearing signal sent by the external logic circuit to the CMOS circuit 101 is asserted, the processor core 102 needs to read the first time recorded in the CMOS circuit 101 and write the first time into the external storage medium 20. The first time may be the time information of the processor 100 currently recorded by the CMOS circuit 101, and the first time may be represented by T1.
The electronic device may be a server, and correspondingly, when the processor 100 is powered on, the BIOS (Basic Input/Output System) stored in the external memory of the processor 100 is moved to the memory outside the processor 100, so that the processor 100 can be booted from the BIOS (Basic Input/Output System ), which is responsible for booting the processor 100, booting the operating System, and accessing the hardware interface by the operating System, and then the BIOS obtains the time stored by the CMOS circuit 101 and manages the services and logs under the BIOS; next, the BIOS reads secondary Boot software from another nonvolatile storage medium, and the Boot software checks whether the BIOS needs to be upgraded after being started. If the BIOS version is correct, the Boot software will continue to Boot the operating system without upgrading, and if the BIOS needs to be upgraded, the BIOS will perform a clear operation on the cmos information inside the processor 100 after the BIOS is upgraded.
Therefore, when the electronic device is a server, the processor core 102 is further configured to read the first time recorded in the CMOS circuit 101 and write the first time into the external storage medium 20 when the BIOS built into the external memory of the processor 100 is upgraded, that is, when an upgrade instruction is received.
The external storage medium 20 is used for storing the first time written by the processor core 102, and the external storage medium 20 may be a nonvolatile storage medium, such as a Flash memory.
The CMOS circuit 101 is used for clearing the CMOS information after receiving an information clearing signal sent by an external logic circuit electrically connected with the processor 100, and when the processor 100 needs to be started, the external logic circuit sends an enabling clearing signal to the CMOS circuit 101 to enable the information clearing signal to be effective so as to clear the CMOS information, and sends a disabling clearing signal to the CMOS circuit 101 to disable the information clearing signal after the signal duration time arrives. The signal duration of the information clear signal is the time interval between the enable clear signal and the disable clear signal sent by the external logic circuit to the CMOS circuit 101, and the signal duration can be represented by T0, T0 is a fixed value, for example, when the information clear signal is at a low level of 50ns, it indicates that the low level is applied for 50ns, and the low level is used to clear the CMOS information, and 50ns is the signal duration T0 of the information clear signal. T0 may be pre-stored in the BIOS, or in a fixed memory space of external storage medium 20, for retrieval during startup of processor 100.
The CMOS circuit 101 is also used for re-clocking after receiving a disable clear signal sent by an external logic circuit, i.e. after the information clear signal is disabled. At this time, the CMOS circuit 101 can still be clocked by the external power supply 30 due to the artificial or unexpected power failure of the processor 100, i.e. the time information in the CMOS circuit 101 continues to increase with the initial value as the base under the driving of the external power supply 30.
The processor core 102 is further configured to read a first time stored in the external storage medium 20 when the processor 100 is started, obtain a second time recorded by the CMOS circuit 101 after receiving the disable clear signal, and write back a sum of the first time, a signal duration of the information clear signal, and the second time to the CMOS circuit 101. Specifically, the second time may be a second time recorded by the CMOS circuit 101 after receiving the disable clear signal until the time of write back, and the second time may be represented by Δ t. The sum of the first time T1, the signal duration T0, and the second time Δ T may be denoted by T2, T2 ═ T1+ T0+ Δ T.
When the electronic device is a server, the external logic circuit sends a disable clear signal from the CMOS circuit 101 in the processor 100, and then cooperates with the processor 100 to enter a power-down restart sequence, so that the BIOS solidified in the external memory of the processor 100 is started after the processor 100 is restarted. That is, when the external logic sends the disable clear signal to the processor 100 to disable the information clear signal, the processor 100 is powered up and the BIOS is restarted. Therefore, the processor core 102 is further configured to read a first time stored in the external storage medium 20 when the BIOS is started, retrieve a second time Δ T recorded by the CMOS circuit 101 after receiving the disable clear signal, and write back the sum T2 of the first time T1, the signal duration T0, and the second time Δ T to the CMOS circuit 101, which is T1+ T0+ Δ T.
Since the first time is stored in the external storage medium 20, it is not cleared due to power down of the electronic device, and if the electronic device is normally powered off, the first time of the previous restart will still be stored in the external storage medium 20. At this time, if the electronic apparatus is turned on again, there may be a problem that the time in the CMOS circuit 101 is wrongly written due to the stored first time, resulting in inconsistency of the time information. To further ensure the reliability of the time alignment, the processor core 102 is further configured to read a first time in the CMOS circuit 101 when the processor 100 needs to be booted, write the first time and a time expiration flag into the external storage medium 20, where the time expiration flag may indicate that the processor 100 is cleared due to a restart (e.g., BIOS upgrade) in the CMOS circuit 101, and the first time corresponding to the time expiration flag is a time in the CMOS circuit 101 cleared due to the BIOS upgrade.
In this embodiment of the present invention, the processor core 102 is further configured to detect whether the external storage medium 20 stores a time expiration flag when the processor 100 is started, and if it is detected that the time expiration flag is stored in the external storage medium 20, indicating that the first time stored in the external storage medium 20 is a time when the BIOS upgrade is cleared, the processor core 102 reads the first time stored in the external storage medium 20; if it is detected that the time expiration flag is not stored in the external storage medium 20, it indicates that the first time is not stored in the external storage medium 20, or the stored first time is not the time for which the BIOS upgrade is cleared, at this time, the processor core 102 does not read the first time stored in the external storage medium 20, but directly controls the processor 100 to continue to start. When the processor core 102 reads the first time, which indicates that the processor 100 has recovered the time in the CMOS circuit 101, the failure flag in the external storage medium 20 is cleared, so as to avoid writing error time information into the CMOS circuit 101 when the subsequent electronic device is started after being normally shut down.
In an embodiment of the present invention, the internal memory 103 is configured to store machine-readable instructions, and the processor core 102 is configured to read the machine-readable instructions to perform: when the processor 100 needs to be started, reading the first time recorded in the CMOS circuit 101 and writing the first time into the external storage medium 20; reading a first time stored in the external storage medium 20 when the processor 100 is started; acquiring the signal duration of an information clearing signal sent to the CMOS circuit 101 by an external logic circuit electrically connected with the processor 100, wherein the signal duration is the time interval between an enable clearing signal and a disable clearing signal sent to the CMOS circuit 101 by the external logic circuit; acquiring a second time, wherein the second time is recorded after the CMOS circuit 101 receives the enable clearing signal; the sum of the first time, the signal duration, and the second time is written back into the CMOS circuit 101.
Compared with the prior art, the embodiment of the invention has the following beneficial effects:
firstly, after the BIOS upgrade cured in the external memory of the processor 100 is completed and before the information clearing signal sent by the external logic circuit becomes effective, the first time recorded in the CMOS circuit 101 is read and written into the external storage medium 20, and after the BIOS is started, the sum of the first time stored in the external storage medium 20, the signal duration of the information clearing signal, and the second time recorded by the CMOS circuit 101 after the information clearing signal is invalid is written back into the CMOS circuit 101, thereby effectively solving the problem of time information loss of the electronic device due to the BIOS upgrade. The electronic equipment can acquire accurate time before the start of the operating system is completed. In addition, the accuracy of the time information is ensured in the starting stage of the electronic equipment, and the reliable starting of the electronic equipment can be ensured.
Secondly, the embodiment of the invention realizes the high-precision and high-reliability calibration of the time information of the electronic equipment, thereby ensuring that the virtual machine application running on the fusion equipment can acquire reliable system time from the fusion equipment, and further ensuring the reliable running of the application.
Second embodiment
Referring to fig. 2, fig. 2 shows a flowchart of a time calibration method according to an embodiment of the present invention, the time calibration method is applied to a logic device 200 of the electronic apparatus shown in fig. 3, the electronic apparatus further includes an external storage medium 20, an external power supply 30 and an external logic circuit, a CMOS circuit 101 and a time calibration module 201 are integrated in the logic device 200, the time calibration module 201 is electrically connected to the external storage medium 20, and the CMOS circuit 101 is electrically connected to the time calibration module 201, the external power supply 30 and the external logic circuit. The electronic Device may be a server, a computer, a switch, a router, etc., the Logic Device 200 may be a Programmable Logic Device such as an FPGA (Field-Programmable Gate Array) or a CPLD (Complex Programmable Logic Device), and the external power source 30 may be a battery. The time calibration method comprises the following steps:
step S101, when the logic device needs to be started, the time calibration module reads the first time recorded in the CMOS circuit and writes the first time into an external storage medium.
In the embodiment of the present invention, since the external logic circuit sends the information clearing signal to the logic device 200 to clear the time information in the CMOS circuit 101 when the electronic device is restarted, in order to ensure the time accuracy requirement of the electronic device, the time calibration module 201 needs to read the first time recorded in the CMOS circuit 101 and write the first time into the external storage medium 20 before the information clearing signal sent by the external logic circuit becomes effective.
If the electronic device is a server, after the BIOS that is solidified in the external memory of the logic device 200 is upgraded, the external logic circuit sends an information clearing signal to the logic device 200 to clear the CMOS information of the CMOS circuit 101, so the time alignment module 201 needs to read the first time recorded in the CMOS circuit 101 and write the first time into the external storage medium 20 after the BIOS is upgraded and before the information clearing signal sent by the external logic circuit is valid.
To further ensure the reliability of the time calibration, when the logic device 200 needs to be started, the time calibration module 201 reads a first time in the CMOS circuit 101, and then writes the first time and a time expiration flag into the external storage medium 20, where the time expiration flag may indicate that the processor 100 is cleared due to a restart (e.g., BIOS upgrade) of the CMOS circuit 101, and the first time corresponding to the time expiration flag is a time in the CMOS circuit 101 cleared due to the BIOS upgrade.
Step S102, when the logic device is started, the time calibration module reads the first time stored in the external storage medium.
In the embodiment of the present invention, after the external logic circuit sends the disable clear signal to the logic device 200 to disable the information clear signal, the time calibration module 201 reads the first time stored in the external storage medium 20.
If the electronic device is a server, after the external logic circuit sends the enable clear signal to the logic device 200 to disable the information clear signal, the logic device 200 is powered on, and then the BIOS is restarted, and when the BIOS is started, the time calibration module 201 reads the first time stored in the external storage medium 20.
In order to further ensure the reliability of the time calibration, before reading the first time stored in the external storage medium 20, the logic device 200 needs to detect whether the external storage medium 20 stores a time expiration flag, and if detecting that the time expiration flag stored in the external storage medium 20 indicates that the first time stored in the external storage medium 20 is the time for which the BIOS upgrade is cleared, read the first time stored in the external storage medium 20; if it is detected that the time expiration flag is not stored in the external storage medium 20, indicating that the first time is not stored in the external storage medium 20, or the stored first time is not the time for which the BIOS upgrade is cleared, controlling the logic device 200 to continue booting.
Step S103, the time calibration module obtains the signal duration of the information clearing signal sent to the CMOS circuit by the external logic circuit electrically connected with the logic device, wherein the signal duration is the time interval between the enabling clearing signal and the disabling clearing signal sent to the CMOS circuit by the external logic circuit.
In the embodiment of the present invention, when the electronic device is restarted, the external logic circuit sends an information clearing signal to the logic device 200 to clear the time information in the CMOS circuit 101, the signal duration of the information clearing signal is a fixed value, for example, 50ns, and the signal duration is the time interval between the enable clearing signal and the disable clearing signal sent by the external logic circuit to the CMOS circuit 101.
If the electronic device is a server, after the BIOS that is solidified in the external memory of the logic device 200 is upgraded, the external logic circuit sends an enable clear signal to the CMOS circuit 101 to enable the information clear signal to be valid to clear the CMOS information, and sends a disable clear signal to the CMOS circuit 101 to disable the information clear signal after a signal duration (for example, 50ns) arrives, and since the CMOS circuit 101 cannot record time within the signal duration, the logic device 200 needs to acquire the signal duration of the information clear signal sent from the external logic circuit to the CMOS circuit 101 in order to guarantee the time accuracy requirement of the electronic device.
It should be noted that the signal duration is a certain value, and the information clearing signal sent by the external logic circuit to the logic device 200 may itself include the signal duration T0, for example, 50 ns.
And step S104, the time calibration module acquires a second time, wherein the second time is the time recorded after the CMOS circuit receives the de-enable clearing signal.
In the embodiment of the present invention, after the external logic circuit sends the disable clear signal to the logic device 200 to disable the information clear signal, the CMOS circuit 101 counts again, and then the logic device 200 restarts, if the logic device 200 is powered off at this time, the CMOS circuit 101 can count under the driving of the external power supply 30, that is, once the information clear signal fails, even if the logic device 200 is powered off manually or accidentally, the CMOS circuit 101 can still count again under the action of the external power supply 30, that is, the time information in the CMOS circuit 101 under the driving of the external power supply 30 continues to increase with the initial value as the base. The second time may be the difference between the CMOS circuit 101 before the information clear signal is deactivated to the time of write back.
In step S105, the time calibration module writes back the sum of the first time, the signal duration, and the second time to the CMOS circuit.
In the embodiment of the present invention, the time calibration module 201 obtains the first time, the signal duration, and the second time, sums the first time, the signal duration, and the second time, and writes the result into the CMOS circuit 101, where the calibration accuracy may reach ns level, so that the time finally written into the CMOS circuit 101 is accurate time information, and high-accuracy and high-reliability calibration of time information of an electronic device is implemented.
In summary, the time calibration method, the processor and the time calibration system provided in the embodiments of the present invention are applied to a logic device of an electronic device, the electronic device further includes an external storage medium, the logic device is electrically connected to the external storage medium, a CMOS circuit and a time calibration module are integrated in the logic device, and the method includes: when the logic device needs to be started, the time calibration module reads the first time recorded in the CMOS circuit and writes the first time into an external storage medium; when the logic device is started, the time calibration module reads first time stored in an external storage medium; the time calibration module acquires the signal duration of an information clearing signal sent to the CMOS circuit by an external logic circuit electrically connected with the logic device, wherein the signal duration is the time interval between an enable clearing signal and a disable clearing signal sent to the CMOS circuit by the external logic circuit; the time calibration module acquires second time, wherein the second time is recorded after the CMOS circuit receives the de-enable clearing signal; the time alignment module writes back the sum of the first time, the signal duration, and the second time into the CMOS circuit. The embodiment of the invention can automatically calibrate the time information of the CMOS circuit after the equipment is restarted, meets the time precision requirement of the electronic equipment and has good reliability.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Claims (9)
1. A time calibration method is applied to a logic device of an electronic device, the electronic device further comprises an external storage medium, the logic device is electrically connected with the external storage medium, a CMOS circuit and a time calibration module are integrated in the logic device, and a BIOS is solidified in the external storage medium, the method comprises the following steps:
when the logic device needs to be started, the time calibration module reads the first time recorded in the CMOS circuit and writes the first time into the external storage medium, wherein when the logic device needs to be started, the time calibration module is after the BIOS solidified in the external storage medium is upgraded and before an information clearing signal sent to the CMOS circuit by the external logic circuit is effective;
when the logic device starts, the time calibration module reads a first time stored in the external storage medium;
the time calibration module acquires the signal duration of an information clearing signal sent to the CMOS circuit by an external logic circuit electrically connected with the logic device, wherein the signal duration is the time interval between an enabling clearing signal and a disabling clearing signal sent to the CMOS circuit by the external logic circuit, the enabling clearing signal enables the information clearing signal to be effective to clear the CMOS information, and the disabling clearing signal disables the information clearing signal;
the time calibration module acquires second time, wherein the second time is recorded after the CMOS circuit receives the de-enable clearing signal;
the time calibration module writes back the sum of the first time, the signal duration, and the second time into the CMOS circuit.
2. The method of claim 1, wherein the step of the time calibration module reading a first time recorded in the CMOS circuit and writing to the storage medium when the logic device needs to boot comprises:
when the logic device needs to be started, the time calibration module reads first time in the CMOS circuit;
writing the first time and time lapse flag to the external storage medium;
the step of reading, by the time calibration module, the first time stored in the external storage medium when the logic device is started includes:
when the logic device is started, the time calibration module detects whether a time invalidation mark is stored in the external storage medium;
if the external storage medium is detected to be stored with the time invalidation mark, reading the first time stored in the external storage medium;
and if the time failure mark is not detected to be stored in the external storage medium, controlling the logic device to continue to start.
3. The method of claim 1, wherein the electronic device is a server;
the method for reading the first time recorded in the CMOS circuit and writing the first time into the external storage medium by the time calibration module when the logic device needs to be started includes:
when the BIOS solidified in the external memory of the logic device is upgraded, the time calibration module reads the first time recorded in the CMOS circuit and writes the first time into the external storage medium;
the manner in which the time calibration module reads the first time stored in the external storage medium when the logic device is started includes: when the BIOS is started, the time calibration module reads the first time stored in the external storage medium.
4. A processor is characterized by being applied to electronic equipment, and further comprising an external storage medium, wherein the processor is electrically connected with the external storage medium, a processor core, an internal memory and a CMOS circuit are integrated in the processor, the processor core is electrically connected with the CMOS circuit and the internal memory, and the BIOS is solidified in the external storage medium;
the internal memory is to store machine-readable instructions;
the processor core is to read the machine-readable instructions to perform:
when the processor needs to be started, reading the first time recorded in the CMOS circuit and writing the first time into the external storage medium, wherein when the processor needs to be started, the time is after the BIOS solidified in the external storage medium is upgraded and before an information clearing signal sent to the CMOS circuit by an external logic circuit is effective;
reading a first time stored in the external storage medium when the processor is started;
acquiring the signal duration of an information clearing signal sent to the CMOS circuit by an external logic circuit electrically connected with the processor, wherein the signal duration is the time interval between an enabling clearing signal and a disabling clearing signal sent to the CMOS circuit by the external logic circuit, the enabling clearing signal enables the information clearing signal to take effect to clear the CMOS information, and the disabling clearing signal disables the information clearing signal;
acquiring second time, wherein the second time is recorded after the CMOS circuit receives the de-enable clearing signal;
writing back the sum of the first time, the signal duration, and the second time into the CMOS circuit.
5. A time calibration system is applied to electronic equipment and comprises a processor and an external storage medium, wherein the processor is electrically connected with the external storage medium, a CMOS circuit and a processor core are integrated in the processor, and a BIOS is solidified in the external storage medium;
the processor core is used for reading the first time recorded in the CMOS circuit and writing the first time into the external storage medium when the processor needs to be started, wherein the time when the processor needs to be started refers to the time when the BIOS solidified in the external storage medium is upgraded and before an information clearing signal sent to the CMOS circuit by the external logic circuit takes effect;
the external storage medium is used for storing a first time written by the processor core;
the CMOS circuit is used for clearing the CMOS information after receiving an information clearing signal sent by an external logic circuit electrically connected with the processor, and retiming after receiving an enable-removing signal sent by the external logic circuit;
the processor core is further configured to read a first time stored in the external storage medium when the processor is started, obtain a second time recorded by the CMOS circuit after receiving the enable removal signal, and write back a sum of the first time, a signal duration of the information removal signal, and the second time to the CMOS circuit, where the signal duration is a time interval between an enable removal signal and a enable removal signal sent by the external logic circuit to the CMOS circuit, the enable removal signal validates the information removal signal to remove the CMOS information, and the enable removal signal disables the information removal signal.
6. The time calibration system of claim 5, wherein the processor core is further configured to read a first time in the CMOS circuit when the processor needs to boot up, write the first time and a time spent flag to the external storage medium;
the processor core is further configured to detect whether the external storage medium stores a time invalidation flag when the processor is started, read a first time stored in the external storage medium if it is detected that the external storage medium stores the time invalidation flag, and control the processor to continue to be started if it is detected that the external storage medium does not store the time invalidation flag.
7. The time calibration system of claim 5, wherein the electronic device is a server, the processor core is further configured to read a first time recorded in the CMOS circuit and write to the external storage medium after completion of the BIOS upgrade cured into the processor external memory, and to read the first time stored in the external storage medium when the BIOS boots.
8. The time calibration system of claim 5, further comprising an external power supply electrically connected to the CMOS circuitry, the external power supply to power the CMOS circuitry when the processor is powered down to drive the CMOS circuitry to begin timing upon receiving the disable clear signal.
9. The time calibration system of claim 8, wherein the external power source is a battery.
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