CN108873668A - Time calibrating method, processor and time calibration system - Google Patents
Time calibrating method, processor and time calibration system Download PDFInfo
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- CN108873668A CN108873668A CN201811005223.1A CN201811005223A CN108873668A CN 108873668 A CN108873668 A CN 108873668A CN 201811005223 A CN201811005223 A CN 201811005223A CN 108873668 A CN108873668 A CN 108873668A
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- time
- storage medium
- cmos circuit
- processor
- exterior storage
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- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G5/00—Setting, i.e. correcting or changing, the time-indication
Abstract
The present embodiments relate to fields of communication technology, a kind of time calibrating method, processor and time calibration system are provided, when the logic device of electronic equipment needs to start, it is integrated into the time calibration module inside logic device and reads the first time recorded in cmos circuit and be written in exterior storage medium；When logic device starting, time calibration module is read at the first time from exterior storage medium, and obtain the erasing of information signal that outer logic circuit is sent to cmos circuit signal duration and cmos circuit receiving enable clear signal after the second time for recording；Finally, time calibration module by the first time, the sum of signal duration and second time be written back in cmos circuit, thus can temporal information in Exact recovery cmos circuit.The embodiment of the present invention can calibrate automatically the temporal information of cmos circuit after equipment is restarted, and meet the time precision requirement of electronic equipment, have good reliability.
Description
Technical field
The present embodiments relate to fields of communication technology, timely in particular to a kind of time calibrating method, processor
Between calibration system.
Background technique
With the development of science and technology, more and more electronic equipments are applied in people's lives and work.In general, electronics
CMOS (Complementary Metal Oxide Semiconductor, the complementation of the temporal information storage of equipment inside it
Metal-oxide semiconductor (MOS)) in, when electronic equipment is restarted, it can be purged operation to CMOS information, will lead to electronics in this way
The temporal information of equipment is lost, and then the even entire electronic equipment of the service of time correlation is caused to be unable to run.In order to solve this
One problem is required to the manual calibration time every time after equipment is restarted, and is not able to satisfy the time precision requirement of electronic equipment.
Summary of the invention
The embodiment of the present invention is designed to provide a kind of time calibrating method, processor and time calibration system, to
It solves the problems, such as to cause temporal information to be lost when equipment is restarted.
To achieve the goals above, technical solution used in the embodiment of the present invention is as follows：
In a first aspect, the embodiment of the invention provides a kind of time calibrating method, applied to the logic device of electronic equipment,
The electronic equipment further includes exterior storage medium, and the logic device is electrically connected with the exterior storage medium, the logic
Device has been internally integrated cmos circuit and time calibration module, the method includes：When the logic device needs to start, institute
Time calibration module is stated to read the first time recorded in the cmos circuit and be written in the exterior storage medium；When described
When logic device starts, the time calibration module reads the first time stored in the exterior storage medium；The time
Calibration module obtains the erasing of information letter that the outer logic circuit being electrically connected with the logic device is sent to the cmos circuit
Number signal duration, the signal duration be the outer logic circuit is sent to the cmos circuit it is enabled clearly
Except signal and go the time interval between enabled clear signal；The time calibration module obtained for the second time, wherein described the
Two times were that the cmos circuit is receiving the time for going to enable to record after clear signal；The time calibration module will
The sum of the first time, signal duration and second time are written back in the cmos circuit.
Second aspect, the embodiment of the invention also provides a kind of processors, are applied to electronic equipment, the electronic equipment is also
Including exterior storage medium, the processor is electrically connected with the exterior storage medium, and the processor has been internally integrated processing
Device core, internal storage and cmos circuit, the processor core are electrically connected with the cmos circuit and the internal storage；
The internal storage is for storing machine readable instructions；The processor core is for reading the machine readable instructions, to hold
Row：When the processor needs to start, reads the first time recorded in the cmos circuit and the external storage is written
In medium；When processor starting, the first time stored in the exterior storage medium is read；It obtains and the processing
The signal duration for the erasing of information signal that the outer logic circuit of device electrical connection is sent to the cmos circuit, the signal
Duration be the enabled clear signal that is sent to the cmos circuit of the outer logic circuit and going enable clear signal it
Between time interval；Obtained for the second time, wherein second time be the cmos circuit receive it is described go it is enabled clear
Except the time recorded after signal；The sum of the first time, signal duration and second time are written back to the CMOS electricity
Lu Zhong.
The third aspect, the embodiment of the invention also provides a kind of time calibration systems, are applied to electronic equipment, the time
Calibration system includes processor and exterior storage medium, and the processor is electrically connected with the exterior storage medium, the processing
Device has been internally integrated cmos circuit and processor core；The processor core is used for when the processor needs to start, and reads institute
It states the first time recorded in cmos circuit and is written in the exterior storage medium；The exterior storage medium is for storing institute
State the first time of processor core write-in；The cmos circuit is for receiving the outer logic circuit being electrically connected with the processor
CMOS information is removed after the erasing of information signal of transmission, and is believed receiving the removing of going to enable that the outer logic circuit is sent
Reclocking after number；The processor core is also used to read when the processor starts and store in the exterior storage medium
At the first time, then obtain the cmos circuit receive it is described go enabled clear signal after the second time for recording, and by institute
State at the first time, the sum of the signal duration of erasing of information signal and second time is written back in the cmos circuit.
Compared with the prior art, a kind of time calibrating method, processor and time calibration system provided in an embodiment of the present invention,
When the logic device of electronic equipment needs to start, it is integrated into the time calibration module inside logic device and reads in cmos circuit
The first time of record is simultaneously written in exterior storage medium；Then, when logic device starts, time calibration module is deposited from outside
It is read at the first time in storage media, and the signal for obtaining the erasing of information signal that outer logic circuit is sent to cmos circuit continues
The second time that time and cmos circuit record after receiving enabled clear signal；Finally, time calibration module is by
The sum of one time, signal duration and second time are written back in cmos circuit, thus can be in Exact recovery cmos circuit
Temporal information.The embodiment of the present invention by the external exterior storage medium of logic device and being internally integrated time calibration module,
The temporal information that cmos circuit can be calibrated automatically after equipment is restarted, meets the time precision requirement of electronic equipment, has good
Good reliability.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 shows the block diagram of time calibration system provided in an embodiment of the present invention.
Fig. 2 shows time calibrating method flow charts provided in an embodiment of the present invention.
Fig. 3 shows the block diagram of electronic equipment provided in an embodiment of the present invention.
Icon：10- time calibration system；100- processor；101-CMOS circuit；102- processor core；It is deposited inside 103-
Reservoir；20- exterior storage medium；30- external power supply；200- logic device；201- time calibration module.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It should be noted that：Similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, term " first ", " second " etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
First embodiment
Fig. 1 is please referred to, Fig. 1 shows the block diagram of time calibration system 10 provided in an embodiment of the present invention.Time
Calibration system 10 is applied to electronic equipment, and time calibration system 10 includes processor 100, exterior storage medium 20 and external power supply
30, exterior storage medium 20 and external power supply 30 are electrically connected with processor 100.
In embodiments of the present invention, processor 100 has been internally integrated cmos circuit 101, processor core 102 and storage inside
Device 103, processor core 102 are electrically connected with cmos circuit 101, internal storage 103 and exterior storage medium 20, cmos circuit
101 are electrically connected with external power supply 30.
In embodiments of the present invention, cmos circuit 101 can store the facility information of processor 100, for example, processor
100 hardware parameter, temporal information etc..External power supply 30 is used to power when processor 100 powers off for cmos circuit 101, with
Driving cmos circuit 101 starts timing after receiving enabled clear signal.As an implementation, external power supply 30 can
To be battery.
In embodiments of the present invention, for storing machine readable instructions, which includes internal storage 103
At least one can be stored in internal storage 103 or be solidificated in electronic equipment in the form of software or firmware (firmware)
Software function module in operating system (operating system, OS).Processor core 102 can read the machine readable finger
It enables and is executed.
Electronic equipment may be, but not limited to, server, computer, interchanger, router etc..Processor 100 can be
CPU (Central Processing Unit, central processing unit), for example, common X86CPU currently on the market.Storage inside
Device 103 can be integrated into a storage unit inside processor 100, and for example, ROM (Read Only Memory, it is read-only to deposit
Reservoir), RAM (Random Access Memory, random access memory), cache memory (Cache：Cache Memory)
Deng processor core 102 can be CPU core.
In embodiments of the present invention, processor core 102 is used for when processor 100 needs to start, and reads cmos circuit 101
The first time of middle record is simultaneously written in exterior storage medium 20.Processor 100 is can be when needing to start when processor 100 connects
When receiving instruction of restarting, before outer logic circuit comes into force to the erasing of information signal that cmos circuit 101 is sent, processor core
102 need to read the first time recorded in cmos circuit 101 and are written in exterior storage medium 20.It can be at the first time
The temporal information of the processor 100 of 101 current record of cmos circuit can be indicated at the first time with T1.
Electronic equipment can be server, corresponding, when processor 100 powers on, be stored in outside processor 100 and deposit
BIOS (Basic Input/Output System, basic input output system) in reservoir can be shifted to outside processor 100
In the memory in portion, such processor 100 can be from BIOS (Basic Input/Output System, basic input and output system
System) it is booted up, BIOS is responsible for the interface of the starting of processor 100, the guidance of operating system and operating system access hardware,
Later BIOS obtain cmos circuit 101 store time, and under BIOS service and log be managed；Next, BIOS
Secondary boot software Boot software is read from other non-volatile memory mediums, can verify whether BIOS needs after the starting of Boot software
Upgrade.If bios version is correct, do not need to upgrade, Boot software will continue to guidance os starting, if BIOS is needed
Upgrade, then after the completion of BIOS upgrades, operation can be purged to the COMS information inside processor 100.
Therefore, when electronic equipment is server, processor core 102, which is also used to work as, is cured to 100 external storage of processor
After the completion of BIOS upgrading in device, that is, when receiving upgrade command, read the first time recorded in cmos circuit 101 and write-in
In exterior storage medium 20.
Exterior storage medium 20 is used for the first time that storage processor core 102 is written, and exterior storage medium 20 can be
Non-volatile memory medium, for example, flash storage etc..
Cmos circuit 101 is used to receive the erasing of information signal that the outer logic circuit being electrically connected with processor 100 is sent
CMOS information is removed afterwards, and when processor 100 needs to start, outer logic circuit, which sends enabled remove to cmos circuit 101, to be believed
Number erasing of information signal is made to come into force to remove CMOS information and send after signal duration reaches to cmos circuit 101
Go enabled clear signal that breath clear signal is made to fail.The signal duration of erasing of information signal is outer logic circuit to CMOS
The enabled clear signal and go the time interval between enabled clear signal that circuit 101 is sent, which can use
T0 indicates that T0 is a fixed value, for example, erasing of information signal is low level 50ns, then shows that the time of low level effect is
50ns, low level are used to remove CMOS information, and 50ns is exactly the signal duration T0 of erasing of information signal.T0 can be deposited in advance
Storage is in BIOS or in a fixed storage space of exterior storage medium 20, to obtain during processor 100 starts
It takes.
Cmos circuit 101 is also used in the reclocking after going enabled clear signal for receiving outer logic circuit transmission,
That is the reclocking after erasing of information Signal Fail.At this point, processor 100 is due to artificial or accident power-off, cmos circuit 101 is still
It so can the timing under the driving of external power supply 30, the i.e. temporal information under the driving of external power supply 30 in cmos circuit 101
Continue to increase using initial value as radix.
Processor core 102 is also used to read the first time stored in exterior storage medium 20 when processor 100 starts,
The second time that cmos circuit 101 records after receiving enabled clear signal is obtained again, and will first time, erasing of information
The sum of the signal duration of signal and the second time are written back in cmos circuit 101.Specifically, the second time can be
The second time that cmos circuit 101 records before receiving enabled clear signal post-arrival time write-back, the second time can be used
Δ t is indicated.The sum of first time T1, signal duration T0 and the second time Δ t can indicate with T2, T2=T1+T0+ Δ t.
When electronic equipment is server, outer logic circuit goes enabled clear from the transmission of cmos circuit 101 in processor 100
After signal, cooperation processor 100 restarts timing into lower electricity, to solidify outside processor 100 after processor 100 is restarted
BIOS starting in memory.That is, when outer logic circuit goes enabled clear signal to make information to the transmission of processor 100
After clear signal failure, processor 100 is powered on, and BIOS restarts later.Therefore, processor core 102 is also used to open as BIOS
The first time stored in exterior storage medium 20 is read when dynamic, then is obtained cmos circuit 101 and received enabled removing letter
The the second time Δ t recorded after number, and by the sum of first time T1, signal duration T0 and the second time Δ t T2=T1+T0
+ Δ t is written back in cmos circuit 101.
Due to being stored in exterior storage medium 20 at the first time, will not because of electronic equipment power down and remove, that
, if electronic equipment is normally to shut down, previous first time when restarting can still be stored in exterior storage medium 20.This
When, if electronic equipment is switched on again, may be by first time for being stored and the time in cmos circuit 101 wrongly writes,
Lead to the problem that temporal information is inconsistent.In order to further ensure that the reliability of time calibration, processor core 102 is also used to when place
When reason device 100 needs to start, the first time in cmos circuit 101 is read, it will be at the first time and outside time failure mark write-in
In portion's storage medium 20, time failure mark can indicate processor 100 due to restarting (for example, BIOS upgrades) cmos circuit
Time in 101 is removed, and first time corresponding with time failure mark is in cmos circuit 101 since BIOS upgrades quilt
The time of removing.
In embodiments of the present invention, processor core 102 is also used to detect exterior storage medium 20 when processor 100 starts
Having time failure mark whether is stored, having time failure mark is stored in exterior storage medium 20 if detecting, shows that outside is deposited
What is stored in storage media 20 is since BIOS upgrades the time removed at the first time, and processor core 102 reads outside and deposits at this time
The first time stored in storage media 20；If detecting not stored time failure mark in exterior storage medium 20, show outside
Not stored first time in storage medium 20, or the first time of storage are not due to the time that BIOS upgrading is removed, this
When processor core 102 to the first time stored in exterior storage medium 20 without reading, but directly control processor 100
Continue to start.When processor core 102 reads out first time, illustrate that processor 100 is extensive by the time in cmos circuit 101
It is multiple, then the invalid markers in exterior storage medium 20 are removed, to CMOS electricity when avoiding starting after Subsequent electronic equipment normal shutdown
Write error temporal information in road 101.
In embodiments of the present invention, internal storage 103 is for storing machine readable instructions, and processor core 102 is for reading
The machine readable instructions are taken, to execute：When processor 100 needs to start, the first time recorded in cmos circuit 101 is read
And it is written in exterior storage medium 20；When processor 100 starts, the first time stored in exterior storage medium 20 is read；
The signal for obtaining the erasing of information signal that the outer logic circuit being electrically connected with processor 100 is sent to cmos circuit 101 continues
Time, signal duration are the enabled clear signal that outer logic circuit is sent to cmos circuit 101 and enabled remove are gone to believe
Time interval between number；Obtained for the second time, wherein the second time was that cmos circuit 101 is receiving enabled removing letter
The time recorded after number；The sum of first time, signal duration and second time are written back in cmos circuit 101.
Compared with prior art, the embodiment of the present invention has the advantages that：
Firstly, when be cured in 100 external memory of processor BIOS upgrading after the completion of and outer logic circuit send
Erasing of information signal come into force before, read first time for recording in cmos circuit 101 and be written in exterior storage medium 20,
BIOS starting after, by the first time stored in exterior storage medium 20, erasing of information signal signal duration and
The sum of the second time that cmos circuit 101 records after erasing of information Signal Fail is written back in cmos circuit 101, effectively solves
Temporal information caused by electronic equipment upgrades due to BIOS loses problem.Guarantee electronic equipment before os starting completion
Precise time can be obtained.In addition, ensuring the accuracy of temporal information in electronic equipment startup stage, it is ensured that electronics is set
Standby reliable starting.
Secondly, the embodiment of the present invention realizes the highly reliable calibration of high-precision of electronic equipment temporal information, therefore can guarantee
The virtual machine application run on fusion device can obtain reliable system time from fusion device, so guarantee application can
By operation.
Second embodiment
Referring to figure 2., Fig. 2 shows time calibrating method flow chart provided in an embodiment of the present invention, the time calibration sides
Method is applied to the logic device 200 of electronic equipment shown in Fig. 3, which further includes exterior storage medium 20, external electrical
Source 30 and outer logic circuit, logic device 200 have been internally integrated cmos circuit 101 and time calibration module 201, time calibration
Module 201 is electrically connected with exterior storage medium 20, and cmos circuit 101 is patrolled with time calibration module 201, external power supply 30 and outside
Circuit is collected to be electrically connected.Electronic equipment can be server, computer, interchanger, router etc., and logic device 200 can be
FPGA (Field-Programmable Gate Array, field programmable gate array) or CPLD (Complex
Programmable Logic Device, Complex Programmable Logic Devices) etc. programmable logic device, external power supply 30 can be with
It is battery.The time calibrating method includes the following steps：
Step S101, when logic device needs to start, when time calibration module reads first recorded in cmos circuit
Between and be written in exterior storage medium.
In embodiments of the present invention, when being restarted due to electronic equipment, outer logic circuit can be sent to logic device 200 to be believed
Breath clear signal removes the temporal information in cmos circuit 101, therefore, in order to guarantee the time precision requirement of electronic equipment,
Before the erasing of information signal that outer logic circuit is sent comes into force, time calibration module 201 needs to read in cmos circuit 101
The first time of record is simultaneously written in exterior storage medium 20.
If electronic equipment is server, after the completion of the BIOS upgrading being cured in 200 external memory of logic device, outside
Portion's logic circuit can remove the CMOS information of cmos circuit 101 to the transmission erasing of information signal of logic device 200, therefore, when
Between calibration module 201 need BIOS upgrading after the completion of and external logic single channel send erasing of information signal come into force before, read
It takes the first time recorded in the cmos circuit 101 and is written in exterior storage medium 20.
In order to further ensure that the reliability of time calibration, when logic device 200 needs to start, time calibration module
201 read the first time in cmos circuit 101, then will first time and time failure mark write-in exterior storage medium 20
In, time failure mark can indicate processor 100 due to restarting the time quilt in (for example, BIOS upgrades) cmos circuit 101
It removes, first time corresponding with time failure mark is in cmos circuit 101 since BIOS upgrades the time removed.
Step S102, when logic device starting, when time calibration module reads first stored in exterior storage medium
Between.
In embodiments of the present invention, when outer logic circuit goes enabled clear signal to make information to the transmission of logic device 200
After clear signal failure, time calibration module 201 reads the first time stored in exterior storage medium 20.
If electronic equipment is server, when outer logic circuit goes enabled clear signal to make letter to the transmission of logic device 200
After ceasing clear signal failure, logic device 200 is powered on, and BIOS restarts later, when BIOS starting, time calibration module
The first time stored in 201 reading exterior storage mediums 20.
In order to further ensure that the reliability of time calibration, logic device 200 stores in reading exterior storage medium 20
First time before, time calibration module 201 also need to detect in exterior storage medium 20 whether store having time failure mark
Will stores having time failure mark if detecting, shows store in exterior storage medium 20 first in exterior storage medium 20
Time is then to read the first time stored in exterior storage medium 20 since BIOS upgrades the time removed；If detecting
Not stored time failure mark, shows not stored first time, Huo Zhecun in exterior storage medium 20 in exterior storage medium 20
The first time of storage is not due to BIOS and upgrades the time removed, then controls the logic device 200 and continue to start.
Step S103, time calibration module obtain the outer logic circuit being electrically connected with logic device and send to cmos circuit
Erasing of information signal signal duration, signal duration be outer logic circuit is sent to cmos circuit it is enabled clearly
Except signal and go the time interval between enabled clear signal.
In embodiments of the present invention, when electronic equipment is restarted, it is clear that outer logic circuit can send information to logic device 200
The temporal information in cmos circuit 101 is removed except signal, the signal duration of erasing of information signal is a fixed value, example
Such as, 50ns, signal duration are the enabled clear signal that outer logic circuit is sent to cmos circuit 101 and go to enable removing
Time interval between signal.
If electronic equipment is server, after the completion of the BIOS upgrading being cured in 200 external memory of logic device, outside
Portion's logic circuit to cmos circuit 101 send enabled clear signal so that erasing of information signal is come into force with remove CMOS information and
Enabled clear signal is gone to make erasing of information signal to the transmission of cmos circuit 101 after signal duration (for example, 50ns) arrival
Failure, since cmos circuit 101 can not record the time in signal duration, therefore in order to guarantee that the time precision of electronic equipment is wanted
It asks, when the signal that logic device 200 needs to obtain the erasing of information signal that outer logic circuit is sent to cmos circuit 101 continues
Between.
It should be noted that signal duration is a determining value, outer logic circuit can be sent to logic device 200
Erasing of information signal itself may include signal duration T0, for example, 50ns.
Step S104, time calibration module obtained for the second time, wherein the second time was that cmos circuit makes receiving
The time recorded after energy clear signal.
In embodiments of the present invention, when outer logic circuit goes enabled clear signal to make information to the transmission of logic device 200
After clear signal failure, 101 reclocking of cmos circuit, logic device 200 is restarted later, if logic device 200 is disconnected at this time
Electricity, then cmos circuit 101 can the timing under the driving of external power supply 30, that is to say, that once erasing of information Signal Fail, i.e.,
Make logic device 200 due to artificial or accident power-off, cmos circuit 101 still can be counted again under the action of external power supply 30
When, i.e., the temporal information under the driving of external power supply 30 in cmos circuit 101 continues to increase using initial value as radix.When second
Between can be difference of the cmos circuit 101 between before erasing of information invalidating signal to time write-back.
The sum of first time, signal duration and second time are written back to CMOS by step S105, time calibration module
In circuit.
In embodiments of the present invention, time calibration module 201 get at the first time, signal duration and when second
Between, it sums to first time, signal duration and the second time, and result is write in cmos circuit 101, calibration essence
Degree can achieve ns grades, ensures that the time in final write-in cmos circuit 101 is accurate temporal information in this way, realizes
The highly reliable calibration of the high-precision of electronic equipment temporal information.
In conclusion a kind of time calibrating method, processor and time calibration system provided in an embodiment of the present invention, described
Time calibrating method is applied to the logic device of electronic equipment, and electronic equipment further includes exterior storage medium, logic device and outer
The electrical connection of portion's storage medium, logic device have been internally integrated cmos circuit and time calibration module, the method includes：Work as logic
When device needs to start, time calibration module reads the first time recorded in the cmos circuit and exterior storage medium is written
In；When logic device starting, time calibration module reads the first time stored in exterior storage medium；Time calibration module
The signal duration for the erasing of information signal that the outer logic circuit being electrically connected with logic device is sent to cmos circuit is obtained,
Signal duration is the enabled clear signal that outer logic circuit is sent to cmos circuit and goes between enabled clear signal
Time interval；Time calibration module obtained for the second time, wherein the second time be the cmos circuit receive it is enabled clear
Except the time recorded after signal；The sum of first time, signal duration and second time are written back to by time calibration module
In cmos circuit.The embodiment of the present invention can calibrate automatically the temporal information of cmos circuit after equipment is restarted, and meet electronics and set
Standby time precision requirement, has good reliability.
In several embodiments provided herein, it should be understood that disclosed device and method can also pass through
Other modes are realized.The apparatus embodiments described above are merely exemplary, for example, flow chart and block diagram in attached drawing
Show the device of multiple embodiments according to the present invention, the architectural framework in the cards of method and computer program product,
Function and operation.In this regard, each box in flowchart or block diagram can represent the one of a module, section or code
Part, a part of the module, section or code, which includes that one or more is for implementing the specified logical function, to be held
Row instruction.It should also be noted that function marked in the box can also be to be different from some implementations as replacement
The sequence marked in attached drawing occurs.For example, two continuous boxes can actually be basically executed in parallel, they are sometimes
It can execute in the opposite order, this depends on the function involved.It is also noted that every in block diagram and or flow chart
The combination of box in a box and block diagram and or flow chart can use the dedicated base for executing defined function or movement
It realizes, or can realize using a combination of dedicated hardware and computer instructions in the system of hardware.
In addition, each functional module in each embodiment of the present invention can integrate one independent portion of formation together
Point, it is also possible to modules individualism, an independent part can also be integrated to form with two or more modules.
It, can be with if the function is realized and when sold or used as an independent product in the form of software function module
It is stored in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes：USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.It needs
Illustrate, herein, relational terms such as first and second and the like be used merely to by an entity or operation with
Another entity or operation distinguish, and without necessarily requiring or implying between these entities or operation, there are any this realities
The relationship or sequence on border.Moreover, the terms "include", "comprise" or its any other variant are intended to the packet of nonexcludability
Contain, so that the process, method, article or equipment for including a series of elements not only includes those elements, but also including
Other elements that are not explicitly listed, or further include for elements inherent to such a process, method, article, or device.
In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including the element
Process, method, article or equipment in there is also other identical elements.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.It should be noted that：Similar label and letter exist
Similar terms are indicated in following attached drawing, therefore, once being defined in a certain Xiang Yi attached drawing, are then not required in subsequent attached drawing
It is further defined and explained.
Claims (9)
1. a kind of time calibrating method, which is characterized in that applied to the logic device of electronic equipment, the electronic equipment further includes
Exterior storage medium, the logic device are electrically connected with the exterior storage medium, and the logic device has been internally integrated CMOS
Circuit and time calibration module, the method includes：
When the logic device needs to start, the time calibration module reads the first time recorded in the cmos circuit
And it is written in the exterior storage medium；
When logic device starting, when the time calibration module reads first stored in the exterior storage medium
Between；
The time calibration module obtains the outer logic circuit being electrically connected with the logic device and sends to the cmos circuit
Erasing of information signal signal duration, the signal duration is the outer logic circuit to the cmos circuit
The enabled clear signal that sends and go the time interval between enabled clear signal；
The time calibration module obtained for the second time, wherein second time be the cmos circuit receive it is described
Go the time recorded after enabled clear signal；
The sum of the first time, signal duration and second time are written back to the CMOS electricity by the time calibration module
Lu Zhong.
2. the method as described in claim 1, which is characterized in that described when the logic device needs to start, the time
Calibration module reads the first time recorded in the cmos circuit and the step in the storage medium is written, including：
When the logic device needs to start, the time calibration module reads the first time in the cmos circuit；
The exterior storage medium is written into the first time and time failure mark；
It is described when the logic device starting when, the time calibration module reads first stored in the exterior storage medium
The step of time, including：
When logic device starting, the time calibration module detects in the exterior storage medium whether store having time
Failure mark；
Having time failure mark is stored in the exterior storage medium if detecting, is read in the exterior storage medium and is stored
First time；
If detecting not stored time failure mark in the exterior storage medium, controls the logic device and continue to start.
3. the method as described in claim 1, which is characterized in that the electronic equipment is server；
It is described when the logic device needs to start, the time calibration module reads first recorded in the cmos circuit
Simultaneously the mode in the exterior storage medium is written in time, including：
After the completion of the BIOS upgrading being cured in the logic device external memory, described in the time calibration module reading
First time for recording in cmos circuit is simultaneously written in the exterior storage medium；
It is described when the logic device starting when, the time calibration module reads first stored in the exterior storage medium
The mode of time, including：When BIOS starting, the time calibration module is read to be stored in the exterior storage medium
At the first time.
4. a kind of processor, which is characterized in that be applied to electronic equipment, the electronic equipment further includes exterior storage medium, institute
Processor is stated to be electrically connected with the exterior storage medium, the processor be internally integrated processor core, internal storage and
Cmos circuit, the processor core are electrically connected with the cmos circuit and the internal storage；
The internal storage is for storing machine readable instructions；
The processor core is for reading the machine readable instructions, to execute：
When the processor needs to start, reads the first time recorded in the cmos circuit and the external storage is written
In medium；
When processor starting, the first time stored in the exterior storage medium is read；
Obtain the letter for the erasing of information signal that the outer logic circuit being electrically connected with the processor is sent to the cmos circuit
Number duration, the signal duration are the enabled clear signal that the outer logic circuit is sent to the cmos circuit
And go the time interval between enabled clear signal；
Obtained for the second time, wherein second time be the cmos circuit receive it is described go enabled clear signal after
The time of record；
The sum of the first time, signal duration and second time are written back in the cmos circuit.
5. a kind of time calibration system, which is characterized in that be applied to electronic equipment, the time calibration system include processor and
Exterior storage medium, the processor are electrically connected with the exterior storage medium, and the processor has been internally integrated cmos circuit
And processor core；
The processor core is used for when the processor needs to start, and reads the first time recorded in the cmos circuit simultaneously
It is written in the exterior storage medium；
The exterior storage medium is used to store the first time of the processor core write-in；
After the cmos circuit is used to receive the erasing of information signal that the outer logic circuit being electrically connected with the processor is sent
CMOS information is removed, and in the reclocking after going enabled clear signal for receiving the outer logic circuit transmission；
The processor core is also used to read the first time stored in the exterior storage medium when the processor starts,
Obtain again the cmos circuit receiving it is described go enabled clear signal after the second time for recording, and when by described first
Between, the sum of the signal duration of erasing of information signal and the second time is written back in the cmos circuit.
6. time calibration system as claimed in claim 5, which is characterized in that the processor core is also used to when the processor
When needing to start, the first time in the cmos circuit is read, it will be described in the first time and time failure mark write-in
In exterior storage medium；
The processor core is also used to detect whether the exterior storage medium stores having time mistake when the processor starts
Valid flag stores having time failure mark if detecting, reads in the exterior storage medium in the exterior storage medium
The first time of storage controls the processor if detecting not stored time failure mark in the exterior storage medium
Continue to start.
7. time calibration system as claimed in claim 5, which is characterized in that the electronic equipment is server, the processing
Device core, which is also used to read in the cmos circuit after the completion of the BIOS upgrading being cured in the processor external memory, to be remembered
The first time of record is simultaneously written in the exterior storage medium, and reads the exterior storage medium when BIOS starting
The first time of middle storage.
8. time calibration system as claimed in claim 5, which is characterized in that the time calibration system further includes external electrical
Source, the external power supply are electrically connected with the cmos circuit, and the external power supply is used in processor power-off be described
Cmos circuit power supply, with drive the cmos circuit receive it is described go enabled clear signal after start timing.
9. time calibration system as claimed in claim 8, which is characterized in that the external power supply is battery.
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