CN101799658A - Backup clock calibrated by GPS - Google Patents
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- CN101799658A CN101799658A CN 201010116226 CN201010116226A CN101799658A CN 101799658 A CN101799658 A CN 101799658A CN 201010116226 CN201010116226 CN 201010116226 CN 201010116226 A CN201010116226 A CN 201010116226A CN 101799658 A CN101799658 A CN 101799658A
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Abstract
The invention provides an adder-based backup clock calibrated by a GPS. The adder-based backup clock comprises a GPS receiver, a singlechip, a crystal oscillator, a programmable logic device and a time-digital converter (TDC) which are connected in sequence. The frequency of the crystal oscillator is divided into second pulse output by an adder-based clock circuit realized in the programmable logic device, wherein the frequency dividing ratio of the clock circuit can be finely adjusted. By utilizing the characteristic that 1PPS second pulse signals output by the GPS receiver has a random jitter error but no accumulation error while a second pulse generated after the frequency division of the high-stability crystal oscillator has good temporary stability but the accumulation error, the time-digital converter (TDC) is adopted to measure a phase difference between the two second pulses and filter measurement results of multiple times so as to calculate an accuracy error value of the frequency of the crystal oscillator, the error value is converted into a clock step fine-adjusting value and the frequency dividing ratio of the circuit is adjusted to compensate an accuracy error of the crystal oscillator generated by aging so as to realize high-precision backup. The backup clock has the advantages of full digitalization, simple structure, convenient integration and the like.
Description
Technical field
The invention belongs to GPS time service and punctual field, particularly relate to a kind of punctual clock of GPS calibration.
Background technology
Punctual clock is a kind of by standard frequency source with have the frequency divider of certain frequency dividing ratio, a precision clock that counter constitutes.
Keep time and be meant the clock that has been calibrated under the state of autonomous operation, keep the as far as possible little ability of error between its time and standard time.Punctual precision also is that the time precision of clock autonomous operation is an important techniques index weighing the clock performance quality.This index may be defined as: under certain external condition, and the ratio of the time of clock autonomous operation and the time deviation that produces during this period.
The punctual ability of clock depends primarily on the frequency stability of standard frequency source.Practical standard frequency source has atomic frequency standard and high stability crystal oscillator frequency marking two big classes, and wherein the latter is to use standard frequency source the most widely.
The key technical indexes of statement crystal oscillator performance has: initial precision, degree of stability (mainly being temperature stability) and ageing rate etc.Can be divided into 4 classes according to the precision of crystal oscillator and the different crystal oscillators of degree of stability: i.e. common crystals (SPXO), voltage type crystal oscillator (VCXO), temp. compensation type crystal oscillator (TCXO) and thermostatic type crystal oscillator (OCXO).Also there is above-mentioned 4 types combination, as: voltage-controlled constant-temperature crystal oscillator (VOCXO) etc.TCXO, OCXO and VOCXO are the crystal oscillator types that is commonly used to make up punctual clock.From the degree of stability of frequency, the index of OCXO is better than the VOCXO of TCXO and equal technological level.
Owing to there is irreversible problem of aging, the frequency accuracy of crystal oscillator output can produce irreversible deviation as time goes by.This is the main cause that causes the punctual precise decreasing of clock.The method that solves is to utilize the time reference signal of time service type GPS receiver output or the available accuracy error that other time reference signal calculates crystal oscillator, and carries out suitable rectification building-out.
The most frequently used rectification building-out scheme is to adopt the phaselocked loop scheme, promptly calculate the frequency departure of crystal oscillator earlier, generate compensation rate, again compensation rate is converted to the output frequency that voltage is directly regulated the VOCXO crystal oscillator, make its frequency lock on specified frequency, reach the punctual function of frequency locking.The advantage of this scheme is also to have realized frequency locking when realization is punctual; Its shortcoming is that scheme implements the circuit complexity, needs to adopt high-precision DAC, multiple power supplies and challenging Analog Circuit Design.
Only needing under the situation of punctual (not needing frequency locking), can recently compensate the frequency deviation of crystal oscillator by the frequency division that changes clock circuit.The advantage of this scheme is that circuit is totally digitilized, so that simplicity of design is convenient to is integrated.In addition, can also adopt degree of stability to be higher than the OCXO of VOCXO of the same type as frequency source.
Summary of the invention
The objective of the invention is to propose the punctual clock of full digital high precision that a kind of frequency dividing ratio based on totalizer can fine adjustment.Behind GPS receiver location, the punctual automatic meter of clock is calculated the accuracy error value of crystal oscillator and is generated the corresponding compensation value, utilizes the frequency dividing ratio of this offset fine setting clock circuit, realizes that the high precision after the GPS receiver losing lock is punctual.
A kind of punctual clock of GPS calibration, comprise single-chip microcomputer, programmable logic device (PLD), time-digital quantizer TDC, GPS receiver, antenna and crystal oscillator, the pps pulse per second signal of GPS receiver send to respectively single-chip microcomputer, programmable logic device (PLD) and time-digital quantizer TDC, has the adjustable clock circuit of frequency dividing ratio in the described programmable logic device (PLD), described time-digital quantizer TDC is also sent in the running of the output drive clock circuit of crystal oscillator, the pps pulse per second signal that its frequency division produces;
Behind described GPS receiver location, described single-chip microcomputer is calculated the frequency accuracy error of crystal oscillator according to the phasometer of above-mentioned two pps pulse per second signals that described time-digital quantizer TDC measures, and according to above-mentioned error further calculate the compensation this error clock step pitch trim values, import in the described clock circuit, thereby dynamically update the frequency dividing ratio of described clock circuit;
After described GPS receiver lost the location, punctual clock entered " keeping time " state, when described crystal oscillator drive clock circuit is independently walked, promptly can realize accurately punctual.
Clock circuit of the present invention comprises specified stride value literal register, first adder and the second adder of step pitch fine setting register, the r-p+1 position of stride value register, the r-q+1 position of time value totalizer second, the r-p+1 position of r position, wherein r, p and q are natural number, and r＞q＞p
The above-mentioned clock step pitch trim values that calculates is write in the step pitch fine setting register, the result who by described second adder step pitch is finely tuned after the numerical value addition of the numerical value of register and described specified stride value literal register sends into the stride value register, second in crystal oscillator cycle, the numerical value and the stride value register of time value totalizer sent back in this second time value totalizer after first adder carries out the unsigned number addition, realized the renewal of described clock circuit frequency dividing ratio.
The measurement of phase differential of the present invention is carried out under " measurement " state behind the location, under this " measurement " state, the pps pulse per second signal GPS-1PPS of GPS receiver and the phase differential of two pulses of pps pulse per second signal ABC-1PPS that frequency division produces are once constantly measured and write down to described single-chip microcomputer (1) per second, and obtain many group measurement results.
The frequency accuracy error of crystal oscillator of the present invention carries out calculating after Kalman filtering is handled to described many group measurement results.
The present invention is under described " measurement " state, when satisfying one of following condition:
1. the phase differential of the pps pulse per second signal ABC-1PPS that produces of the pps pulse per second signal GPS-1PPS of GPS receiver (4) and frequency division exceeds described time-measurement range of digital quantizer TDC;
When 2. the number of times of Ce Lianging exceeds the higher limit that sets in advance;
Punctual clock enters " renewal step pitch " state, under this " renewal step pitch " state, calculate the accuracy error of crystal oscillator according to above-mentioned many group measurement results, and further calculate corresponding clock step pitch trim values and write in the step pitch fine setting register, the frequency dividing ratio of refresh clock circuit, return " measurement " state then, the circulation said process loses positioning states until the GPS receiver.
The present invention is after the GPS receiver is located once more, and punctual clock comes back to " measurement " state from " keeping time " state.
Before returning before " measurement " state and enter " keep time " state the present invention entering " measurement " state behind the location before, from " renewal step pitch " state, all earlier described two pps pulse per second signals are finished once " synchronously " and operate.
Location of the present invention is determined according to the location time service message that GPS receiver (4) sends by described single-chip microcomputer (1).
A kind of described punctual clock of above-mentioned each technical scheme of using carries out accurately punctual method, comprises the steps:
(1) determines crystal oscillator type and the further figure place of determining time value totalizer second in the described clock circuit, stride value register, step pitch fine setting register and specified stride value literal register according to punctual accuracy requirement;
(2) upgrade step pitch: behind described GPS receiver location, the single-chip microcomputer per second once constantly writes down the phase difference measurement result of GPS-1PPS and two pulses of ABC-1PPS; When following condition taking place one of at least the time: 1. the phase differential of GPS-1PPS and two pulses of ABC-1PPS exceeds the measurement range of TDC3 or the number of times 2. measured exceeds a higher limit that sets in advance, and the measurement result that single-chip microcomputer adopts Kalman filtering algorithm that the front is repeatedly write down is carried out calculating the accuracy error of crystal oscillator after the filtering and further calculated corresponding clock step pitch offset and write in the step pitch fine setting register;
(3) when described punctual clock loses the location and enters punctual state, change the frequency dividing ratio of described clock circuit based on the above-mentioned clock step pitch offset that writes step pitch fine setting register, realize accurately punctual.
Further, in the above-mentioned steps (1), determine the frequency stability of required crystal oscillator earlier according to punctual accuracy requirement, selected crystal oscillator, determine the figure place r of described second time value totalizer again according to the frequency stability of above-mentioned crystal oscillator, determine the parameter p of the specified stride value constant of r-p+1 position according to the nominal period value of crystal oscillator, determine the parameter q of the step pitch fine setting register of r-q+1 position, thereby determine the figure place of totalizer and each register according to the maximum frequency error scope of compensation crystal oscillator.
Technique effect of the present invention is embodied in:
(1) but the frequency departure that adopts programmable logic device (PLD) to realize that clock circuit based on the frequency dividing ratio fine adjustment of totalizer compensates crystal oscillator realizes that high precision is punctual, whole proposal is a full-digital circuit, has simplicity of design, is convenient to advantages such as power type integrated and that require is few.
(2) frequency source of clock circuit can adopt higher OCXO of degree of stability rather than VCOXO crystal oscillator, is beneficial to the punctual precision that improves clock.
Description of drawings
The punctual bell structure block diagram of the full digital of Fig. 1: GPS calibration;
Fig. 2: programming device inside is based on the clock circuit logic diagram of totalizer;
Fig. 3: the state transition graph of punctual clock;
Fig. 4: time difference method frequency measurement differential intention
Table 1: the temporal resolution of register-bit representative;
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments.
Based on the punctual clock of the full digital of totalizer comprise GPS receiver 4, antenna 5, single-chip microcomputer 1, programmable logic device (PLD) 2, crystal oscillator 6 and time-digital quantizer TDC3; The pps pulse per second signal GPS-1PPS of GPS receiver 4 outputs sends single-chip microcomputer 1, programmable logic device (PLD) 2 and TDC3 respectively to, and the NMEA-0183 location time service message of GPS receiver 4 outputs sends single-chip microcomputer 1 to; Single-chip microcomputer 1 judges whether the GPS receiver locatees on (satellite of locking more than 4 and 4) according to message, and controls clock circuit in view of the above and enter different duties.Single-chip microcomputer 1 links to each other with programmable logic device (PLD) 2 with control signal wire CS, WR, SELE and CLEAR by data bus dbus, address bus ABUS, links to each other with TDC3 by spi bus.
In the described programmable logic device (PLD) 2 based on the clock circuit of totalizer as shown in Figure 2, comprise a r position ([1 of number of bits scope,-r position]) time value totalizer 21 second, ([p position, one (r-p+1) position,-r position]) stride value register 22, ([q position, one (r-q+1) position,-r position]) step pitch fine setting register 23, (r-p+1) position ([p position ,-r position]) specified stride value constant 24, totalizer 25, totalizer 26 or door 27, alternative selector switch 28 and with door 29.Table 1 has provided each binary digit time corresponding resolution.
The output of crystal oscillator 6 drives whole clock circuit running as shown in Figure 2, it is each of [1 of time value totalizer 21 numerical value second in crystal oscillator cycle,-r position] and stride value register 22[-p position ,-r position] carry out sending back to a second time value totalizer 21[-1 position ,-r position after the unsigned number addition] in; When second, time value totalizer 21 overflowed, produce pulse per second (PPS) ABC-1PPS; The numerical value that changes stride value register 22 can change the frequency dividing ratio of clock circuit; And the numerical value of stride value register 22 [p position ,-r position] is by specified stride value constant 24[-p position ,-r position] and step pitch fine setting register 23[-q position ,-r position] carry out under the effect of quenching pulse SYN-CLR synchronously that sign extended and complement code addition produce.The numerical value of step pitch fine setting register 23 is the complement codes of [q position ,-r position] being write by single-chip microcomputer 1, and wherein most significant digit (that is :-q position) be a sign bit, and other is a value bit.Before the addition, the complement code of [q position ,-r position] elder generation sign extended be again with the clock stride value of new [p the position ,-r position] of the specified stride value constant 24 additions generation of [p position ,-r position] and write in the stride value register 22 after [p position ,-r position].When the step pitch trim values that writes was positive number, the clock stride value of generation increased, and a second time value totalizer 21 overflows constantly in advance, and the corresponding pulse per second (PPS) ABC-1PPS cycle reduces, and has been equivalent to reduce the frequency dividing ratio of circuit; When the step pitch trim values that writes was negative, the result was just in time opposite.
The GPS-1PPS signal is sent into the STOP2 input end of TDC3 as shown in Figure 2; The ABC-1PPS signal is sent into the STOP1 input end of TDC3; Or door 27 is delivered to the START input end of TDC3 as the enabling signal of measuring the time difference with producing signal GorA-1PPS after GPS-1PPS and two pulse signal inclusive-OR operations of ABC-1PPS.Single-chip microcomputer 1 control TDC3 per second is finished once the phase difference measurement to GPS-1PPS and two pulse front edges of ABC-1PPS when punctual clock is in " measurement state "; And after adopting Kalman filtering algorithm that the result (Δ t1 shown in Figure 4, Δ t2...) who repeatedly measures is carried out filtering, calculate the accuracy error of crystal oscillator 6; This error being converted to corresponding clock step pitch offset writes in the step pitch fine setting register 23 again; When being in " punctual state ", utilize this offset to realize that high precision is punctual.
When single-chip microcomputer 1 needs the control clock circuit to finish once " synchronous operation " with the pulse per second (PPS) of GPS, send the CLEAR signal as shown in Figure 2, this signal and GPS-1PPS through with door 29 " with " after at the forward position of GPS-1PPS generation SYN-CLR signal.The SYN-CLR signal makes second time value totalizer 21 zero clearings realize synchronously (the forward position alignment of GPS-1PPS shown in Figure 4 and two pulses of ABC-1PPS), and makes totalizer 26 finish an additive operation, upgrades the content of stride value register 22.Single-chip microcomputer 1 sends the SELE signal according to the difference of duty and gives alternative data selector 28, selects the current OPT-1PPS of pulse per second (PPS) the most accurately output from GPS-1PPS and two pulse signals of ABC-1PPS, and this signal is also delivered to the INT2 pin of single-chip microcomputer 1.
Fig. 3 is the duty transition diagram of punctual clock, enters " initialization " state after punctual clock powers on, and waits for that under this state GPS receiver positioning instant locks 4 and 4 above satellites at least; Enter " measurement " state again after finishing once " synchronously " operation (sending the CLEAR signal) behind the location earlier; (send the SELE signal and select GPS-1PPS as OPT-1PPS) under " measurement " state, single-chip microcomputer 1 per second once constantly writes down the phase difference measurement result of GPS-1PPS and two pulses of ABC-1PPS; When generation: 1. the phase differential of GPS-1PPS and two pulses of ABC-1PPS exceeds the measurement range of TDC3 or the number of times 2. measured when exceeding higher limit that sets in advance, and punctual clock enters " renewal step pitch " state; Under this state, the measurement result that single-chip microcomputer 1 adopts Kalman filtering algorithm that the front is repeatedly write down is carried out calculating the accuracy error of crystal oscillator 6 after the filtering and is further calculated corresponding clock step pitch offset and write in the step pitch fine setting register 23, return " measurement " state then, also will carry out once " synchronously " operation before returning; " renewal step pitch " state is a unsteady state, and punctual clock only stops 1 second time at this state; If the satellite number of GPS receiver locking then enters " keeping time " state immediately less than 4, finish once " synchronously " operation before entering earlier, select ABC-1PPS as OPT-1PPS again; After entering " keeping time " state, rely on crystal oscillator 6 to drive when frequency dividing ratio is independently walked through the clock circuit of fine setting compensation and realize that high precision is punctual; After the GPS receiver was located once more, clock came back to " measurement " state.
When punctual clock is in " measurement " state, single-chip microcomputer 1 from the NMEA-0183 location time service message of GPS receiver 4 output, parse second, branch, the time, day, the moon, year equal time information; When punctual clock is in " keeping time " state, the interruption that single-chip microcomputer 1 produces according to the OPT-1PPS pulse per second (PPS) finish automatically second, branch, the time, adding of day, the moon, year 1 count and adjust the leap year leap month.
Suppose that the punctual precision that need to realize is better than 200us/ days (that is: second 200us/86400 second=2.3148ns/, being equivalent to the total frequency accuracy of crystal oscillator must be less than 2.3148ppb), therefore in order to leave the high-stability constant-temperature OCXO crystal oscillator that certain surplus crystal oscillator 6 selected frequency degree of stability are better than 1x10E-9 (being 1ppb).The rated frequency of supposing crystal oscillator 6 again is 20MHz (corresponding nominal period To=50ns).In order to overcome the influence of frequency accuracy error that the crystal oscillator ageing rate produces to punctual precision, must regularly measure calibration, and guarantee that the aging frequency accuracy error that produces of crystal oscillator is not more than total accuracy error between twice alignment epoch and require (that is: 2.3148ppb).
Determine the figure place r of second time value totalizer 21 among Fig. 2: owing to adopt limited bit to represent that the crystal oscillator cycle will inevitably produce truncation error, here getting truncation error is not more than 1ns/ and (should be not more than 2.3148ns/ second second, and leave surplus), the truncation error in each corresponding crystal oscillator cycle is not more than 1ns/20MHz=5x10E-17 second=50as, table look-up and 1 know that-55 corresponding 27.76as meet the demands, so get: the r=55 position.
Determine specified stride value constant 24 and figure place p among Fig. 2: because the nominal period To=50ns of crystal oscillator, table look-up and 1 can determine to be-25 by figure place p (corresponding temporal resolution is: 29.80ns).The binary number scope of specified stride value constant 24 is [25 ,-55] totally 31.The computing formula of specified stride value constant is: nominal period value/lowest order temporal resolution specifically is calculated as follows:
T
o/2
-r＝50×10
-9/2
-55≈1801439851＝110，1011，0101，1111，1100，1010，0110，1011B
The numerical value of determining the figure place q:q of the step pitch fine setting register 23 among Fig. 2 has determined circuit can compensate the maximum likelihood deviation range of crystal oscillator 6.Suppose punctual clock after work for many years, because initial accuracy error, total accuracy error that aging cumulative errors and other factors cause is no more than: ± 10ppm.The cycle maximal regulated scope that can determine the ABC-1PPS pulse per second (PPS) thus is: ± 10us/ second, the maximum adjustable adjusting range in corresponding each crystal oscillator cycle is: ± 10us/20MHz=± 0.5ps/ crystal oscillator cycle.Table look-up and 1 know :-41 time corresponding resolution are that 0.45475ps meets the demands, and the binary number scope that therefore can determine step pitch fine setting register 23 is that [40 ,-55] figure place (increasing by 1 bit sign position) amounts to 16.
The logical design of above-mentioned clock circuit based on totalizer can adopt Verilog or VHDL language design, compiling and programming in programmable logic device (PLD).
The margin of error of shake before and after the forward position of the 1PPS pulse per second (PPS) of GPS receiver output existed one constantly with respect to whole second of UTC time, this margin of error is commonly considered as the stochastic variable of a zero-mean.Adopt as shown in Figure 4 GPS_1PPS that time difference method measures and ABC_1PPS time difference Δ t1, Δ t2 ... in also comprised this error.Adopt repeatedly the average or Kalman filtering algorithm of measurement result can eliminate of the influence of this stochastic error amount to the frequency difference measurement result.Owing to the data of the algorithm of introducing this respect and Kalman filtering algorithm is more, repeat no more here
Described GPS receiver 4 can adopt any a time service type GPS receiver, as: the M12M timing type receiver of motorola inc.
Single-chip microcomputer, DSP or ARM etc. that described single-chip microcomputer 1 can adopt any a computational resource and operating rate to meet the demands.
Described programmable logic device (PLD) 2 can adopt any a logical resource enough big CPLD or FPGA, as: the XC95288XL of Xilinx company.
Described time-digital quantizer TDC3 can adopt the sufficiently high device of any a resolution, as TDC-GP2 (temporal resolution is 50ps).
Constant-temperature crystal oscillator 0CXO or temperature compensating crystal oscillator TCXO that described crystal oscillator 6 can adopt any a frequency stability to meet the demands.
The temporal resolution of table 1 register-bit representative
| Item | Time of equal value | Item | Time of equal value | Item | Time of equal value | Item | Time of equal value |
| ??-01 | ??500ms | ??-17 | ??7.62us | ??-33 | ??116.42ps | ??-49 | ??1.77fs |
| ??-02 | ??250ms | ??-18 | ??3.81us | ??-34 | ??58.21ps | ??-50 | ??888.18as |
| ??-03 | ??125ms | ??-19 | ??1.90us | ??-35 | ??29.10ps | ??-51 | ??444.09as |
| ??-04 | ??62.5ms | ??-20 | ??953.67ns | ??-36 | ??14.56ps | ??-52 | ??222.04as |
| ??-05 | ??31.25ms | ??-21 | ??476.83ns | ??-37 | ??7.28ps | ??-53 | ??111.02as |
| ??-06 | ??15.62ms | ??-22 | ??238.41ns | ??-38 | ??3.64ps | ??-54 | ??55.51as |
| ??-07 | ??7.81ms | ??-23 | ??119.21ns | ??-39 | ??1.82ps | ??-55 | ??27.76as |
| ??-08 | ??3.81ms | ??-24 | ??59.60ns | ??-40 | ??909.50fs | ??-56 | ??13.88as |
| ??-09 | ??1.90ms | ??-25 | ??29.80ns | ??-41 | ??454.75fs | ??-57 | ??6.94as |
| ??-10 | ??976.56us | ??-26 | ??14.90ns | ??-42 | ??227.38fs | ??-58 | ??3.47as |
| ??-11 | ??488.28us | ??-27 | ??7.45ns | ??-43 | ??113.69fs | ??-59 | ??1.73as |
| ??-12 | ??244.14us | ??-28 | ??3.72ns | ??-44 | ??56.84fs | ??-60 | ??867.36zs |
| ??-13 | ??122.07us | ??-29 | ??1.86ns | ??-45 | ??28.42fs | ??-61 | ??433.68zs |
| ??-14 | ??61.03us | ??-30 | ??931.32ps | ??-46 | ??14.21fs | ??-62 | ??216.84zs |
| ??-15 | ??30.51us | ??-31 | ??465.66ps | ??-47 | ??7.11fs | ??-63 | ??108.42zs |
| ??-16 | ??15.25us | ??-32 | ??232.83ps | ??-48 | ??3.55fs | ??-64 | ??54.21zs |
Annotate: s=second, ms=millisecond, us=microsecond, ns=nanosecond, ps=psec, fs=femtosecond, as=Ah second, narrow second of zs=
Claims (10)
1. the punctual clock of GPS calibration, comprise single-chip microcomputer (1), programmable logic device (PLD) (2), time-digital quantizer TDC (3), GPS receiver (4), antenna (5) and crystal oscillator (6), the pps pulse per second signal of GPS receiver (4) send to respectively single-chip microcomputer (1), programmable logic device (PLD) (2) and time-digital quantizer TDC (3), has the adjustable clock circuit of frequency dividing ratio in the described programmable logic device (PLD) (2), described time-digital quantizer TDC (3) is also sent in the running of the output drive clock circuit of crystal oscillator (6), the pps pulse per second signal that its frequency division produces;
Behind described GPS receiver (4) location, described single-chip microcomputer (1) is calculated the frequency accuracy error of crystal oscillator (6) according to the phasometer of above-mentioned two pps pulse per second signals that described time-digital quantizer TDC (3) measures, and according to above-mentioned error further calculate the compensation this error clock step pitch trim values, import in the described clock circuit, thereby dynamically update the frequency dividing ratio of described clock circuit;
After described GPS receiver (4) lost the location, punctual clock entered " keeping time " state, when described crystal oscillator (6) drive clock circuit is independently walked, promptly can realize accurately punctual.
2. the punctual clock of a kind of GPS calibration according to claim 1, it is characterized in that, described clock circuit comprises specified stride value literal register (24), first adder (25) and the second adder (26) of step pitch fine setting register (23), the r-p+1 position of stride value register (22), the r-q+1 position of time value totalizer second (21), the r-p+1 position of r position, wherein r, p and q are natural number, and r＞q＞p
The above-mentioned clock step pitch trim values that calculates is write in the step pitch fine setting register (23), the result who by described second adder (26) step pitch is finely tuned after the numerical value addition of the numerical value of register (23) and described specified stride value literal register (24) sends into stride value register (22), the numerical value of time value totalizer second in crystal oscillator cycle (21) and stride value register (22) send back in this second time value totalizer (21) after first adder (25) carries out the unsigned number addition, realize the renewal of described clock circuit frequency dividing ratio.
3. the punctual clock of a kind of GPS calibration according to claim 1 and 2, it is characterized in that, the measurement of described phase differential is carried out under " measurement " state behind the location, under this " measurement " state, the pps pulse per second signal GPS-1PPS of GPS receiver (4) and the phase differential of two pulses of pps pulse per second signal ABC-1PPS that frequency division produces are once constantly measured and write down to described single-chip microcomputer (1) per second, and obtain many group measurement results.
4. the punctual clock of a kind of GPS calibration according to claim 3 is characterized in that, the frequency accuracy error of described crystal oscillator (6) carries out calculating after Kalman filtering is handled to described many group measurement results.
5. according to the punctual clock of claim 3 or 4 described a kind of GPS calibrations, it is characterized in that, under described " measurement " state, when satisfying one of following condition:
1. the phase differential of the pps pulse per second signal ABC-1PPS that produces of the pps pulse per second signal GPS-1PPS of GPS receiver (4) and frequency division exceeds described time-measurement range of digital quantizer TDC (3);
When 2. the number of times of Ce Lianging exceeds the higher limit that sets in advance;
Punctual clock enters " renewal step pitch " state, under this " renewal step pitch " state, calculate the accuracy error of crystal oscillator (6) according to above-mentioned many group measurement results, and further calculate corresponding clock step pitch trim values and write in the step pitch fine setting register (23), the frequency dividing ratio of refresh clock circuit, return " measurement " state then, the circulation said process loses positioning states until GPS receiver (4).
6. according to the punctual clock of the described a kind of GPS calibration of one of claim 1-5, it is characterized in that after GPS receiver (4) was located once more, punctual clock came back to " measurement " state from " keeping time " state.
7. according to the punctual clock of the described a kind of GPS calibration of one of claim 3-6, it is characterized in that, before returning before " measurement " state and enter " keep time " state before behind the location, entering " measurement " state, from " renewal step pitch " state, all earlier described two pps pulse per second signals are finished once " synchronously " and operate.
8. according to the punctual clock of the described a kind of GPS calibration of one of claim 1-7, it is characterized in that described location is determined according to the location time service message that GPS receiver (4) sends by described single-chip microcomputer (1).
9. use the method that the described punctual clock of above-mentioned each claim carries out accurately keeping time for one kind, comprise the steps:
(1) determines crystal oscillator type and the further figure place of determining time value totalizer second (21) in the described clock circuit, stride value register (22), step pitch fine setting register (23) and specified stride value literal register (24) according to punctual accuracy requirement;
(2) upgrade step pitch: behind described GPS receiver (4) location, single-chip microcomputer (1) per second once constantly writes down the phase difference measurement result of GPS-1PPS and two pulses of ABC-1PPS; When following condition taking place one of at least the time: 1. the phase differential of GPS-1PPS and two pulses of ABC-1PPS exceeds the measurement range of TDC 3 or the number of times 2. measured exceeds a higher limit that sets in advance, and the measurement result that single-chip microcomputer (1) adopts Kalman filtering algorithm that the front is repeatedly write down is carried out calculating the accuracy error of crystal oscillator (6) after the filtering and further calculated corresponding clock step pitch offset and write in the step pitch fine setting register (23);
(3) when described punctual clock loses the location and enters punctual state, change the frequency dividing ratio of described clock circuit based on the above-mentioned clock step pitch offset that writes step pitch fine setting register (23), realize accurately punctual.
10. method according to claim 9, it is characterized in that, in the above-mentioned steps (1), determine the frequency stability of required crystal oscillator (6) earlier according to punctual accuracy requirement, selected crystal oscillator (6), determine the figure place r of described time value totalizer second (21) again according to the frequency stability of above-mentioned crystal oscillator (6), determine the parameter p of the specified stride value constant (24) of r-p+1 position according to the nominal period value of crystal oscillator (6), determine the parameter q of the step pitch fine setting register (23) of r-q+1 position according to the maximum frequency error scope of compensation crystal oscillator (6), thereby determine the figure place of totalizer and each register.
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| CN 201010116226 CN101799658A (en) | 2010-02-24 | 2010-02-24 | Backup clock calibrated by GPS |
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| CN110133998A (en) * | 2019-05-17 | 2019-08-16 | 长沙理工大学 | A kind of method of anti-duration synchronization attack |
| CN110262210A (en) * | 2019-06-28 | 2019-09-20 | 北斗天汇（北京）科技有限公司 | Crystal oscillator based on counter is kept time method |
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| CN111208539A (en) * | 2019-12-18 | 2020-05-29 | 中国航空工业集团公司成都飞机设计研究所 | High-precision GNSS simulator time synchronization method |
| CN111490777A (en) * | 2019-01-29 | 2020-08-04 | 大唐移动通信设备有限公司 | Crystal oscillator frequency detection method and device |
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| CN110677144B (en) * | 2019-10-14 | 2022-12-23 | 上海无线电设备研究所 | Crystal oscillator calibration method and system |
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| CN111208539B (en) * | 2019-12-18 | 2023-06-23 | 中国航空工业集团公司成都飞机设计研究所 | High-precision GNSS simulator time synchronization method |
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| CN111897201B (en) * | 2020-07-08 | 2021-03-30 | 北京海泰方圆科技股份有限公司 | Clock calibration method and electronic equipment |
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| CN111598727A (en) * | 2020-07-23 | 2020-08-28 | 国网江西省电力有限公司电力科学研究院 | Method for improving metering clock synchronization of intelligent substation based on code phase counting method |
| CN112098720A (en) * | 2020-07-27 | 2020-12-18 | 深圳市风云实业有限公司 | Device and method for testing clock precision and drift by utilizing satellite timekeeping |
| CN112098720B (en) * | 2020-07-27 | 2023-04-07 | 深圳市风云实业有限公司 | Device and method for testing clock precision and drift by utilizing satellite timekeeping |
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| US11545933B2 (en) | 2021-06-01 | 2023-01-03 | Institute Of Geology And Geophysics, Chinese Academy Of Sciences | Real-time correction method for oven controlled crystal oscillator and electromagnetic receiver |
| WO2022252614A1 (en) * | 2021-06-01 | 2022-12-08 | 中国科学院地质与地球物理研究所 | Real-time correction method for constant-temperature crystal oscillator, and electromagnetic receiver |
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