CN105162458A - Whole-spacecraft single-particle soft error time-frequency fault ground-based simulation system - Google Patents
Whole-spacecraft single-particle soft error time-frequency fault ground-based simulation system Download PDFInfo
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Abstract
The invention discloses a whole-spacecraft single-particle soft error time-frequency fault ground-based simulation system. The system adopts a DDS (Direct Digital Synthesizer) to connect with an external frequency marker; the DDS is controlled by an MCU (Micro-programmed Control Unit), and the output of the DDS is connected to an FPGA (Field Programmable Gate Array). An output signal of the DDS after subjected to frequency multiplication by a PLL (Phase Locked Loop) serves as a work clock signal of the FPGA; besides outputting, the output end of a first counter also drives a second counter; the output end of the second counter is connected with an input end of a pulse width counter; a reference 1pps counter outputs a 1pps counting signal; the output end of the pulse width counter outputs while the reset end of the pulse width counter is connected with the work clock signal of the FPGA; an output end of an adding and subtracting period control counter is connected with the period control end of the first counter; the MCU inputs an adding and subtracting period control drive signal, a 1pps whole phase signal and a reset request signal to the FPGA through an MCU interface; and the adding and subtracting period control drive signal, the 1pps whole phase signal and the reset request signal are respectively used for period control and restoration of the adding and subtracting period control counter, the first counter and the second counter. The whole-spacecraft single-particle soft error time-frequency fault ground-based simulation system can finish high-precision and comprehensive simulation of a single event upset effect time-frequency fault.
Description
Technical field
The invention belongs to Aerospace Satellite field of navigation technology, be specifically related to a kind of whole star single-particle soft error time-frequency fault ground simulation system.
Background technology
The China New Generation Big Dipper No. two satellites increase the space communication functions such as upper note, inter-satellite link first, and electronic environment complicated in space may cause the communication failure of uncertain single-particle rank.When occurring to prevent fault, each unit of whole star cannot error correction and affect normal work, need design the system-level multi-level fault filling method of single-particle soft error and carry out simulated failure, to test each unit performance of whole star.Wherein, time-frequency equipment fault simulation is an important component part.
Time-frequency fault simulation equipment usually needed the frequency hopping of frequency marking, phase hit, frequency drift, the simulation cut off and time the target cycle, phase place, duty ratio, the simulation cut off.At present, for the checking of time-frequency Autonomous Integrity Monitoring functions of the equipments and performance, the mode usually adopting all purpose instrument to set for this platform realizes, as adopted rubidium clock, low noise frequency synthesizer and signal generator.Its implementation is: rubidium clock provides the 10MHz frequency standard signal of high stable for platform; Low noise frequency synthesizer produces the 10.23MHz frequency standard signal of low phase noise, frequency and phase-adjustable; Signal generator produce with 10MHz, 10.23MHz coherent, the cycle, phase place and adjustable pulse width 1PPS signal.
Adopt the test platform that all purpose instrument is built, most of functional parameter of time-frequency fault simulation can be completed, but such as frequency drift, the 1PPS phase place change caused because of 10.23MHz frequency anomaly, input and still cannot complete with reference to functional parameters such as compatible 10.23MHz, also there is the shortcomings such as cost is high, volume is large, integrated level is low, interface quantity is dumb, complicated operation simultaneously.
Summary of the invention
In view of this, the invention provides a kind of whole star single-particle soft error time-frequency fault ground simulation system, Single event upset effecf time-frequency fault high accuracy can be completed, comprehensively simulate.
In order to achieve the above object, technical scheme of the present invention is: this system comprises a SP3T switch, Direct Digital Synthesizer DDS, micro-control unit chip MCU, fpga chip, the phase-locked crystal oscillator in arrowband and the first drive circuit and the second drive circuit.
External three frequency markings in SP3T switch one end, the other end connects DDS, for selecting a frequency marking as reference clock from three frequency markings for DDS.
The control end that DDS output connects FPGA, DDS connects MCU by spi bus.
MCU is received the default output frequency of outside input by RS232 bus and presets output phase place, is connected the control end of DDS by spi bus, is linked in FPGA by MCU interface; MCU according to preset output frequency, by spi bus to DDS incoming frequency control word and phase control words.
Be integrated with phase-locked loop pll, the first counter, the second counter in FPGA, with reference to 1pps counter, add and subtract periodic Control counter, pulse width counter, MCU interface and one and door.
PLL receives the output signal of DDS, exports FPGA operating clock signals after carrying out frequency multiplication by the output of PLL, and this FPGA operating clock signals is the first counter, provides drive singal with reference to 1pps counter and pulse width counter.
The output of the first counter be connected on the one hand the second counter drive end, exported by the phase-locked crystal oscillator in arrowband and the first drive circuit on the other hand; Wherein the count module of the first counter is determined by frequency multiplication of phase locked loop multiple.
The output of the second counter is connected to pulse width counter input, and the count module of the second counter is determined by self clock; The periodic Control end of the second counter passes through MCU interface 1pps complete cycle phase signal, to realize the periodic Control of MCU to the second counter; The drive end of the second counter receives the output of the first counter as drive singal.
With reference to the outside markers of the input access 1pps of 1pps counter, it is exported the count signal of 1pps under FPGA operating clock signals drives by output.
The output of pulse width counter connects the second drive circuit and exports; The reset terminal access FPGA operating clock signals of pulse width counter.
Plus-minus periodic Control counter is by the plus-minus periodic Control drive singal of MCU interface MCU, and the output of this plus-minus periodic Control counter is connected to the periodic Control end of the first counter.
MCU sends plus-minus periodic Control drive singal, 1pps complete cycle phase signal and reseting request signal by MCU interface, the count signal of reseting request signal and 1pps is by carrying out exporting phase place reset pulse afterwards with operation with door, and this phase place reset pulse is linked into the phase place reset terminal of the first counter and the second counter respectively.
Further, the frequency multiplication multiple of PLL is 10, then the first counter is mould 10 counter.
Further, frequency marking comprises a rubidium atomic clock and two outside frequency markings.
Two outside frequency markings are except being linked into SP3T switch, also be connected in MCU and detect, whether MCU detects two outside frequency markings online, if two outside frequency markings are all online, any one reference clock as DDS in three kinds of frequency markings selected by SP3T switch.
Further, this system has following fault simulation pattern:
1), 10.23MHz fault simulation, comprise that 10.23M signal is cut off suddenly, 10.23M frequency hopping, export phase hit and frequency drift.
Rubidium atomic clock is 10MHz, and outside frequency marking is 10MHz and 10.23MHz.
10.23M signal is cut off suddenly, realizes by controlling to switch the power supply cutting off the phase-locked crystal oscillator in arrowband.
10.23M frequency hopping, is realized by DDS frequency modulation, and DDS has 48 bit frequency control words, and when clock is 10.23MHz, frequency Adjustment precision is 0.6uHz; The tuning range of the VCOCXO that the phase-locked crystal oscillator in arrowband adopts is ± 0.3ppm, and namely frequency hopping scope is ± 3Hz, then the frequency hopping exporting 10.23MHz is: ± 3Hz tuning range, the saltus step of the stepping of 0.6uHz.
Export phase hit, realized by DDS phase control, the phase place Adjustment precision of DDS is 6ps.
Frequency drift realizes in the following way: MCU Interruption 1s, and when interrupting occurring, MCU is by spi bus to DDS incoming frequency control word, and now the scope of frequency drift is frequency hopping scope ± 3Hz, and drift velocity resolution is 0.6uHz/s.
2), 1pps fault simulation, comprise 1pps cycle and pulsewidth width adjustment and the adjustment of 1pps phase place.
1pps cycle and pulsewidth width adjustment, in the adjustment cycle of a setting, second counter is under the driving of FPGA operating clock signals 10.23MHz, and from accumulation loop counting between 0 ~ divide ratio, each circulation generation pulse signal is sent to pulse width counter; After pulse width counter receives the pulse of frequency counter, accumulated counts from 0, stopping counting when reaching pulse width values, exporting high level in counting process, realizes period modulation and the pulse duration adjustment of 1PPS.
Second counter works clock is 10.23MHz, then realize the period modulation of 97.8ns resolution; Pulse width counter work clock is 102.3MHz, then realize the pulse duration adjustment of 9.8ns resolution.
1pps phase place adjusts, and the first counter counting under 102.3M drives produces digital 10.23M clock, and the first counter has three kinds of mode of operations: mould 10 pattern, mould 9 pattern, mould 11 pattern.
When without the need to adjusting phase place, counter works is in mould 10 pattern, and counter cycle is each lasting 5 the 102.3M clocks of the low and high level of 10,10.23M.
When needing the amount into horizontal phasing control for ± Pns, wherein+represent advanced ,-representing delayed, host computer calculates the work week issue N=floor (P*102.3M) of mould 9 or mould 11.
If advanced, then select mould 9 pattern, the count cycle is 9, and relative to mould 10 pattern, low level reduces by a clock cycle, and the duration is 4 clocks, and high level is still 5 clocks, now the advanced 9.775ns of rising edge.
If delayed, then select mould 11 pattern, the count cycle is 11, and relative to mould 10 pattern, low level increases by 1 one clock cycle, the delayed 9.775ns of rising edge.
Beneficial effect:
The whole star single-particle soft error time-frequency fault ground simulation system that the present invention proposes, contrast prior art, when carrying out Single event upset effecf time-frequency fault simulation, can reach higher precision, such as frequency hopping is realized by DDS frequency modulation in the present embodiment.Frequency Adjustment precision
the DDS selected has 48 bit frequency control words, and clock is 10.23MHz (10MHz) × 16, then frequency Adjustment precision
the tuning range of the VCOCXO adopted due to phase-locked crystal oscillator is generally ± 0.3ppm, and namely frequency hopping scope is ± 3Hz.Like this, the frequency exporting 10.23MHz can realize ± 3Hz tuning range, the stepping of 0.6uHz; Native system comprehensively can be simulated for the duty ratio of the frequency shift (FS) to frequency signal, frequency drift, phase place change, time signal, cycle, phase place change adjustment etc. simultaneously, and it has the effect simplifying test environment, improve test coverage, improve testing efficiency, reduce testing cost.
Accompanying drawing explanation
Fig. 1 is the theory diagram of embodiment of the present invention;
10.23MHz phase place adjustment schematic diagram when Fig. 2 is 1PPS phase modulation.
Embodiment
To develop simultaneously embodiment below in conjunction with accompanying drawing, describe the present invention.
Embodiment 1, one whole star single-particle soft error time-frequency fault ground simulation system as shown in Figure 1, this system comprises a SP3T switch, Direct Digital Synthesizer DDS, micro-control unit chip MCU, fpga chip, the phase-locked crystal oscillator in arrowband and drive circuit.
External three frequency markings in SP3T switch one end, the other end connects DDS, for selecting a frequency marking as reference clock from three frequency markings for DDS.
The control end that DDS output connects FPGA, DDS connects MCU by spi bus.
MCU is received the default output frequency of outside input by RS232 bus and presets output phase place, is connected the control end of DDS by spi bus, is linked in FPGA by MCU interface; MCU according to preset output frequency, by spi bus to DDS incoming frequency control word and phase control words.
Be integrated with phase-locked loop pll, the first counter, the second counter in FPGA, with reference to 1pps counter, add and subtract periodic Control counter, pulse width counter and MCU interface.
PLL receives the output signal of DDS, exports FPGA operating clock signals after carrying out frequency multiplication by the output of PLL, and this FPGA operating clock signals is the first counter, provides drive singal with reference to 1pps counter and pulse width counter.
The output of the first counter be connected on the one hand the second counter drive end, exported by the phase-locked crystal oscillator in arrowband and drive circuit on the other hand; Wherein the count module of the first counter is determined by frequency multiplication of phase locked loop multiple.
The output of the second counter is connected to pulse width counter input, and the count module of the second counter is determined by self clock; The periodic Control end of the second counter passes through MCU interface 1pps complete cycle phase signal, to realize the periodic Control of MCU to the second counter.
With reference to the outside markers of the input access 1pps of 1pps counter, it is exported the count signal of 1pps under FPGA operating clock signals drives by output.
The output of pulse width counter connects drive circuit and exports; The reset terminal access FPGA operating clock signals of pulse width counter.
Plus-minus periodic Control counter is by the plus-minus periodic Control drive singal of MCU interface MCU, and the output of this plus-minus periodic Control counter is connected to the periodic Control end of the first counter.
MCU sends plus-minus periodic Control drive singal, 1pps complete cycle phase signal and reseting request signal by MCU interface, the count signal of reseting request signal and 1pps carries out obtaining phase place reset pulse afterwards with operation, and this phase place reset pulse is linked into the phase place reset terminal of the first counter and the second counter respectively.
In the present embodiment, the frequency multiplication multiple of PLL is 10, then the first counter is mould 10 counter.
In the present embodiment, frequency marking comprises a rubidium atomic clock and two outside frequency markings; Two outside frequency markings are except being linked into SP3T switch, also be connected in MCU and detect, whether MCU detects two outside frequency markings online, if two outside frequency markings are all online, any one reference clock as DDS in three kinds of frequency markings selected by SP3T switch.
In embodiment 2, the present embodiment, two outside frequency markings are respectively 10MHz and 10.23MHz, and the first counter is mould 10 counter, and the second counter is mould 10230000 counter, and the specific works process of native system is as follows:
The core devices of frequency marking part is 10MHz rubidium atomic clock.This rubidium atomic clock, as the input of DDS, can provide the long-term stability of superelevation and lower phase noise.
At the input of two kinds of outer frequency markings, all have coupler that signal is sent to detecting circuit, when detecting circuit is greater than the threshold value of setting, system judges that outside frequency marking is online.User can select a road arbitrarily as required between the online frequency marking of interior atoms clock and outside, by SP3T switch using by select signal give DDS as with reference to clock.
1,10.23MHz fault simulation
Generation and the fault simulation of 10.23M complete by DDS, and the purification of frequency spectrum is realized by the phase-locked crystal oscillator in the arrowband of rear class.The reference clock frequency multiplier that DDS is inner integrated 4 ~ 20 times, has programmable 48 bit frequency control registers, the phase deviation register of 14 and 20 slop control registers.
1. 10.23M signal is cut off suddenly
By controlling to switch the power supply cutting off the phase-locked crystal oscillator of 10.23MHz, realize interrupting suddenly.
2. 10.23M frequency hopping
Frequency hopping is realized by DDS frequency modulation.Frequency Adjustment precision
the DDS selected has 48 bit frequency control words, and clock is 10.23MHz (10MHz) × 16, then frequency Adjustment precision
the tuning range of the VCOCXO adopted due to phase-locked crystal oscillator is generally ± 0.3ppm, and namely frequency hopping scope is ± 3Hz.Like this, the frequency exporting 10.23MHz can realize ± 3Hz tuning range, the stepping of 0.6uHz.
For when producing 10.23MHz with 10MHz reference, there is the frequency difference situation of drawing frequency control word non-integer situation and causing, realize 10.23MHz and 10MHz frequency accuracy by backoff algorithm identical.
3. phase hit is exported
Phase hit is realized by DDS phase control.Frequency Adjustment precision
the DDS selected has 14 phase control words, then its phase place Adjustment precision can reach
4. frequency drift
When analog frequency drifts about, the long-term time dependent effect of main analog clock frequency.The slop control word of DDS only has 20, and it is to the maximum at the residence time of each frequency like this
do not reach the needs of 1s far away.Utilize single-chip microcomputer Interruption 1s, the frequency control word refreshing DDS in real time can realize the function of frequency drift.The scope of such frequency drift is frequency hopping scope ± 3Hz, and drift velocity resolution is 0.6uHz/s.
2,1pps fault simulation
The fault simulation of 1pps signal all realizes in FPGA.The 10.23MHz signal that DDS produces is sent into the inner frequency multiplication of phase locked loop of FPGA, FPGA and is exported 102.3MHz clock as FPGA work clock.There are 3 counters FPGA inside: mould 10 counter, mould 10230000 counter and pulse width counter.10.23MHz frequency counter and pulse width counter.102.3MHz clock drives " mould 10 counter " to produce 10.23MHz and exports, then drives " mould 10230000 counter " to produce 1PPS signal with the 10.23MHz clock produced.
1. 1pps cycle and pulsewidth width adjustment
When adjustment cycle, the divide ratio of " mould 10230000 counter " changes according to setting cycle, 10.23MHz clock-driven counter is from accumulation loop counting between 0 ~ " divide ratio ", and each circulation generation pulse signal gives pulse width counter; After pulse width counter receives the pulse of frequency counter, accumulated counts from 0, stopping counting when reaching " pulse duration " value, exporting high level in counting process, realizes period modulation and the pulse duration adjustment of 1PPS.
" mould 10230000 counter " work clock is 10.23MHz, then can realize the period modulation of 97.8ns resolution; Pulse width counter work clock is 102.3MHz, then can realize the pulse duration adjustment of 9.8ns resolution.
2. 1pps phase place adjustment
In this application, require the 1PPS phase place change because 10.23MHz frequency anomaly causes, in exception procedure and after recovery normally, 10.23MHz and 1PPS phase relation is fixed all the time." mould 10 counter " counting under 102.3M drives produces digital 10.23M clock, and counter modulus value is controlled by RS232, has three kinds of mode of operations: mould 10, mould 9, mould 11, as shown in Figure 2.Under normal circumstances, when namely not needing adjustment phase place, counter works is in mould 10 pattern, and counter cycle is each lasting 5 the 102.3M clocks of the low and high level of 10,10.23M.
Under mould 9 mode of operation, the count cycle is 9, and low level reduces by a clock cycle, and the duration is 4 clocks, and high level is still 5 clocks, advanced 1/102.3M=9.775ns before now rising.
Under mould 11 mode of operation, low level increases by 1 one clock cycle, the delayed 9.775ns of rising edge.
When needing the amount into horizontal phasing control for ± Pns, "+" represents advanced, and "-" represents delayed, and host computer calculates the work week issue N of mould 9 or mould 11:
N＝floor(P*102.3M)
FPGA state machine, according to designated mode mode of operation control counter counting N number of work period, then gets back to mould 10 mode of operation, thus completes the phase place adjustment of advanced or delayed N*9.775ns.
Two counters also should comprise a reset terminal, and when host computer initiates phase place reset request, or when the outside 1PPS rising edge of gating arrives, reset counter resets 10.23M and 1PPS phase place.
(5) 1pps fault simulation
The 10.23MHz signal that the phase-locked crystal oscillator in arrowband exports, exports the frequency standard signal of sine, LVDS, RS422 level by interface driving circuit; The 1PPS signal that FPGA exports exports the timing signal of TTL, LVTTl, LVDS, RS422 level through interface driving circuit.
To sum up, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. a whole star single-particle soft error time-frequency fault ground simulation system, it is characterized in that, this system comprises a SP3T switch, Direct Digital Synthesizer DDS, micro-control unit chip MCU, fpga chip, the phase-locked crystal oscillator in arrowband and the first drive circuit and the second drive circuit:
External three frequency markings in described SP3T switch one end, the other end connects described DDS, for selecting a frequency marking as reference clock from three frequency markings for DDS;
The control end that described DDS output connects FPGA, DDS connects described MCU by spi bus;
Described MCU is received the default output frequency of outside input by RS232 bus and presets output phase place, is connected the control end of DDS by spi bus, is linked in described FPGA by MCU interface; MCU according to described default output frequency, by spi bus to DDS incoming frequency control word and phase control words;
Be integrated with phase-locked loop pll, the first counter, the second counter in described FPGA, with reference to 1pps counter, add and subtract periodic Control counter, pulse width counter, MCU interface and one and door;
Described PLL receives the output signal of DDS, exports FPGA operating clock signals after carrying out frequency multiplication by the output of PLL, and this FPGA operating clock signals is the first counter, provides drive singal with reference to 1pps counter and pulse width counter;
The output of described first counter be connected on the one hand described second counter drive end, exported by the phase-locked crystal oscillator in arrowband and the first drive circuit on the other hand; Wherein the count module of the first counter is determined by frequency multiplication of phase locked loop multiple;
The output of described second counter is connected to described pulse width counter input, and the count module of the second counter is determined by self clock; The periodic Control end of the second counter passes through described MCU interface 1pps complete cycle phase signal, to realize the periodic Control of MCU to the second counter; The drive end of the second counter receives the output of the first counter as drive singal;
The outside markers of the described access of the input with reference to 1pps counter 1pps, it is exported the count signal of 1pps under FPGA operating clock signals drives by output;
The output of described pulse width counter connects the second drive circuit and exports; The reset terminal of pulse width counter accesses described FPGA operating clock signals;
Described plus-minus periodic Control counter is by the plus-minus periodic Control drive singal of described MCU interface MCU, and the output of this plus-minus periodic Control counter is connected to the periodic Control end of described first counter;
Described MCU sends plus-minus periodic Control drive singal, 1pps complete cycle phase signal and reseting request signal by MCU interface, the count signal of described reseting request signal and described 1pps carries out exporting phase place reset pulse afterwards with operation with door by described, and this phase place reset pulse is linked into the phase place reset terminal of the first counter and the second counter respectively.
2. a kind of whole star single-particle soft error time-frequency fault ground simulation system as claimed in claim 1, it is characterized in that, the frequency multiplication multiple of described PLL is 10, then the first counter is mould 10 counter.
3. a kind of whole star single-particle soft error time-frequency fault ground simulation system as claimed in claim 1, it is characterized in that, described frequency marking comprises a rubidium atomic clock and two outside frequency markings;
Described two outside frequency markings are except being linked into SP3T switch, also be connected in described MCU and detect, whether described MCU detects two outside frequency markings online, if two outside frequency markings are all online, any one reference clock as DDS in three kinds of frequency markings selected by described SP3T switch.
4. a kind of whole star single-particle soft error time-frequency fault ground simulation system as claimed in claim 3, it is characterized in that, this system has following fault simulation pattern:
1), 10.23MHz fault simulation, comprise that 10.23M signal is cut off suddenly, 10.23M frequency hopping, export phase hit and frequency drift;
Described rubidium atomic clock is 10MHz, and described outside frequency marking is 10MHz and 10.23MHz
Described 10.23M signal is cut off suddenly, realizes by controlling to switch the power supply cutting off the phase-locked crystal oscillator in arrowband;
Described 10.23M frequency hopping, is realized by DDS frequency modulation, and described DDS has 48 bit frequency control words, and when clock is 10.23MHz, frequency Adjustment precision is 0.6uHz; The tuning range of the VCOCXO that the phase-locked crystal oscillator in described arrowband adopts is ± 0.3ppm, and namely frequency hopping scope is ± 3Hz, then the frequency hopping exporting 10.23MHz is: ± 3Hz tuning range, the saltus step of the stepping of 0.6uHz;
Described output phase hit, is realized by DDS phase control, and the phase place Adjustment precision of described DDS is 6ps;
Described frequency drift realizes in the following way: described MCU Interruption 1s, when interrupting occurring, MCU is by spi bus to DDS incoming frequency control word, and now the scope of frequency drift is frequency hopping scope ± 3Hz, and drift velocity resolution is 0.6uHz/s.
2), 1pps fault simulation, comprise 1pps cycle and pulsewidth width adjustment and the adjustment of 1pps phase place
Described 1pps cycle and pulsewidth width adjustment, in the adjustment cycle of a setting, described second counter is under the driving of FPGA operating clock signals 10.23MHz, and from accumulation loop counting between 0 ~ divide ratio, each circulation generation pulse signal is sent to pulse width counter; After pulse width counter receives the pulse of frequency counter, accumulated counts from 0, stopping counting when reaching pulse width values, exporting high level in counting process, realizes period modulation and the pulse duration adjustment of 1PPS;
Second counter works clock is 10.23MHz, then realize the period modulation of 97.8ns resolution; Pulse width counter work clock is 102.3MHz, then realize the pulse duration adjustment of 9.8ns resolution.
Described 1pps phase place adjustment, the first counter counting under 102.3M drives produces digital 10.23M clock, and the first counter has three kinds of mode of operations: mould 10 pattern, mould 9 pattern, mould 11 pattern;
When without the need to adjusting phase place, counter works is in mould 10 pattern, and counter cycle is each lasting 5 the 102.3M clocks of the low and high level of 10,10.23M;
When needing the amount into horizontal phasing control for ± Pns, wherein+represent advanced ,-representing delayed, host computer calculates the work week issue N=floor (P*102.3M) of mould 9 or mould 11;
If advanced, then select mould 9 pattern, the count cycle is 9, and relative to mould 10 pattern, low level reduces by a clock cycle, and the duration is 4 clocks, and high level is still 5 clocks, now the advanced 9.775ns of rising edge;
If delayed, then select mould 11 pattern, the count cycle is 11, and relative to mould 10 pattern, low level increases by 1 one clock cycle, the delayed 9.775ns of rising edge.
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| CN109738732A (en) * | 2019-02-14 | 2019-05-10 | 北京润科通用技术有限公司 | A kind of signal edge fault filling method and device |
| CN109738732B (en) * | 2019-02-14 | 2021-04-20 | 北京润科通用技术有限公司 | Signal edge fault injection method and device |
| CN112383300A (en) * | 2020-10-26 | 2021-02-19 | 深圳市儒科电子有限公司 | High-precision frequency phase micro-jump meter |
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