CN105162458B - A kind of whole star single-particle soft error time-frequency failure ground simulation system - Google Patents
A kind of whole star single-particle soft error time-frequency failure ground simulation system Download PDFInfo
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Abstract
The invention discloses a kind of whole star single-particle soft error time-frequency failure ground simulation system, the system is using the outside frequency marking of DDS connections；DDS is controlled by MCU, and is exported into FPGA, using PLL to DDS output signals frequency multiplication as FPGA operating clock signals；The output end of first counter except output in addition to, also drive the second counter；The output end connection pulse width counter input of second counter；With reference to 1pps counters output 1pps count signal；The output end of pulse width counter is exported, its reset terminal access FPGA operating clock signals；The output end of plus-minus periodic Control counter is connected to the periodic Control end of the first counter；MCU inputs plus-minus periodic Control drive signal, 1pps complete cycles phase signal and reseting request signal by MCU interfaces into FPGA, is respectively used to carry out periodic Control and reset to plus-minus periodic Control counter, the first counter and the second counter.The present invention can complete Single event upset effecf time-frequency failure high accuracy, comprehensive simulation.
Description
Technical field
The invention belongs to Aerospace Satellite field of navigation technology, and in particular to a kind of whole star single-particle soft error time-frequency failure
Face simulation system.
Background technology
No. two satellites of the China New Generation Big Dipper increase the space communication functions such as upper note, inter-satellite link first, complicated in space
Electronic environment may cause the communication failure of uncertain single-particle rank.Whole each unit of star during in order to prevent that failure from occurring
Can not error correction and influence normal work, need to design the system-level multi-level fault filling method of single-particle soft error carrys out simulated failure,
To test each unit performance of whole star.Wherein, time-frequency equipment fault simulation is an important component.
Time-frequency fault simulation equipment usually requires to complete frequency hopping, phase hit, frequency drift, the mould cut off of frequency marking
Intend and when the target cycle, phase, dutycycle, the simulation cut off.At present, for time-frequency Autonomous Integrity Monitoring functions of the equipments and
The checking of performance, the mode that generally use all purpose instrument is set for this platform are realized, such as use rubidium clock, low noise frequency synthesizer and letter
Number generator.Its implementation is：Rubidium clock provides the 10MHz frequency standard signals of high stable for platform；Low noise frequency synthesizer produces
The 10.23MHz frequency standard signals of raw low phase noise, frequency and phase-adjustable；Signal generator produces and 10MHz, 10.23MHz
Coherent, the cycle, the 1PPS signals of phase and adjustable pulse width.
The test platform built using all purpose instrument, most of functional parameter of time-frequency fault simulation can be completed, but such as
Frequency drift, the 1PPS phase place changes caused by 10.23MHz frequency anomalies, input are with reference to functional parameters such as compatible 10.23MHz
Or it can not complete, while the shortcomings of cost is high, volume is big, integrated level is low, interface quantity is dumb, complex operation also be present.
The content of the invention
In view of this, can be complete the invention provides a kind of whole star single-particle soft error time-frequency failure ground simulation system
Into Single event upset effecf time-frequency failure high accuracy, comprehensive simulation.
In order to achieve the above object, the technical scheme is that：The system includes a SP3T switch, directly number
Word formula frequency synthesizer DDS, micro-control unit chip MCU, fpga chip, arrowband lock phase crystal oscillator and the first drive circuit and the
Two drive circuits.
External three frequency markings in SP3T switch one end, other end connection DDS, for being selected for DDS from three frequency markings
One frequency marking is as reference clock.
DDS output ends connect FPGA, and DDS control terminal connects MCU by spi bus.
MCU receives the default output frequency of outside input by RS232 buses and default output phase, passes through spi bus
Connect DDS control terminal, be linked into by MCU interfaces in FPGA；MCU is according to default output frequency, by spi bus to DDS
Incoming frequency control word and phase control words.
Be integrated with FPGA phase-locked loop pll, the first counter, the second counter, with reference to 1pps counters, plus-minus the cycle control
Counter processed, pulse width counter, MCU interfaces and one and door.
PLL receive DDS output signal, carry out frequency multiplication after by PLL output end export FPGA operating clock signals, should
FPGA operating clock signals provide drive signal for the first counter, with reference to 1pps counters and pulse width counter.
On the one hand the output end of first counter is connected to the drive end of the second counter, on the other hand locks phase by arrowband
Crystal oscillator and the first drive circuit are exported；Wherein the count module of the first counter is determined by frequency multiplication of phase locked loop multiple.
The output end of second counter is connected to pulse width counter input, and the count module of the second counter is by itself
Clock determines；The periodic Control end of second counter is by MCU interface 1pps complete cycle phase signals, to realize MCU to
The periodic Control of two counters；The drive end of second counter receives the output of the first counter as drive signal.
With reference to 1pps counters input access 1pps outside markers, its FPGA operating clock signals drive under,
By output end output 1pps count signal.
The output end of pulse width counter connects the second drive circuit and exported；The reset terminal of pulse width counter
Access FPGA operating clock signals.
Add and subtract plus-minus periodic Control drive signal of the periodic Control counter by MCU interfaces MCU, the plus-minus cycle
The output end of control counter is connected to the periodic Control end of the first counter.
MCU sends plus-minus periodic Control drive signal, 1pps complete cycles phase signal and reset request by MCU interfaces to be believed
Number, reseting request signal and 1pps count signal are by with door answer with output phase reset pulse, the phase after operation
Digit pulse is respectively connected to the phase reset terminal to the first counter and the second counter.
Further, PLL frequency multiplication multiple is 10, then the first counter is the counter of mould 10.
Further, frequency marking includes a rubidium atomic clock and two outside frequency markings.
Two outside frequency markings are additionally coupled to be detected in MCU in addition to SP3T switch are linked into, MCU detections two
Whether individual outside frequency marking is online, if two outside frequency markings are online, SP3T switch select any of three kinds of frequency markings to make
For DDS reference clock.
Further, the system has following fault simulation pattern：
1), 10.23MHz fault simulations, including 10.23M signals are cut off suddenly, 10.23M frequency hoppings, output phase are jumped
Change and frequency drift.
Rubidium atomic clock is 10MHz, and outside frequency marking is 10MHz and 10.23MHz.
10.23M signals are cut off suddenly, by controlling the power supply realization for switching cut-out arrowband and locking phase crystal oscillator.
10.23M frequency hoppings, realized by DDS frequency modulation, DDS has 48 bit frequency control words, clock 10.23MHz
When, frequency Adjustment precision is 0.6uHz；VCOCXO tuning range is ± 0.3ppm, i.e. frequency used by arrowband lock phase crystal oscillator
Saltus step scope is ± 3Hz, then the frequency hopping for exporting 10.23MHz is：± 3Hz tuning ranges, the saltus step of 0.6uHz stepping.
Output phase saltus step, realized by DDS phase controllings, DDS phase adjustment precision is 6ps.
Frequency drift is realized in the following way：MCU Interruption 1s, interrupt when occurring, MCU is by spi bus to DDS
Incoming frequency control word, now the scope of frequency drift is frequency hopping scope ± 3Hz, and drift velocity resolution ratio is
0.6uHz/s。
2), 1pps fault simulations, including 1pps cycles and pulsewidth width adjustment and 1pps phase adjustments.
1pps cycles and pulsewidth width adjustment, within the adjustment cycle of a setting, the second counter is when FPGA works
Under clock signal 10.23MHz driving, counted from accumulation loop between 0~divide ratio, circulation every time produces a pulse signal
Send to pulse width counter；After pulse width counter receives the pulse of frequency counter, the accumulated counts since 0, when
Stop counting when reaching pulse width values, high level is exported in counting process, the period modulation and pulse width for realizing 1PPS are adjusted
It is whole.
Second counter works clock is 10.23MHz, then realizes the period modulation of 97.8ns resolution ratio；Pulse width meter
Number device work clock is 102.3MHz, then realizes the pulse width adjustment of 9.8ns resolution ratio.
1pps phase adjustments, the first counter counts under 102.3M drivings produces digital 10.23M clocks, and first counts
Device has three kinds of mode of operations：The pattern of mould 10, the pattern of mould 9, the pattern of mould 11.
When without adjustment phase place, counter works are in the pattern of mould 10, counter cycle 10,10.23M low and high level
It is each to continue 5 102.3M clocks.
When it is ± P ns to need the amount into horizontal phasing control, wherein+represent advanced ,-hysteresis is represented, host computer calculates mould
9 or work week issue N=floor (P*102.3M) of mould 11.
If advanced, then the pattern of mould 9 is selected, it is 9 to count the cycle, and relative to the pattern of mould 10, low level reduces by a clock
Cycle, duration are 4 clocks, and high level is still 5 clocks, now the advanced 9.775ns of rising edge.
If hysteresis, then the pattern of mould 11 is selected, it is 11 to count the cycle, relative to the pattern of mould 10, when low level increases by 1 one
Clock cycle, rising edge hysteresis 9.775ns.
Beneficial effect：
Whole star single-particle soft error time-frequency failure ground simulation system proposed by the present invention, prior art is contrasted, is being carried out
During Single event upset effecf time-frequency fault simulation, higher precision can be reached, such as frequency hopping passes through in the present embodiment
DDS frequency modulation is realized.Frequency Adjustment precisionThe DDS of selection has 48 bit frequency control words, clock 10.23MHz
(10MHz) × 16, then frequency Adjustment precisionVCOCXO used by due to lock phase crystal oscillator
Tuning range is generally ± 0.3ppm, i.e. frequency hopping scope is ± 3Hz.So, export 10.23MHz frequency can realize ±
3Hz tuning ranges, 0.6uHz stepping；The system can be for the frequency shift (FS) to frequency signal, frequency drift, phase simultaneously
Change, the dutycycle of time signal, cycle, phase place change adjustment etc. are comprehensively simulated, and it, which has, simplifies test environment, complete
Kind test coverage, the effect for improving testing efficiency, reducing testing cost.
Brief description of the drawings
Fig. 1 is the theory diagram of embodiment of the present invention；
10.23MHz phase adjustment schematic diagrams when Fig. 2 is 1PPS phase modulation.
Embodiment
The present invention will now be described in detail with reference to the accompanying drawings and examples.
Embodiment 1, a kind of whole star single-particle soft error time-frequency failure ground simulation system as shown in Figure 1, the system bag
Include a SP3T switch, Direct Digital Synthesizer DDS, micro-control unit chip MCU, fpga chip, arrowband lock
Phase crystal oscillator and drive circuit.
External three frequency markings in SP3T switch one end, other end connection DDS, for being selected for DDS from three frequency markings
One frequency marking is as reference clock.
DDS output ends connect FPGA, and DDS control terminal connects MCU by spi bus.
MCU receives the default output frequency of outside input by RS232 buses and default output phase, passes through spi bus
Connect DDS control terminal, be linked into by MCU interfaces in FPGA；MCU is according to default output frequency, by spi bus to DDS
Incoming frequency control word and phase control words.
Be integrated with FPGA phase-locked loop pll, the first counter, the second counter, with reference to 1pps counters, plus-minus the cycle control
Counter, pulse width counter and MCU interfaces processed.
PLL receive DDS output signal, carry out frequency multiplication after by PLL output end export FPGA operating clock signals, should
FPGA operating clock signals provide drive signal for the first counter, with reference to 1pps counters and pulse width counter.
On the one hand the output end of first counter is connected to the drive end of the second counter, on the other hand locks phase by arrowband
Crystal oscillator and drive circuit are exported；Wherein the count module of the first counter is determined by frequency multiplication of phase locked loop multiple.
The output end of second counter is connected to pulse width counter input, and the count module of the second counter is by itself
Clock determines；The periodic Control end of second counter is by MCU interface 1pps complete cycle phase signals, to realize MCU to
The periodic Control of two counters.
With reference to 1pps counters input access 1pps outside markers, its FPGA operating clock signals drive under,
By output end output 1pps count signal.
The output end connection drive circuit of pulse width counter is exported；The reset terminal access of pulse width counter
FPGA operating clock signals.
Add and subtract plus-minus periodic Control drive signal of the periodic Control counter by MCU interfaces MCU, the plus-minus cycle
The output end of control counter is connected to the periodic Control end of the first counter.
MCU sends plus-minus periodic Control drive signal, 1pps complete cycles phase signal and reset request by MCU interfaces to be believed
Number, reseting request signal and 1pps count signal are carried out with obtaining phase reset pulse after operation, the phase reset pulse point
The phase reset terminal of the first counter and the second counter is not linked into.
In the present embodiment, PLL frequency multiplication multiple is 10, then the first counter is the counter of mould 10.
In the present embodiment, frequency marking includes a rubidium atomic clock and two outside frequency markings；Two outside frequency markings are removed and are linked into list
Outside the throw switch of knife three, it is additionally coupled to be detected in MCU, whether the outside frequency markings of MCU detections two are online, if two outside frequencies
Mark is online, and SP3T switch select reference clock of any of the three kinds of frequency markings as DDS.
In embodiment 2, the present embodiment, two outside frequency markings are respectively 10MHz and 10.23MHz, and the first counter is mould 10
Counter, the second counter are the counter of mould 10230000, and the specific work process of the system is as follows：
The core devices of frequency marking part are 10MHz rubidium atomic clocks.Input of the rubidium atomic clock as DDS, it is possible to provide superelevation
Long-term stability and relatively low phase noise.
In the input of two kinds of outer frequency markings, there is coupler that signal is sent into detecting circuit, when detecting circuit is more than setting
Threshold value when, system judges that outside frequency marking is online.User internally can appoint between atomic clock and outside online frequency marking as needed
Meaning selection is used as reference clock by what selected signal gave DDS all the way, by SP3T switch.
1st, 10.23MHz fault simulations
10.23M generation and fault simulation are completed by DDS, and the purification of frequency spectrum locks phase crystal oscillator Lai real by the arrowband of rear class
It is existing.DDS is internally integrated 4~20 times of reference clock frequency multiplier, has programmable 48 bit frequency control register, the phase of 14
Position offset register and 20 slop control registers.
1. 10.23M signals are cut off suddenly
By controlling the power supply for switching cut-out 10.23MHz and locking phase crystal oscillator, realize and interrupt suddenly.
2. 10.23M frequency hoppings
Frequency hopping is realized by DDS frequency modulation.Frequency Adjustment precisionThe DDS of selection has 48 bit frequencies
Control word, clock are 10.23MHz (10MHz) × 16, then frequency Adjustment precisionDue to locking phase
VCOCXO tuning range is generally ± 0.3ppm used by crystal oscillator, i.e. frequency hopping scope is ± 3Hz.So, export
10.23MHz frequency can realize ± 3Hz tuning ranges, 0.6uHz stepping.
During for 10MHz with reference to 10.23MHz is produced, exist and draw frequency difference feelings caused by frequency control word non-integer situation
Condition, realize that 10.23MHz is identical with 10MHz frequency accuracies by backoff algorithm.
3. output phase saltus step
Phase hit is realized by DDS phase controllings.Frequency Adjustment precisionThe DDS of selection has 14
Position phase control words, then its phase adjustment precision is reachable
4. frequency drift
When analog frequency drifts about, effect that main analog clock frequency changes over time for a long time.DDS slop control word
Only 20, so its be up in the residence time of each frequency1s needs are not reached much.
Using single-chip microcomputer Interruption 1s, the function of frequency drift can be realized by refresh in real time DDS frequency control word.So frequency is floated
The scope of shifting is frequency hopping scope ± 3Hz, and drift velocity resolution ratio is 0.6uHz/s.
2nd, 1pps fault simulations
The fault simulation of 1pps signals is all realized in FPGA.10.23MHz signals caused by DDS are sent into FPGA, FPGA
Internal frequency multiplication of phase locked loop exports 102.3MHz clocks as FPGA work clocks.There are 3 counters inside FPGA：Mould 10 counts
Device, the counter of mould 10230000 and pulse width counter.10.23MHz frequency counter and pulse width counter.
102.3MHz clocks driving " counter of mould 10 " produces 10.23MHz outputs, then 10.23MHz clocks driving " mould caused by using
10230000 counters " produce 1PPS signals.
1. 1pps cycles and pulsewidth width adjustment
In the case where adjusting the cycle, the divide ratio of " counter of mould 10230000 " according to setting mechanical periodicity,
10.23MHz clock-driven counters count from accumulation loop between 0~" divide ratio ", and circulation every time produces a pulse letter
Number give pulse width counter；After pulse width counter receives the pulse of frequency counter, the accumulated counts since 0, when
Stop counting when reaching " pulse width " value, export high level in counting process, realize 1PPS period modulation and pulse width
Adjustment.
" counter of mould 10230000 " work clock is 10.23MHz, then can realize that the cycle of 97.8ns resolution ratio adjusts
It is whole；Pulse width counter work clock is 102.3MHz, then can realize the pulse width adjustment of 9.8ns resolution ratio.
2. 1pps phase adjustments
In this application, it is desirable to the 1PPS phase place changes caused by 10.23MHz frequency anomalies, it is in exception procedure and extensive
After answering normally, 10.23MHz and 1PPS phase relations are fixed all the time." counter of mould 10 " counts under 102.3M drivings and produces number
Word 10.23M clocks, counter modulus value are controlled by RS232, there is three kinds of mode of operations：Mould 10, mould 9, mould 11, as shown in Figure 2.
Under normal circumstances, that is, when not needing adjustment phase place, counter works are in the pattern of mould 10, counter cycle 10,10.23M height
Low level is each to continue 5 102.3M clocks.
Under the mode of operation of mould 9, it is 9 to count the cycle, and low level reduces by a clock cycle, and the duration is 4 clocks, high
Level is still 5 clocks, advanced 1/102.3M=9.775ns before now rising.
Under the mode of operation of mould 11, low level increases by 1 one clock cycle, rising edge hysteresis 9.775ns.
When it is ± P ns to need the amount into horizontal phasing control, "+" represents advanced, and "-" represents hysteresis, and host computer calculates mould
The 9 or work week issue N of mould 11：
N=floor (P*102.3M)
FPGA state machines count N number of work period according to designated mode mode of operation control counter, are then return to mould 10
Mode of operation, so as to complete advanced or hysteresis N*9.775ns phase adjustment.
Two counters should also include a reset terminal, when host computer initiates phase reset request, or the outside of gating
When 1PPS rising edges arrive, reset count, which is thought highly of, puts 10.23M and 1PPS phases.
(5) 1pps fault simulations
The 10.23MHz signals of arrowband lock phase crystal oscillator output, sine, LVDS, RS422 electricity are exported by interface driving circuit
Flat frequency standard signal；The 1PPS signals of FPGA outputs are by interface driving circuit output TTL, LVTTl, LVDS, RS422 level
Timing signal.
To sum up, presently preferred embodiments of the present invention is these are only, is not intended to limit the scope of the present invention.It is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements made etc., the protection of the present invention should be included in
Within the scope of.
Claims (2)
1. a kind of whole star single-particle soft error time-frequency failure ground simulation system, it is characterised in that the system includes a hilted broadsword
Three throw switches, Direct Digital Synthesizer DDS, micro-control unit chip MCU, fpga chip, arrowband lock phase crystal oscillator and
First drive circuit and the second drive circuit：
External three frequency markings in SP3T switch one end, the other end connect the DDS, for being DDS from three frequency markings
A frequency marking is selected as reference clock；
The DDS output ends connect FPGA, and DDS control terminal connects the MCU by spi bus；
The MCU receives the default output frequency of outside input by RS232 buses and default output phase, passes through spi bus
Connect DDS control terminal, be linked into by MCU interfaces in the FPGA；MCU is according to the default output frequency, total by SPI
Line is to DDS incoming frequencies control word and phase control words；
Be integrated with the FPGA phase-locked loop pll, the first counter, the second counter, with reference to 1pps counters, plus-minus the cycle control
Counter processed, pulse width counter, MCU interfaces and one and door；
The PLL receives DDS output signal, carries out exporting FPGA operating clock signals by PLL output end after frequency multiplication, should
FPGA operating clock signals provide drive signal for the first counter, with reference to 1pps counters and pulse width counter；
On the one hand the output end of first counter is connected to the drive end of second counter, on the other hand passes through arrowband
Lock phase crystal oscillator and the first drive circuit are exported；Wherein the count module of the first counter is determined by frequency multiplication of phase locked loop multiple；
The output end of second counter is connected to the pulse width counter input, the count module of the second counter by
Itself clock determines；The periodic Control end of second counter is by the MCU interfaces 1pps complete cycle phase signals, to realize
Periodic Controls of the MCU to the second counter；The drive end of second counter receives the output of the first counter as drive signal；
The input with reference to 1pps counters accesses 1pps outside markers, its in the case where FPGA operating clock signals drive,
By output end output 1pps count signal；
The output end of the pulse width counter connects the second drive circuit and exported；The reset terminal of pulse width counter
Access the FPGA operating clock signals；
The plus-minus periodic Control counter passes through the plus-minus periodic Control drive signal of the MCU interfaces MCU, the plus-minus
The output end of periodic Control counter is connected to the periodic Control end of first counter；
The MCU sends plus-minus periodic Control drive signal, 1pps complete cycles phase signal and reset request by MCU interfaces to be believed
Number, the count signal of the reseting request signal and the 1pps resets arteries and veins by described with door progress and output phase after operation
Punching, the phase reset pulse are respectively connected to the phase reset terminal to the first counter and the second counter；
Wherein, the frequency multiplication multiple of the PLL is 10, then the first counter is the counter of mould 10；The frequency marking includes a rubidium original
Secondary clock and two outside frequency markings；Described two outside frequency markings are additionally coupled in the MCU in addition to SP3T switch are linked into
Detected, the MCU detects whether two outside frequency markings are online, if two outside frequency markings are online, the SP3T is opened
Close the reference clock for selecting any of three kinds of frequency markings as DDS.
2. a kind of whole star single-particle soft error time-frequency failure ground simulation system as claimed in claim 1, it is characterised in that should
System has following fault simulation pattern：
1), 10.23MHz fault simulations, including 10.23M signals are cut off suddenly, 10.23M frequency hoppings, output phase saltus step, with
And frequency drift；
The rubidium atomic clock is 10MHz, and the outside frequency marking is 10MHz and 10.23MHz；
The 10.23M signals are cut off suddenly, by controlling the power supply realization for switching cut-out arrowband and locking phase crystal oscillator；
The 10.23M frequency hoppings, are realized by DDS frequency modulation, and the DDS has 48 bit frequency control words, and clock is
During 10.23MHz, frequency Adjustment precision is 0.6uHz；Used by the arrowband lock phase crystal oscillator VCOCXO tuning range for ±
0.3ppm, i.e. frequency hopping scope are ± 3Hz, then the frequency hopping for exporting 10.23MHz is：± 3Hz tuning ranges, 0.6uHz
Stepping saltus step；
The output phase saltus step, is realized by DDS phase controllings, and the phase adjustment precision of the DDS is 6ps；
The frequency drift is realized in the following way：The MCU Interruptions 1s, when interrupting generation, MCU passes through spi bus
To DDS incoming frequency control words, now the scope of frequency drift is frequency hopping scope ± 3Hz, and drift velocity resolution ratio is
For 0.6uHz/s；
2), 1pps fault simulations, including 1pps cycles and pulsewidth width adjustment and 1pps phase adjustments
The 1pps cycles and pulsewidth width adjustment, within the adjustment cycle of a setting, second counter is in FPGA works
Under the driving for making clock signal 10.23MHz, counted from accumulation loop between 0~divide ratio, circulation every time produces a pulse
Signal is sent to pulse width counter；After pulse width counter receives the pulse of frequency counter, add up meter since 0
Number, stop counting when reaching pulse width values, export high level in counting process, realize that 1PPS period modulation and pulse are wide
Degree adjustment；
Second counter works clock is 10.23MHz, then realizes the period modulation of 97.8ns resolution ratio；Pulse width counter
Work clock is 102.3MHz, then realizes the pulse width adjustment of 9.8ns resolution ratio；
The 1pps phase adjustments, the first counter counts under 102.3M drivings produces digital 10.23M clocks, and first counts
Device has three kinds of mode of operations：The pattern of mould 10, the pattern of mould 9, the pattern of mould 11；
When without adjustment phase place, counter works are respectively held in the pattern of mould 10, counter cycle 10,10.23M low and high level
Continue 5 102.3M clocks；
When it is ± P ns to need the amount into horizontal phasing control, wherein+represent advanced ,-represent hysteresis, host computer calculate mould 9 or
Work week issue N=floor (P*102.3M) of mould 11；
If advanced, then the pattern of mould 9 is selected, it is 9 to count the cycle, and relative to the pattern of mould 10, low level reduces by a clock cycle,
Duration is 4 clocks, and high level is still 5 clocks, now the advanced 9.775ns of rising edge；
If hysteresis, then the pattern of mould 11 is selected, it is 11 to count the cycle, and relative to the pattern of mould 10, low level increases by 1 one clock weeks
Phase, rising edge hysteresis 9.775ns.
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| CN105577164B (en) * | 2016-01-20 | 2018-05-08 | 北京时代民芯科技有限公司 | A kind of anti-single particle transient state differential driver suitable for aerospace FPGA |
| CN105759197B (en) * | 2016-03-28 | 2018-06-12 | 工业和信息化部电子第五研究所 | DDS devices single particle effect unusual waveforms capture systems and its catching method |
| CN109738732B (en) * | 2019-02-14 | 2021-04-20 | 北京润科通用技术有限公司 | Signal edge fault injection method and device |
| CN112383300A (en) * | 2020-10-26 | 2021-02-19 | 深圳市儒科电子有限公司 | High-precision frequency phase micro-jump meter |
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