CN111897201A - Clock calibration method and electronic equipment - Google Patents
Clock calibration method and electronic equipment Download PDFInfo
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- CN111897201A CN111897201A CN202010653404.6A CN202010653404A CN111897201A CN 111897201 A CN111897201 A CN 111897201A CN 202010653404 A CN202010653404 A CN 202010653404A CN 111897201 A CN111897201 A CN 111897201A
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Abstract
The embodiment of the invention provides a clock calibration method and electronic equipment, wherein the clock calibration method comprises the following steps: recording a first output frequency and a current time of a clock chip in response to a calibration signal of the clock chip; the current time is to-be-calibrated time; obtaining a first frequency mean value according to the first output frequency and a plurality of prestored second output frequencies; calculating the aging rate of the clock chip according to the first frequency average value and the second frequency average value; wherein the second frequency mean is determined from the plurality of second output frequencies; and calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time. Through the technical scheme of the invention, the clock precision of the clock chip electrically connected with the crystal oscillator can be improved under the condition that the crystal oscillator has an aging phenomenon.
Description
Technical Field
The present invention relates to the field of clock technologies, and in particular, to a clock calibration method and an electronic device.
Background
The clock chip realizes real-time display by timing year, month, week, day, hour, minute, second and the like. With the development of technologies such as communication, the requirement for the clock accuracy of the clock chip is higher and higher.
In the related art, a clock chip is connected with a crystal oscillator circuit, and an input frequency is provided to the clock chip through the crystal oscillator circuit, so that the clock chip generates a corresponding clock signal, and therefore, the clock accuracy of the clock chip is influenced by the input frequency of the crystal oscillator.
Along with the increase of the service time of the clock chip and the crystal oscillator, the crystal oscillator can age gradually, the aging of the crystal oscillator causes the deviation of the frequency of the crystal oscillator, and the deviation of the frequency of the crystal oscillator causes the deviation of the output time of the clock chip, thereby causing the reduction of the clock precision.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a clock calibration method to improve the clock accuracy of a clock chip electrically connected to a crystal oscillator under the condition that the crystal oscillator has an aging phenomenon.
Correspondingly, the embodiment of the invention also provides a clock calibration device, electronic equipment and a storage medium, which are used for ensuring the realization and application of the method.
In order to solve the above problem, an embodiment of a first aspect of the present invention discloses a clock calibration method, including:
recording a first output frequency and a current time of a clock chip in response to a calibration signal of the clock chip; the current time is to-be-calibrated time;
obtaining a first frequency mean value according to the first output frequency and a plurality of prestored second output frequencies;
calculating the aging rate of the clock chip according to the first frequency average value and the second frequency average value; wherein the second frequency mean is determined from the plurality of second output frequencies;
and calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time.
Optionally, the obtaining a first frequency average value according to the first output frequency and a plurality of pre-stored second output frequencies includes:
arranging the plurality of second output frequencies according to the sequence of the output time, and generating an output frequency queue;
inserting the first output frequency to the tail of the output frequency queue, and deleting a second output frequency at the head of the output frequency queue to generate an updated frequency array;
and determining the first frequency mean value according to the updated frequency sequence.
Optionally, the determining the first frequency average according to the updated frequency sequence further includes:
filtering out jitter data in the updated frequency sequence to generate a current frequency sequence;
and determining the frequency mean value of the current frequency sequence as the first frequency mean value.
Optionally, the calculating the aging rate of the clock chip according to the first frequency average and the second frequency average includes:
determining a difference between the first frequency mean and the second frequency mean;
determining a ratio between the difference and the second frequency average as the aging rate.
Optionally, the calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time includes:
determining historical time corresponding to a second output frequency obtained last in the output frequency queue;
obtaining the service time corresponding to the clock chip according to the time to be calibrated and the historical time;
obtaining compensation time according to the service time and the aging rate;
and calibrating the time to be calibrated by adopting the compensation time so as to enable the clock chip to output the calibrated time.
Optionally, the method further comprises:
updating the output frequency queue according to the current frequency sequence so as to determine the second frequency mean value according to the updated output frequency queue when executing next clock calibration; and
storing the calibrated clock signal as a historical clock signal corresponding to the first output frequency.
Optionally, the recording the first output frequency and the current time of the clock chip in response to the calibration signal of the clock chip includes:
responding to the calibration signal, and adjusting the chip temperature of a specified chip according to a preset adjusting mode, wherein the specified chip is the clock chip and/or a processor matched with the clock chip;
and recording the first output frequency and the current time when the temperature of the chip is detected to be adjusted to be greater than or equal to a preset temperature threshold value.
Optionally, the adjusting the chip temperature of the designated chip according to the preset adjusting manner includes:
and controlling a pre-stored high-power-consumption program to continuously run so as to increase the chip temperature of the appointed chip until the chip temperature is detected to be increased to be greater than or equal to the preset temperature threshold value.
Optionally, before recording the first output frequency of the clock chip and the current time in response to the calibration signal of the clock chip, the method further comprises:
and circularly running the high-power-consumption program, and recording second output frequency of the clock chip to generate a plurality of pre-stored second output frequencies under the condition that the temperature of the chip is detected to be greater than or equal to the preset temperature threshold value each time.
An embodiment of a second aspect of the present invention discloses a clock calibration apparatus, including:
the recording unit is used for responding to a calibration signal of a clock chip and recording a first output frequency and current time of the clock chip; the current time is to-be-calibrated time;
the acquisition unit is used for acquiring a first frequency mean value according to the first output frequency and a plurality of pre-stored second output frequencies;
the calculating unit is used for calculating the aging rate of the clock chip according to the first frequency average value and the second frequency average value; wherein the second frequency mean is determined from the plurality of second output frequencies;
and the calibration unit is used for calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time.
An embodiment of a third aspect of the invention discloses an electronic device, comprising: a processor, a clock chip, a crystal oscillator circuit and a memory, wherein,
the clock chip is electrically connected with the crystal oscillator circuit, the crystal oscillator circuit is used for providing input frequency for the clock chip, and the clock chip is used for configuring output frequency according to the input frequency;
the processor is respectively connected with the clock chip and the memory in a communication way, the processor can read the output frequency and the time signal of the clock chip,
the memory stores instructions executable by the processor to enable the processor to perform the steps of the clock calibration method of any one of the embodiments of the first aspect of the invention.
Optionally, the electronic device further comprises:
the circuit board comprises a circuit board, a first circuit board and a second circuit board, wherein at least one board surface of the circuit board is provided with a copper-clad area; the processor and the clock chip are arranged in the same copper-clad area, or one of the processor and the clock chip is arranged in the copper-clad area, and the other one of the processor and the clock chip is arranged on the board surface of the other side of the circuit substrate opposite to the copper-clad area;
the temperature sensor is arranged on the processor and electrically connected with the processor, and the temperature sensor is used for collecting the chip temperature of the processor.
Embodiments of the fourth aspect of the present invention disclose a computer-readable medium storing computer-executable instructions, wherein the computer-executable instructions are configured to perform the clock calibration method according to any one of the embodiments of the first aspect of the present invention.
According to the embodiment of the invention, when the processor acquires the calibration signal of the clock chip, the first output frequency and the current time of the clock chip are read, and the current time is the time required to be calibrated by the clock chip. The memory electrically connected with the processor stores a plurality of second output frequencies, the second output frequencies are historical output frequencies of the clock chip, a second frequency mean value is obtained according to the plurality of second output frequencies, a first frequency mean value is obtained according to the first output frequency and the plurality of second output frequencies, and then the aging rate of the clock chip can be evaluated according to the first frequency mean value and the second frequency mean value, wherein the aging rate of the clock chip can also be understood as the aging rate of a crystal oscillator for inputting the crystal oscillator frequency to the clock chip. After the aging rate of the clock chip is determined, the current time is compensated based on the aging rate so as to realize the calibration operation of the time to be calibrated, further reduce the timing deviation of the clock chip and ensure the timing precision of the clock chip, thereby being beneficial to prolonging the service life of a clock chip system comprising the clock chip and the crystal oscillator.
Drawings
FIG. 1 is a flow chart of the steps of one embodiment of a clock calibration method of the present invention;
FIG. 2 is a flow chart of steps in another embodiment of a clock calibration method of the present invention;
FIG. 3 is a flow chart of steps in yet another embodiment of a clock calibration method of the present invention;
FIG. 4 is a flowchart illustrating the steps of another embodiment of a clock calibration method of the present invention;
FIG. 5 is a flowchart illustrating the steps of another embodiment of a clock calibration method of the present invention;
FIG. 6 is a flowchart illustrating the steps of another embodiment of a clock calibration method of the present invention;
FIG. 7 is a block diagram of a clock calibration apparatus according to an embodiment of the present invention;
FIG. 8 is a block diagram of a clock calibration apparatus according to an embodiment of the present invention;
fig. 9 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
So that the manner in which the above recited objects, features and advantages of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. It should be noted that the embodiments of the present invention and features of the embodiments may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.
Referring to fig. 1, a flowchart illustrating steps of an embodiment of a clock calibration method of the present invention is shown, which may specifically include the following steps:
step S102, responding to a calibration signal of the clock chip, and recording a first output frequency and current time of the clock chip, wherein the current time is time to be calibrated.
The calibration signal of the clock chip may be a calibration signal received by the electronic device, the calibration signal may be sent by a server adapted to the electronic device, or may be obtained through a touch operation of a user, and in addition, the calibration signal may be automatically generated by setting a fixed calibration period when the calibration period is reached, for example, setting to automatically calibrate the clock chip once every half year.
In addition, the first output frequency of the clock chip can be used to provide a required clock frequency for other working chips.
Step S104, obtaining a first frequency average value according to the first output frequency and a plurality of pre-stored second output frequencies.
The first frequency average value is obtained according to the first output frequency and a plurality of pre-stored second output frequencies, and specifically, the first frequency average value can be obtained by performing average solution on the first output frequency and the plurality of second output frequencies.
The second output frequency may be a frequency obtained through testing before the clock chip and the crystal oscillator leave the factory.
And step S106, calculating the aging rate of the clock chip according to the first frequency average value and the second frequency average value, wherein the second frequency average value is determined according to the plurality of second output frequencies.
Specifically, the determining the second frequency average value according to the plurality of second output frequencies specifically includes determining an average value of the plurality of second output frequencies as the second frequency average value. However, as can be understood by those skilled in the art, each time the time calibration is performed, if there is a history of the time calibration performed, the first frequency average obtained in the previous time of performing the clock calibration is used as the second frequency average in the current time of performing the clock calibration.
The aging rate of the quartz crystal refers to the deviation of the quartz crystal in parameters such as frequency generated after the quartz crystal is used for a period of time, and the deviation of the crystal oscillator frequency correspondingly causes the deviation of the output frequency of the clock chip, so that the aging rate of the quartz crystal can be determined by detecting the aging rate of the clock chip, the aging rate of the clock chip is determined by detecting the deviation of the output frequency of the clock chip, and the deviation of the output frequency is calculated and determined by the first frequency mean value and the second frequency mean value.
And S108, calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time.
After the aging rate of the clock chip is determined, the current time is compensated based on the aging rate, so that the calibration operation of the time to be calibrated is realized, and the timing deviation of the clock chip is reduced.
In the clock calibration method provided by this embodiment, when the processor acquires the calibration signal of the clock chip, the first output frequency and the current time of the clock chip are read, where the current time is the time that the clock chip needs to be calibrated. The memory electrically connected with the processor stores a plurality of second output frequencies, the second output frequencies are historical output frequencies of the clock chip, a second frequency mean value is obtained according to the plurality of second output frequencies, a first frequency mean value is obtained according to the first output frequency and the plurality of second output frequencies, and then the aging rate of the clock chip can be evaluated according to the first frequency mean value and the second frequency mean value, wherein the aging rate of the clock chip can also be understood as the aging rate of a crystal oscillator for inputting the crystal oscillator frequency to the clock chip. The clock chip timing precision can be ensured based on the aging rate to the current time, so that the service life of a clock chip system comprising the clock chip and the crystal oscillator is prolonged.
Referring to fig. 2, a flowchart illustrating steps of another embodiment of a clock calibration method of the present invention is shown, which may specifically include the following steps:
step S202, responding to the calibration signal of the clock chip, and recording the first output frequency and the current time of the clock chip, wherein the current time is the time to be calibrated.
In this embodiment, a specific implementation process of step S202 may refer to a related description of step S102 in the embodiment shown in fig. 1, and is not described herein again.
And step S204, arranging the plurality of pre-stored second output frequencies according to the sequence of the output time, and generating an output frequency queue.
The output frequency queue is a group of frequency value arrays obtained finally by arranging a plurality of second output frequencies according to time sequence, and the output frequency queue is characterized by first-in first-out, last-in last-out and then-out, and comprises: f1, F2, F3, F4 and F5 … … Fn, wherein n is the number of second output frequencies, preferably n is more than or equal to 10, and n is an integral multiple of 5, F1 is the frequency value acquired earliest in the plurality of second output frequencies, and Fn is the frequency value acquired latest in the plurality of second output frequencies.
Step S206, insert the first output frequency to the tail of the output frequency queue, and delete the second output frequency at the head of the output frequency queue, so as to generate an updated frequency sequence.
Because the output frequency queue is characterized by first-in first-out and last-out, when the first output frequency Fn +1 is inserted to the tail of the output frequency queue, F1 is deleted correspondingly, and the obtained update frequency number is: f2, F3, F4 and F5 … … Fn + 1.
Step S208, determining a first frequency mean value according to the updated frequency sequence.
Specifically, the first frequency mean value, i.e., the average value of F2, F3, F4, F5 … … Fn +1, is determined according to the updated frequency sequence to serve as the first frequency mean value, the first frequency mean value reflects the shifted output frequency of the current clock chip, and the second frequency mean value reflects the standard value of the output frequency of the clock chip, so as to calculate the aging rate of the clock chip according to the first frequency mean value and the second frequency mean value.
Step S210, calculating an aging rate of the clock chip according to the first frequency average and a second frequency average, wherein the second frequency average is determined according to the plurality of second output frequencies.
Step S212, calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time.
In this embodiment, a specific implementation process of step S202 may refer to a description related to step S106 and step S108 in the embodiment shown in fig. 1, and is not described herein again.
In this embodiment, the output frequency queue and the updated frequency array are generated in the form of a queue to correspondingly calculate the second frequency average value and the first frequency average value, and the aging rate of the clock chip is calculated by using the second frequency average value and the first frequency average value, so that the calculation accuracy of the aging rate can be ensured, and the reliability of clock calibration according to the aging rate can be ensured.
Referring to fig. 3, a flowchart illustrating steps of another embodiment of a clock calibration method according to the present invention is shown, which may specifically include the following steps:
step S302, responding to the calibration signal of the clock chip, and recording the first output frequency and the current time of the clock chip, wherein the current time is the time to be calibrated.
Step S304, a plurality of second output frequencies which are pre-stored are arranged according to the sequence of the output time, and an output frequency queue is generated.
Step S306, insert the first output frequency to the tail of the output frequency queue, and delete the second output frequency at the head of the output frequency queue, so as to generate an updated frequency sequence.
In this embodiment, for specific implementation processes of step S302 to step S306, reference may be made to the related descriptions of step S202 to step S206 in the embodiment shown in fig. 2, and details are not repeated here.
Step S308, filter the jitter data in the updated frequency sequence to generate the current frequency sequence.
The jitter data can be understood as the output frequency when the clock chip works abnormally, and one way of filtering the jitter data in the updated frequency sequence is to remove the output frequency with abnormal frequency value, so as to ensure the reliability of the calculation of the first frequency mean value.
On the premise that n is more than or equal to 10 and n is an integral multiple of 5, n/5 with the smallest frequency value and the largest n/5 are removed from the update frequency queues { F2, F3, F4 and F5 … … Fn +1 }.
In step S310, the frequency average of the current frequency sequence is determined as the first frequency average.
Step S312, calculating the aging rate of the clock chip according to the first frequency average and the second frequency average, wherein the second frequency average is determined according to the plurality of second output frequencies.
Specifically, in the calculation of the second frequency average value, the smallest n/5 frequency values are removed from the output frequency queues { F1, F2, F3, F4, and F5 … … Fn }, and then the largest n/5 frequency values are removed, and the average value is calculated as the second frequency average value.
And step S314, calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time.
In this embodiment, on the basis of generating the updated frequency sequence, the jitter data is further filtered to improve the calculation accuracy of the first frequency average and the second frequency average, which is further beneficial to improving the calculation accuracy of the aging rate, thereby improving the calibration accuracy of the clock calibration.
Referring to fig. 4, a flowchart illustrating steps of another embodiment of a clock calibration method of the present invention is shown, which may specifically include the following steps:
step S402, responding to a calibration signal of a clock chip, and recording a first output frequency and current time of the clock chip; the current time is the time to be calibrated.
Step S404, arranging the plurality of pre-stored second output frequencies according to the output time sequence, and generating an output frequency queue.
Step S406, insert the first output frequency to the tail of the output frequency queue, and delete the second output frequency at the head of the output frequency queue, so as to generate an updated frequency sequence.
In step S408, the jitter data in the updated frequency sequence is filtered out to generate the current frequency sequence.
In step S410, the frequency mean value of the current frequency sequence is determined as the first frequency mean value.
In this embodiment, for a specific implementation process of steps S402 to S410, reference may be made to the related description of steps S302 to S310 in the embodiment shown in fig. 3, and details are not repeated here.
In step S412, a difference between the first frequency average and the second frequency average is determined.
In step S414, the ratio between the difference and the second frequency average is determined as the aging rate.
Step S416, calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time.
In the embodiment, the aging rate is determined by adopting the ratio of the difference value between the first frequency mean value and the second frequency mean value to the second frequency mean value, so that the offset rate of the crystal oscillator frequency can be more accurately estimated, the time to be calibrated of the clock chip is calibrated by the aging rate, and reliable clock calibration is realized on the premise of not increasing the hardware cost.
Referring to fig. 5, a flowchart illustrating steps of another embodiment of a clock calibration method of the present invention is shown, which may specifically include the following steps:
step S502, responding to a calibration signal of a clock chip, and recording a first output frequency and current time of the clock chip; the current time is the time to be calibrated.
Step S504, arranging the plurality of pre-stored second output frequencies according to the output time sequence, and generating an output frequency queue.
Step S506, the first output frequency is inserted to the tail of the output frequency queue, and the second output frequency at the head of the output frequency queue is deleted, so as to generate an updated frequency sequence.
Step S508, filter out the jitter data in the updated frequency sequence to generate the current frequency sequence.
In step S510, the frequency average of the current frequency sequence is determined as the first frequency average.
In step S512, a difference between the first frequency mean value and the second frequency mean value is determined.
In step S514, the ratio between the difference and the second frequency average is determined as the aging rate.
In this embodiment, for specific implementation processes of step S502 to step S514, reference may be made to related descriptions of step S402 to step S414 in the embodiment shown in fig. 4, and details are not described here again.
In step S516, the historical time corresponding to the second output frequency obtained last in the output frequency queue is determined.
Step S518, obtaining the usage duration corresponding to the clock chip according to the time to be calibrated and the historical time.
Step S520, obtaining the compensation time according to the use duration and the aging rate.
Step S522, calibrating the time to be calibrated by using the compensation time, so that the clock chip outputs the calibrated time.
In this embodiment, the historical time may be understood as a starting point of time for starting use of the clock chip, the use duration corresponding to the clock chip may be obtained by combining the time to be calibrated, and the compensation time may be determined according to the use duration and the aging rate, so as to realize accurate compensation of the time to be calibrated.
Preferably, after step S522, the time calibration method further includes:
and updating the output frequency queue according to the current frequency sequence so as to determine a second frequency mean value according to the updated output frequency queue when next clock calibration is executed. And
the calibrated clock signal is stored as a historical clock signal corresponding to the first output frequency.
In this embodiment, after each time of time calibration, the calibrated time and the corresponding first output frequency are stored as the last obtained second output frequency in the historical time and output frequency queue, so that the data are used as the compensation reference in the next time of calibration.
Referring to fig. 6, a flowchart illustrating steps of another embodiment of a clock calibration method of the present invention is shown, which may specifically include the following steps:
step S602, in response to the calibration signal, adjusting the chip temperature of the designated chip according to a preset adjustment manner, where the designated chip is a clock chip and/or a processor configured to cooperate with the clock chip.
In step S604, it is detected that the chip temperature is adjusted to be greater than or equal to the preset temperature threshold, and the first output frequency and the current time are recorded.
Wherein, because different crystal oscillators have different frequency temperature characteristics, so the oscillation frequency of crystal oscillator is influenced a lot by ambient temperature, in the time calibration scheme of this application, through being adjusted to the output frequency that corresponds of record under the condition that is greater than or equal to preset temperature threshold value at the chip temperature, like this, can eliminate because the influence of the temperature difference that the difference in seasons or place latitude caused to crystal oscillator oscillation frequency, guarantee output frequency and read the uniformity of operating mode environment, and then obtain the ageing rate after eliminating the temperature influence, make the time calibration scheme based on this ageing rate execution more have the commonality.
Optionally, before recording the first output frequency of the clock chip and the current time in response to the calibration signal of the clock chip, the method further comprises:
and circularly running the high-power-consumption program, and recording the second output frequency of the clock chip to generate a plurality of prestored second output frequencies under the condition that the temperature of the chip is detected to be greater than or equal to the preset temperature threshold value each time.
As an optional implementation manner of step S602, the method includes: and controlling the pre-stored high-power-consumption program to continuously run so as to improve the chip temperature of the appointed chip until the chip temperature is detected to be increased to be greater than or equal to a preset temperature threshold value.
Specifically, as a preferred implementation scheme, a chip is designated as a processor, a high-power-consumption program is called and run by controlling the processor, the high-power-consumption program corresponds to a higher heating value, and the chip temperature of the processor is adjusted in such a way, so that the acquired chip temperature of the processor is used as the chip temperature of a clock chip.
The following arrangement mode of combining the processor and the clock chip comprises the following steps: at least one board surface of the circuit substrate is provided with a copper-clad area; the processor and the clock chip are arranged in the same copper-clad area, or one of the processor and the clock chip is arranged in the copper-clad area, and the other one of the processor and the clock chip is arranged on the other side of the circuit substrate opposite to the copper-clad area; and the temperature sensor is arranged on the processor and electrically connected with the processor, and is used for acquiring the chip temperature of the processor and enabling the chip temperature of the processor to be close to or the same as the chip temperature of the clock chip.
Step S606, arranging the plurality of pre-stored second output frequencies according to the sequence of the output time, and generating an output frequency queue.
Step S608, insert the first output frequency to the tail of the output frequency queue, and delete the second output frequency at the head of the output frequency queue, so as to generate the update frequency sequence.
Step S610, filter the jitter data in the updated frequency sequence to generate the current frequency sequence.
In step S612, the frequency average of the current frequency sequence is determined as the first frequency average.
In step S614, a difference between the first frequency mean value and the second frequency mean value is determined.
In step S616, the ratio between the difference and the second frequency average is determined as the aging rate.
Step 618, determining the historical time corresponding to the second output frequency finally obtained in the output frequency queue;
step S620, obtaining the use duration corresponding to the clock chip according to the time to be calibrated and the historical time;
in step S622, the compensation time is obtained according to the usage duration and the aging rate.
Step S624, calibrating the time to be calibrated by using the compensation time, so that the clock chip outputs the calibrated time.
In this embodiment, for specific implementation processes of step S606 to step S624, reference may be made to related descriptions of step S504 to step S522 in the embodiment shown in fig. 5, and details are not described here again.
Referring to fig. 7, a flowchart illustrating steps of another embodiment of a clock calibration method according to the present invention is shown, which may specifically include the following steps:
before the product leaves a factory, the main chip increases the temperature of the system through a high-energy-consumption algorithm which is continuously operated in a circulating mode, and when the temperature reaches a high-temperature alarm threshold value, the second output frequency F of the clock chip at the moment is read and recorded.
The number of times of detecting the second output frequency reading of the clock chip reaches n times, and a group of output frequency number sequences { F1, F2, F3, F4, F5 … … Fn } is obtained, wherein n is not less than 10 and is an integral multiple of 5.
And removing the n/5 with the minimum frequency values from the output frequency sequence, removing the n/5 with the maximum frequency values, calculating the average value of the residual frequencies to be used as a second frequency average value Fi, and recording the current historical time read from the clock chip as Ti.
In the use of a product, the main chip obtains the current first output frequency Fn +1 by circularly running a high-energy-consumption algorithm, F1 in an output frequency number sequence { F1, F2, F3, F4 and F5 … … Fn } is removed, then Fn +1 is added to the end of the number sequence, and an updated frequency number sequence { F2, F3, F4 and F5 … … Fn +1} is obtained.
And removing the n/5 with the minimum frequency values from the updated frequency array, and then removing the n/5 with the maximum frequency values to obtain the current frequency array, calculating the average value of the current frequency array to be Fm, and recording the current time Tm read from the clock chip, namely the time to be calibrated.
The aging rate at this time was calculated to be (Fi-Fm)/Fi.
And compensating the clock according to the aging rate by using the current time Tr ═ Tm + (Tm-Ti) × (Fi-Fm)/Fi.
Tr is saved as new Ti and Fm is saved as new Fi.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Referring to fig. 7, a block diagram of a clock calibration apparatus 700 according to an embodiment of the present invention is shown, and may specifically include a recording unit 702, an obtaining unit 704, a calculating unit 706, and a calibrating unit 708.
The recording unit 702 is configured to record a first output frequency and a current time of the clock chip in response to a calibration signal of the clock chip; the current time is the time to be calibrated.
The obtaining unit 704 is configured to obtain a first frequency average value according to the first output frequency and a plurality of pre-stored second output frequencies.
The calculating unit 706 is configured to calculate an aging rate of the clock chip according to the first frequency average value and the second frequency average value; wherein the second frequency mean is determined according to a plurality of second output frequencies.
The calibration unit 708 is configured to calibrate the time to be calibrated of the clock chip according to the aging rate, and obtain a calibrated time.
Alternatively, referring to fig. 8, the obtaining unit 704 includes: a generating subunit 7042, configured to arrange the plurality of second output frequencies according to the order of the output time, and generate an output frequency queue; generating subunit 7042 is further configured to: inserting the first output frequency to the tail of the output frequency queue, and deleting the second output frequency at the head of the output frequency queue to generate an updating frequency array; a first determining subunit 7044, configured to determine the first frequency average according to the updated frequency sequence.
Optionally, the first determining subunit 7044 further includes: a filtering subunit 7044A, configured to filter out jitter data in the updated frequency sequence to generate a current frequency sequence; first determining subunit 7044 is further configured to: and determining the frequency average value of the current frequency sequence as the first frequency average value.
Optionally, the calculation unit 706 comprises: a second determining subunit 7062, configured to determine a difference between the first frequency average value and the second frequency average value; second determining subunit 7062 is further configured to: the ratio between the difference and the second frequency average is determined as the aging rate.
Optionally, the calibration unit 708 comprises: a third determining subunit 7082, configured to determine a historical time corresponding to a second output frequency obtained last in the output frequency queue; the obtaining subunit 7084 is configured to obtain a use duration corresponding to the clock chip according to the time to be calibrated and the historical time; the obtaining subunit 7084 is further configured to: obtaining compensation time according to the use duration and the aging rate; the calibration subunit 7086 is configured to calibrate the time to be calibrated by using the compensation time, so that the clock chip outputs the calibrated time.
Optionally, the apparatus 700 further comprises: an updating unit 710, configured to update the output frequency queue according to the current frequency sequence, so as to determine a second frequency average value according to the updated output frequency queue when performing next clock calibration; and a storage unit 712 for storing the calibrated clock signal as a historical clock signal corresponding to the first output frequency.
Alternatively, the recording unit 702 includes: the adjusting subunit 7022 is configured to adjust, in response to the calibration signal, a chip temperature of the designated chip according to a preset adjusting manner, where the designated chip is a clock chip and/or a processor configured to cooperate with the clock chip; the recording subunit 7024 is configured to detect that the chip temperature is adjusted to be greater than or equal to a preset temperature threshold, and record the first output frequency and the current time.
Optionally, the adjusting subunit 7022 includes: the control subunit 7022A is configured to control the pre-stored high power consumption program to continuously run so as to increase the chip temperature of the designated chip until it is detected that the chip temperature rises to be greater than or equal to a preset temperature threshold.
Optionally, the apparatus 700 further comprises: and the generating unit 714 is used for circularly running the high-power-consumption program, and recording the second output frequency of the clock chip to generate a plurality of prestored second output frequencies under the condition that the temperature of the chip is detected to be greater than or equal to the preset temperature threshold value each time.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
Referring to fig. 9, there is shown a block diagram of an electronic device of the present invention, including: the clock chip 904 is electrically connected with the crystal oscillator circuit 906, the crystal oscillator circuit 906 is used for providing an input frequency for the clock chip 904, and the clock chip 904 is used for configuring an output frequency according to the input frequency; the processor 902 is communicatively connected to the clock chip 904 and the memory 908, respectively, the processor 902 can read the output frequency and the time signal of the clock chip 904, and the memory 908 stores instructions executable by the processor 902, so that the processor 902 can perform the steps of the clock calibration method according to any one of the above embodiments of the present invention.
Optionally, the electronic device further comprises: the circuit board comprises a circuit board, wherein at least one board surface of the circuit board is provided with a copper-clad area; the processor and the clock chip are arranged in the same copper-clad area, or one of the processor and the clock chip is arranged in the copper-clad area, and the other one of the processor and the clock chip is arranged on the other side of the circuit substrate opposite to the copper-clad area; and the temperature sensor is arranged on the processor and electrically connected with the processor, and is used for acquiring the temperature of the chip of the processor.
When the hardware principle is designed, the oscillation frequency of the clock chip is output to the I/O input port of the main chip through the I/O port.
When the hardware circuit board is designed, the device in the clock system is placed near the main chip or at the position of the circuit board on the reverse side of the main chip, and shares a heat dissipation copper layer with the main chip, so that heat conduction is facilitated.
And starting a main chip temperature detection function and setting interrupt enable.
Before the product leaves a factory, the main chip raises the temperature of the system by continuously operating a high-energy-consumption algorithm, and when the temperature reaches a high-temperature alarm threshold value, the frequency F output by the clock chip at the moment is read and recorded.
The embodiment of the invention can be applied to electronic equipment with a clock function, and the electronic equipment can be mobile electronic equipment or non-mobile electronic equipment. By way of example, the mobile electronic device may be a cryptographic device, a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the cryptographic device may be a tax Ukey, and the non-mobile electronic device may be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a television (television, TV), a teller machine, a self-service machine, and the like, and the embodiments of the present application are not limited in particular.
The computer-readable medium of an embodiment of the present invention stores computer-executable instructions for performing:
recording a first output frequency and a current time of a clock chip in response to a calibration signal of the clock chip; the current time is to-be-calibrated time;
obtaining a first frequency mean value according to the first output frequency and a plurality of prestored second output frequencies;
calculating the aging rate of the clock chip according to the first frequency average value and the second frequency average value; wherein the second frequency mean is determined from the plurality of second output frequencies;
and calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time.
Optionally, the obtaining a first frequency average value according to the first output frequency and a plurality of pre-stored second output frequencies includes:
arranging the plurality of second output frequencies according to the sequence of the output time, and generating an output frequency queue;
inserting the first output frequency to the tail of the output frequency queue, and deleting a second output frequency at the head of the output frequency queue to generate an updated frequency array;
and determining the first frequency mean value according to the updated frequency sequence.
Optionally, the determining the first frequency average according to the updated frequency sequence further includes:
filtering out jitter data in the updated frequency sequence to generate a current frequency sequence;
and determining the frequency mean value of the current frequency sequence as the first frequency mean value.
Optionally, the calculating the aging rate of the clock chip according to the first frequency average and the second frequency average includes:
determining a difference between the first frequency mean and the second frequency mean;
determining a ratio between the difference and the second frequency average as the aging rate.
Optionally, the calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time includes:
determining historical time corresponding to a second output frequency obtained last in the output frequency queue;
obtaining the service time corresponding to the clock chip according to the time to be calibrated and the historical time;
obtaining compensation time according to the service time and the aging rate;
and calibrating the time to be calibrated by adopting the compensation time so as to enable the clock chip to output the calibrated time.
Optionally, the method further comprises:
updating the output frequency queue according to the current frequency sequence so as to determine the second frequency mean value according to the updated output frequency queue when executing next clock calibration; and
storing the calibrated clock signal as a historical clock signal corresponding to the first output frequency.
Optionally, the recording the first output frequency and the current time of the clock chip in response to the calibration signal of the clock chip includes:
responding to the calibration signal, and adjusting the chip temperature of a specified chip according to a preset adjusting mode, wherein the specified chip is the clock chip and/or a processor matched with the clock chip;
and recording the first output frequency and the current time when the temperature of the chip is detected to be adjusted to be greater than or equal to a preset temperature threshold value.
Optionally, the adjusting the chip temperature of the designated chip according to the preset adjusting manner includes:
and controlling a pre-stored high-power-consumption program to continuously run so as to increase the chip temperature of the appointed chip until the chip temperature is detected to be increased to be greater than or equal to the preset temperature threshold value.
Optionally, before recording the first output frequency of the clock chip and the current time in response to the calibration signal of the clock chip, the method further comprises:
and circularly running the high-power-consumption program, and recording second output frequency of the clock chip to generate a plurality of pre-stored second output frequencies under the condition that the temperature of the chip is detected to be greater than or equal to the preset temperature threshold value each time.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The clock calibration method and the clock calibration device provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A method of clock calibration, comprising:
recording a first output frequency and a current time of a clock chip in response to a calibration signal of the clock chip; the current time is to-be-calibrated time;
obtaining a first frequency mean value according to the first output frequency and a plurality of prestored second output frequencies;
calculating the aging rate of the clock chip according to the first frequency average value and the second frequency average value; wherein the second frequency mean is determined from the plurality of second output frequencies;
and calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time.
2. The method of claim 1, wherein obtaining a first frequency average value according to the first output frequency and a plurality of pre-stored second output frequencies comprises:
arranging the plurality of second output frequencies according to the sequence of the output time, and generating an output frequency queue;
inserting the first output frequency to the tail of the output frequency queue, and deleting a second output frequency at the head of the output frequency queue to generate an updated frequency array;
and determining the first frequency mean value according to the updated frequency sequence.
3. The method of claim 2, wherein determining the first frequency average according to the updated frequency sequence further comprises:
filtering out jitter data in the updated frequency sequence to generate a current frequency sequence;
and determining the frequency mean value of the current frequency sequence as the first frequency mean value.
4. The method of claim 3, wherein calculating the aging rate of the clock chip according to the first frequency average and the second frequency average comprises:
determining a difference between the first frequency mean and the second frequency mean;
determining a ratio between the difference and the second frequency average as the aging rate.
5. The method according to claim 4, wherein the calibrating the time to be calibrated of the clock chip according to the aging rate to obtain the calibrated time comprises:
determining historical time corresponding to a second output frequency obtained last in the output frequency queue;
obtaining the service time corresponding to the clock chip according to the time to be calibrated and the historical time;
obtaining compensation time according to the service time and the aging rate;
and calibrating the time to be calibrated by adopting the compensation time so as to enable the clock chip to output the calibrated time.
6. The method of claim 5, further comprising:
updating the output frequency queue according to the current frequency sequence so as to determine the second frequency mean value according to the updated output frequency queue when executing next clock calibration; and
storing the calibrated clock signal as a historical clock signal corresponding to the first output frequency.
7. The method of any one of claims 1 to 6, wherein recording the first output frequency and the current time of the clock chip in response to the calibration signal of the clock chip comprises:
responding to the calibration signal, and adjusting the chip temperature of a specified chip according to a preset adjusting mode, wherein the specified chip is the clock chip and/or a processor matched with the clock chip;
and recording the first output frequency and the current time when the temperature of the chip is detected to be adjusted to be greater than or equal to a preset temperature threshold value.
8. The method of claim 7, wherein the adjusting the chip temperature of the specific chip according to the preset adjusting manner comprises:
and controlling a pre-stored high-power-consumption program to continuously run so as to increase the chip temperature of the appointed chip until the chip temperature is detected to be increased to be greater than or equal to the preset temperature threshold value.
9. The method of claim 8, wherein prior to recording the first output frequency and the current time of the clock chip in response to the calibration signal of the clock chip, the method further comprises:
and circularly running the high-power-consumption program, and recording second output frequency of the clock chip to generate a plurality of pre-stored second output frequencies under the condition that the temperature of the chip is detected to be greater than or equal to the preset temperature threshold value each time.
10. An electronic device, comprising: a processor, a clock chip, a crystal oscillator circuit and a memory, wherein,
the clock chip is electrically connected with the crystal oscillator circuit, the crystal oscillator circuit is used for providing input frequency for the clock chip, and the clock chip is used for configuring output frequency according to the input frequency;
the processor is respectively connected with the clock chip and the memory in a communication way, the processor can read the output frequency and the time signal of the clock chip,
the memory stores instructions executable by the processor to enable the processor to perform the steps of the clock calibration method of any one of claims 1 to 9.
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