CN108414841A - A kind of pulse per second (PPS) stable measurement device - Google Patents
A kind of pulse per second (PPS) stable measurement device Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
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Abstract
The present invention is suitable for electronic instrument technical field, provides a kind of pulse per second (PPS) stable measurement device, including GPS receiver, combining unit tester, first timer, second timer, digital signal processor, asynchronous memory interface and display；GPS receiver sends the first pps pulse per second signal to first timer；Combining unit tester sends the second pps pulse per second signal to the second timer；The first pps pulse per second signal of first timer pair is counted and is latched and exported；The second pps pulse per second signal of second timer pair is counted and is latched and exported；Digital signal processor calculates the pulse per second (PPS) stability of combining unit tester according to the first pps pulse per second signal and the second pps pulse per second signal, and above-mentioned pulse per second (PPS) stability is sent to display by asynchronous memory interface and is shown.Through the invention, measurement procedure can be effectively reduced and shorten time of measuring, to reduce the measurement cost to the pulse per second (PPS) stability of combining unit tester.
Description
Technical field
The invention belongs to electronic instrument technical field more particularly to a kind of pulse per second (PPS) stable measurement devices.
Background technology
With extensive use of the intelligent substation in China's electric power networks process of construction, combining unit and intelligent terminal
Exist, combining unit respectively as the important equipment of process network in intelligent substation process of construction and the content of composed structure
Under the control of pulse per second (PPS), it is digital quantity to synchronize sample conversion for the analog quantity to whole station, therefore it is required that every merging
The internal clocking of unit can keep certain punctual precision.And the punctual precision of combining unit by combining unit tester Lai complete
At providing that the class of accuracy of calibrator (-ter) unit is needed higher than tested 2 grades of equipment or 1/4 times according to metrological regulation.
But the measuring instrument of higher accuracy is needed for the pulse per second (PPS) stable measurement of combining unit tester, such as
10-10Time interval/frequency counter of grade high accuracy.The time interval of this high accuracy/frequency counter price is high
Expensive, equipment is big, and professional is needed to calibrate so as to the measurement cost of the pulse per second (PPS) stability of combining unit tester
High, flow complexity, detection time are long.
Invention content
In view of this, an embodiment of the present invention provides a kind of pulse per second (PPS) stable measurement device, to solve in the prior art
Of high cost to the pulse per second (PPS) stable measurement of combining unit tester, flow is complicated, the problem of detection time length.
An embodiment of the present invention provides a kind of pulse per second (PPS) stable measurement devices, including GPS receiver, combining unit to verify
Instrument, first timer, second timer, digital signal processor, asynchronous memory interface and display；
The first input end of the output end of above-mentioned GPS receiver and first timer connects, combining unit tester it is defeated
The first input end of outlet and second timer connects, the input terminal of digital signal processor respectively with the output of first timer
After end is connected with the output end of second timer, the output end of digital signal processor and the input terminal of asynchronous memory interface connect
It connects, the output end of asynchronous memory interface and the input terminal of display connect；
Above-mentioned GPS receiver sends the first pps pulse per second signal to first timer；Combining unit tester is to described second
Timer sends the second pps pulse per second signal；
The first pps pulse per second signal of above-mentioned first timer pair is counted and is latched and exported；
The second pps pulse per second signal of above-mentioned second timer pair is counted and is latched and exported；
The first pps pulse per second signal and second timer that above-mentioned digital signal processor is exported according to first timer export
The second pps pulse per second signal, calculate the pulse per second (PPS) stability of combining unit tester, and above-mentioned pulse per second (PPS) stability passed through different
Step memory interface is sent to display and is shown.
Optionally, above-mentioned pulse per second (PPS) stable measurement device further includes crystal；
The output end of crystal and the second input terminal of the second input terminal of first timer and second timer connect；
Crystal generates base frequency signal, and base frequency signal is synchronized and is sent to first timer and the second timing
Device.
Optionally, above-mentioned pulse per second (PPS) stable measurement device further includes frequency multiplier circuit；
The input terminal of frequency multiplier circuit and the output end of crystal connect, the output end of frequency multiplier circuit and the second of first timer
Input terminal is connected with the second input terminal of second timer；
The base frequency signal that frequency multiplier circuit frequency-doubling crystal generates, and the base frequency signal after frequency multiplication is synchronized and is sent to
First timer and second timer.
Optionally, above-mentioned frequency multiplier circuit includes phase phase discriminator, loop filter, voltage controlled oscillator, frequency divider and clock
Frequency divider；
Above-mentioned phase phase discriminator, loop filter, voltage controlled oscillator and Clock dividers are sequentially connected, voltage controlled oscillator
Output end is connected by the input terminal of frequency divider and voltage controlled oscillator；
Phase phase discriminator measures the phase of the output frequency and base frequency signal of frequency divider；
The output frequency of voltage controlled oscillator is directly proportional to the output voltage of loop filter；
When the frequency of voltage controlled oscillator output is the frequency dividing multiple of crystal and frequency divider, the output frequency of Clock dividers
For the half of the output frequency of voltage controlled oscillator.
Optionally, above-mentioned first timer or second timer include falling edge detectors, counter and period register；
The output end of falling edge detectors and the first input end of the input terminal of counter and period register connect, and count
The output end of device and the second input terminal of period register connect.
Optionally, when above-mentioned falling edge detectors detect that base frequency signal exports rising edge, pulse-triggered letter is generated
Number；
When falling edge detectors detect pulse triggering signal output rising edge and the second pulse signal is not detected, count
Device is counted, and count results are latching to period register；
When falling edge detectors detect pulse triggering signal output rising edge and detect the second pulse signal, counter
It counts and resets.
Optionally, above-mentioned pulse per second (PPS) stable measurement device further includes digital signal processing chip, and frequency multiplier circuit, first are determined
When device, second timer, digital signal processor and asynchronous memory interface be integrated on digital signal processing chip.
Optionally, second second exported according to the first pps pulse per second signal of above-mentioned first timer output and second timer
Pulse signal calculates the pulse per second (PPS) stability of combining unit tester, including：
It obtains first timer in preset time and receives the first count value counted after the first pps pulse per second signal；
It is synchronous to obtain the second count value counted after the second pps pulse per second signal of second timer reception in preset time；
The resolution ratio of combining unit tester is calculated according to the first count value and the second count value；
When resolution ratio reaches preset standard, n times obtain the second count value of second timer in preset time, record N
The second count value of group；Wherein N is the integer more than 1；
The pulse per second (PPS) stability of combining unit tester is calculated according to the second count value of N groups.
Optionally, the resolution ratio of combining unit tester is calculated according to above-mentioned first count value and the second count value, including：
According to the first count value, the time base period of the first pps pulse per second signal is calculated, formula is：
The first count value sum total in time base period=preset time/preset time；
It according to time base period, calculates and obtains the time that the second count value uses, formula is：
Second count value sum total × time base period in time=preset time；
According to the when base nominal frequency of first timer or second timer, first timer or second timer are calculated
Resolution ratio, formula are：
Resolution ratio=1/ (when base nominal frequency × preset time).
Optionally, the pulse per second (PPS) stability of the combining unit tester is calculated according to above-mentioned the second count value of N groups, is wrapped
It includes：
The correct time of every group of second count value in N the second count values of group is calculated, formula is：
The correct time of N groups=(the second count value sum total × preset time of N groups/the first count value sum total-is preset
Time)/preset time；
According to correct time, the basic pulse per second (PPS) stability of combining unit tester is calculated, formula is：
Basic pulse per second (PPS) stability=| the correct time of correct time the-the N groups of N-1 groups |；
Obtain the greatest measure in basic pulse per second (PPS) stability, the pulse per second (PPS) stability as combining unit tester.
Existing advantageous effect is the embodiment of the present invention compared with prior art：By counting triggering in timer and resetting
The asynchronization of triggering and the periodic characteristics of pps pulse per second signal are established in conjunction with the long-time stability of GPS and accuracy and are measured
Time reference, to realize the high-resolution to the pulse per second (PPS) stability of combining unit tester, high accuracy measures.Pass through
Pulse per second (PPS) stable measurement device provided by the invention, can effectively reduce measurement procedure and time of measuring, to reduce pairing
And the measurement cost of the pulse per second (PPS) stability of unit tester.
Description of the drawings
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description be only the present invention some
Embodiment for those of ordinary skill in the art without having to pay creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the structural schematic diagram for the pulse per second (PPS) stable measurement device that the embodiment of the present invention one provides；
Fig. 2 is the structural schematic diagram of another pulse per second (PPS) stable measurement device provided by Embodiment 2 of the present invention；
Fig. 3 is the structural schematic diagram of another pulse per second (PPS) stable measurement device provided by Embodiment 2 of the present invention；
Fig. 4 is the structural schematic diagram of frequency multiplier circuit provided by Embodiment 2 of the present invention；
Fig. 5 is the structural schematic diagram of the first timer that the embodiment of the present invention three provides or second timer；
Fig. 6 is the calculation process schematic diagram for the pulse per second (PPS) stability that the embodiment of the present invention four provides；
Fig. 7 is the specific calculation process schematic diagram of step S603 in the embodiment of the present invention four；
Fig. 8 is the specific calculation process schematic diagram of step S605 in the embodiment of the present invention four.
Specific implementation mode
In being described below, for illustration and not for limitation, it is proposed that such as tool of particular system structure, technology etc
Body details, to understand thoroughly the embodiment of the present invention.However, it will be clear to one skilled in the art that there is no these specific
The present invention can also be realized in the other embodiments of details.In other situations, it omits to well-known system, device, electricity
The detailed description of road and method, in case unnecessary details interferes description of the invention.
In order to illustrate technical solutions according to the invention, illustrated below by specific embodiment.
Embodiment one
Fig. 1 shows the structural schematic diagram for the pulse per second (PPS) stable measurement device that first embodiment of the invention provides, in order to
Convenient for explanation, only the parts related to this embodiment are shown, and details are as follows：
The pulse per second (PPS) stable measurement device includes GPS (GlobalPositioningSystem, global positioning system)
Receiver 1, combining unit tester 2, first timer 3, second timer 4, digital signal processor 5, asynchronous memory interface 6
With display 7；
The output end of the GPS receiver 1 is connect with the first input end of the first timer 3, the combining unit
The output end of tester 2 is connect with the first input end of the second timer 4, the input terminal of the digital signal processor 5
After being connect respectively with the output end of the output end of the first timer 3 and the second timer 4, the Digital Signal Processing
The output end of device 5 is connect with the input terminal of the asynchronous memory interface 6, and the output end of the asynchronous memory interface 6 is shown with described
Show the input terminal connection of device 7；
The GPS receiver 1 sends the first pps pulse per second signal to the first timer 3；The combining unit tester 2
The second pps pulse per second signal is sent to the second timer 4；
The first timer 3 is counted and is latched and exported to first pps pulse per second signal；
The second timer 4 is counted and is latched and exported to second pps pulse per second signal；
First pps pulse per second signal that the digital signal processor 5 is exported according to the first timer 3 and described
Second pps pulse per second signal that second timer 4 exports, calculates the pulse per second (PPS) stability of the combining unit tester 2, and
The pulse per second (PPS) stability is sent to the display 7 by the asynchronous memory interface 6 to show.
Wherein, the pps pulse per second signal that the first timer 3 exports the GPS receiver 1 is counted and is latched；Institute
The pps pulse per second signal that second timer 4 exports the combining unit tester 2 is stated to be counted and latched.
In practical applications, after the first timer 3 and second timer 4 are counted and latched, at digital signal
It manages device 5 period of first timer 3 and second timer 4 detect for a long time and using suitable algorithm (follow-up
Embodiment in decompose in detail), the prolonged pulse per second (PPS) stability according to GPS and accuracy calculate combining unit tester
The pulse per second (PPS) stability of the pps pulse per second signal of 2 output, what digital signal processor 5 calculated, combining unit tester 2
The pulse per second (PPS) stability of the pps pulse per second signal of output, is sent to by asynchronous memory interface 6 on display 7.It is preferred that
GPS receiver 1 is using the GPS receiver module of model NEO-M8, and accuracy each second is better than 30 nanoseconds.
In the above-described embodiments, provide a kind of pulse per second (PPS) stable measurement device, by timer count triggering and
The asynchronization of triggering and the periodic characteristics of pps pulse per second signal are reset, are established in conjunction with the long-time stability of GPS and accuracy
Time of measuring benchmark, to realize the high-resolution to the pulse per second (PPS) stability of combining unit tester, high accuracy measures.
The pulse per second (PPS) stable measurement device provided through the invention, can effectively reduce measurement procedure and time of measuring, to reduce
To the measurement cost of the pulse per second (PPS) stability of combining unit tester.
Embodiment two
Fig. 2 shows another structural schematic diagrams of pulse per second (PPS) stable measurement device.The pulse per second (PPS) stable measurement dress
It can also includes crystal 8 to set, as shown in Fig. 2, the second input terminal of the output end of the crystal 8 and the first timer 3 and
Second input terminal of the second timer 4 connects；
The crystal 8, which generates base frequency signal and synchronizes the base frequency signal, is sent to the first timer
3 and the second timer 4.
Optionally, the pulse per second (PPS) stable measurement device can also include frequency multiplier circuit 9, as shown in figure 3, being pulse per second (PPS)
The another structural schematic diagram of stable measurement device, the input terminal of the frequency multiplier circuit 9 are connect with the output end of the crystal 8,
Second input of the output end of the frequency multiplier circuit 9 and the second input terminal and the second timer 4 of the first timer 3
End connection；
The base frequency signal that crystal 8 described in 9 frequency multiplication of the frequency multiplier circuit generates, and by the base frequency after the frequency multiplication
Signal, which synchronizes, is sent to the first timer 3 and the second timer 4.
In practical applications, crystal 8 exports 25 megahertzs of base frequency signal to frequency multiplier circuit 9, frequency multiplier circuit 9 25
Megahertz clock signal frequency multiplication to 125 megahertzs of synchronism outputs to first timer 3 and second timer 4 as base when counting
Input.125 megahertzs of the when base that first timer 3 is exported according to frequency multiplier circuit 9, the pulse per second (PPS) to the output of GPS receiver 1
The period of signal is counted and is latched；125 megahertzs of the when base that second timer 4 is exported according to frequency multiplier circuit 9, to being closed
And the period of the pps pulse per second signal of the output of unit tester 2 is counted and is latched.
Fig. 4 shows the structural schematic diagram of frequency multiplier circuit 9 in Fig. 3, as shown, the frequency multiplier circuit 9 reflects including phase
Phase device 91, loop filter 92, voltage controlled oscillator 93, frequency divider 94 and Clock dividers 95.
The phase phase discriminator 91, loop filter 92, voltage controlled oscillator 93 and Clock dividers 95 are sequentially connected, described
The output end of voltage controlled oscillator 93 is connect by the frequency divider 94 with the input terminal of the voltage controlled oscillator 93；The phase mirror
Phase device 91 measures the phase of the output frequency and the base frequency signal of the frequency divider 94；The voltage controlled oscillator 93 it is defeated
It is directly proportional to the output voltage of the loop filter 92 to go out frequency；When the frequency that the voltage controlled oscillator 93 exports is the crystalline substance
When the frequency dividing multiple of body 8 and frequency divider 94, the output frequency of the Clock dividers 95 is the output of the voltage controlled oscillator 93
The half of frequency.
Specifically, phase phase discriminator 91 is used to measure the output phase of the output frequency and crystal 8 of frequency divider 94, when there is phase
When potential difference, output voltage passes through loop filter 92, and output frequency and the output voltage for controlling voltage controlled oscillator 91 are directly proportional
Frequency signal, and it is input to the input terminal of frequency divider 94, when the frequency and phase of the output of voltage controlled oscillator 91 are just crystal 8
When with the frequency dividing multiple of frequency divider 94, this clock phase-locked loop is stablized, and the frequency dividing multiplying power of frequency divider 94 is 10, so voltage controlled oscillation
The output frequency of device 91 is 10 times of the output frequency of crystal 8, and Clock dividers 95 are exactly a frequency dividing circuit, take frequency division coefficient
It is 2, so output frequency is the 1/2 of the output frequency of voltage controlled oscillator 93.
Optionally, the pulse per second (PPS) stable measurement device further includes digital signal processing chip, the frequency multiplier circuit 9,
First timer 3, second timer 4 and the digital signal processor 5 and the asynchronous memory interface 6 are integrated in digital letter
In number processing chip.
It is understood that the frequency multiplier circuit 9, first timer 3, second timer 4 and the digital signal
Processor 5 and the asynchronous memory interface 6 can be integrated in the external electrical on circuit board as digital signal processing chip
Road can also be the function module being integrated on digital signal processing chip.
It is preferred that the processing chip of the digital signal processing chip selection model ADSP-BF533.
In the above-described embodiments, a kind of pulse per second (PPS) stable measurement device is provided, base frequency letter is generated by crystal
Number, by frequency multiplier circuit by above-mentioned base frequency signal frequency multiplication, using the base frequency signal after frequency multiplication as first timer and
Second, which determines base when the counting of device, synchronizes input, ensures the measurement basic synchronization to GPS receiver and combining unit tester, simultaneously
The good periodicity that ensure that the pps pulse per second signal in first timer and second timer is to promote pulse per second (PPS) stability
The resolution ratio of measurement and the precondition of accuracy.
Embodiment three
Realization for the more detailed description present invention and operation principle, Fig. 5 show that third embodiment of the invention carries
The first timer of confession or the structural schematic diagram of second timer, as shown in figure 5, being determined by taking the first timer 3 as an example
When device structural schematic diagram：
The first timer 3 includes falling edge detectors 31, counter 32 and period register 33；The rising edge inspection
The output end for surveying device 31 is connect with the first input end of the input terminal of the counter 32 and the period register 33, the meter
The output end of number device 32 is connect with the second input terminal of the period register 33.
In a particular application, the falling edge detectors 31 are used for：
When detecting the base frequency signal output rising edge, pulse triggering signal is generated；
When detecting the pulse triggering signal output rising edge and second pps pulse per second signal be not detected, the meter
Number device 34 is counted, and count results are latching to the period register 33；
When detecting the pulse triggering signal output rising edge and detecting second pps pulse per second signal, the counting
Device 34, which counts, to reset.
During above-mentioned first timer 3 or second timer 4 are counted and latched, pass through falling edge detectors
31 ensure that the accumulated value of counter 34 only with the pps pulse per second signal in GPS transceiver 1, i.e. the first pps pulse per second signal is synchronous
, thus by the measurement in two pps pulse per second signal periods, relative to the pps pulse per second signal in GPS transceiver 1 more than the period
Number part remains.Resolution ratio and the accuracy of clock measurement can be constantly promoted by repeatedly measuring.
It is understood that the first timer 3 and the second timer 4 have similar structure and function.
The detailed process of counter counting is illustrated below, to illustrate the counting machine of above-mentioned first timing or second timer
System can constantly promote the resolution ratio and accuracy that clock measures by repeatedly measuring.
Assuming that the time base period SCLK in timer is Ts；
1, at the time of the pps pulse per second signal of first time GPS reaches；
Counter counts count to N, N SCLKn+N-SCLKn, and cycle T 1 is that N × Ts is sent to the preservation of period register 33, simultaneously
Counter 34 is reset.
2, at the time of the pps pulse per second signal of second of GPS reaches；
Counter counts count to N, N SCLKn+2N-SCLKn+N, and cycle T 2 is that N × Ts is sent to the preservation of period register 33,
Counter 34 is reset simultaneously.
3, at the time of the pps pulse per second signal of third time GPS reaches；
Counter counts count to N-1, N SCLKn+3N-1-SCLKn+2N, and cycle T 3 is that (N-1) × Ts is sent to period deposit
Device 33 preserves, while counter 34 is reset.
Its average period is measured by 3 times, formula is：
(T1+T2+T3)/3=(N × Ts+N × Ts+ (N-1) × Ts)/3=(3N-1)/3 × Ts=NTs-1/3Ts
After over-sampling three times, resolution ratio is increased to 1/3Ts by Ts.
It should be noted that base is the digit in timer, the i.e. base unit of time showing when described；When described
Shown digit in a primitive period phase i.e. cycle time.
The pps pulse per second signal refers to the pulse signal that pulsing device was generated every one second, and GPS receiver
The pps pulse per second signal that machine generates has the advantages that long-term high accuracy, long-term although GPS has the error of 30 nanoseconds each second
Error also there was only for 30 nanoseconds, be the basic condition that resolution ratio and accuracy are improved as benchmark and multiple repairing weld.And pass through
Using GPS receiver, long-range or local self calibration may be implemented in combining unit tester, eliminates a combining unit tester and send
It calibrates primary trouble every year to gauge check mechanism, saves verification cost and time of measuring.
In the above-described embodiments, provide a kind of pulse per second (PPS) stable measurement device, by timer count triggering and
The asynchronization of triggering and the periodic characteristics of pps pulse per second signal are reset, the resolution of time measurement is improved by multiple repairing weld
Rate establishes testing time benchmark in conjunction with the long-time stability of GPS and accuracy, to realize the second to combining unit tester
High-resolution, the high accuracy of pulse stabilization degree measure.The pulse per second (PPS) stable measurement device provided through the invention, can subtract
Few measurement procedure and time of measuring, to reduce the measurement cost to the pulse per second (PPS) stability of combining unit tester.
Example IV
Fig. 6 is the calculation process schematic diagram for the pulse per second (PPS) stability that fourth embodiment of the invention provides, and is applied to pulse per second (PPS)
The structure of stable measurement device, pulse per second (PPS) stable measurement device is identical with above-described embodiment one, is not repeating.This
Embodiment is to embody the algorithm or signal processing in digital signal processor 5, i.e., according to the first timer 3 and institute
The process that the pps pulse per second signal in second timer 4 calculates the pulse per second (PPS) stability of the combining unit tester 2 is stated, can be wrapped
It includes：
Step S601：The first timer in preset time is obtained to be counted after receiving first pps pulse per second signal
The first count value；
Step S602：It is synchronous to obtain in the preset time after the second timer reception second pps pulse per second signal
The second count value counted；
Step S603：The resolution of the combining unit tester is calculated according to first count value and the second count value
Rate；
In above-mentioned steps S603, the specific calculation process of the resolution ratio of combining unit tester is as shown in Figure 7：
Step S701：According to first count value, the time base period of first pps pulse per second signal is calculated, formula is：
The first count value sum total ∑ TGn in time base period Ts=preset time S1/ preset times；
Step S702：It according to the time base period Ts, calculates and obtains the time that second count value uses, formula is：
Second count value sum total ∑ TMn × time base period Ts in time S2=preset time；
Step S703：According to the first timer or the when base nominal frequency fs of the second timer, described in calculating
The resolution ratio P of first timer or second timer, formula are：
Resolution ratio P=1/ (when base nominal frequency fs × preset time S1).
Step S604：When the resolution ratio reaches preset standard, n times obtain second timing in the preset time
Second count value of device records N the second count values of group；Wherein N is the integer more than 1；
Step S605：The pulse per second (PPS) stability of the combining unit tester is calculated according to second count value of N groups.
In above-mentioned steps S605, the specific calculation process of the pulse per second (PPS) stability of combining unit tester is as shown in Figure 8：
Step S801：The correct time Sa_n of every group of second count value in second count value of N groups is calculated, formula is：
(the second count value sum total ∑ TMn × the first count values of preset time S1/ sum total ∑ TGn- of N groups is pre- by Sa_n=
If time S1)/preset time S1；
Step S802：According to the correct time Sa_n, the basic pulse per second (PPS) for calculating the combining unit tester is stablized
E is spent, formula is：
Basic pulse per second (PPS) stability e=| the correct time Sa_ (n) of the-the N groups of correct time Sa_ (n-1) of N-1 groups |；
Step S803：The greatest measure in the basic pulse per second (PPS) stability e is obtained, as the combining unit tester
Pulse per second (PPS) stability D.
In order to make it easy to understand, being illustrated below in practical application, the measurement of pulse per second (PPS) stability and calculating process.On assuming that
The preset time stated is 10 minutes, i.e., 600 seconds.
1, the resolution ratio of the combining unit tester is calculated；
It measures in GPS receiver preset time, i.e. S1=10 minutes (600 seconds), the count value of first timer is (TGn+
1+...+TGn+600)
Then S1=(TGn+1+...+TGn+600) × Ts
So Ts=S1/ (TGn+1+...+TGn+S1)
Wherein, TGn represents the pulse per second (PPS) time cycle of the n-th GPS receiver measured；Ts represents GPS receiver output
Pps pulse per second signal time base period.
Within the synchro measure time, the time S2 that second count value uses is obtained, i.e. combining unit tester is default
The time of 600 pulse per second (PPS)s caused by time S1：
S2=(TMn+1+...+TMn+600) × Ts；
It brings the formula for calculating Ts into above-mentioned formula, obtains：
S2=(TMn+1+...+TMn+600) × 600/ (TGn+1+...+TGn+600)；
Since the when base nominal frequency fs of the first timing or second timer is 125 megahertzs, nominal period is received for 8
Second, crystal accuracy is hundred a ten thousandths, so in first timer count value, TGn+1+...+TGn+600 is ranging from：
125000000 × 600 × (1-0.000001)~125000000 × 600 × (1+0.000001)；
1/ (125000000 × 600)=1.3 × 10 its resolution ratio P ≈-11；
Since the accuracy that combining unit tester exports pulse per second (PPS) is 1 microsecond namely hundred a ten thousandths, so timing
The accuracy of the output pulse per second (PPS) of the crystal of the ranging from Ts of device count value TMn+1+...+TMn+600+combining unit tester
Each second is：
125000000 × 600 × (1-0.000002)~125000000 × 600 × (1+0.000002), resolution ratio is about
For 1/ (125000000 × 600)=1.3 × 10-11。
In summary it analyzes, the overall accuracy and resolution ratio of calibrating installation are up to 1.3 × 10-11+1.3×10-11=2.6
×10-11, meet design requirement, therefore n times obtain the second count value of the second timer in the preset time, record N
The second count value of group；Wherein N is the integer more than 1.
In the measurement scheme proposed in the present embodiment, sets 3 times and obtain the second timer in the preset time
The second count value, continue calculate combining unit tester pulse per second (PPS) stability.
2, the pulse per second (PPS) stability of combining unit tester is calculated.
The correct time Sa_1 of combining unit tester is in first group of 10 minute time interval：
The correct time Sa_2 of combining unit tester is in second group of 10 minute time interval：
Combining unit tester correct time Sa_3 is in 10 minute time interval of third group：
Basic pulse per second (PPS) stability e is calculated according to above-mentioned correct time：
First basic pulse per second (PPS) stability e1=| Sa_1-Sa_2 |
Second basic pulse per second (PPS) stability e2=| Sa_2-Sa_3 |
It is 10 minutes pulse per second (PPS) stability value D of combining unit tester to take the middle maximum value of e1 and e2.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each process
Execution sequence should be determined by its function and internal logic, the implementation process without coping with the embodiment of the present invention constitutes any limit
It is fixed.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, is not described in detail or remembers in some embodiment
The part of load may refer to the associated description of other embodiments.
It is understood that for convenience of description and succinctly, only being lifted with the division of above-mentioned each functional unit, module
Example illustrates, in practical application, can be completed, i.e., will by different functional units, module as needed and by above-mentioned function distribution
The internal structure of described device is divided into different functional units or module, to complete all or part of work(described above
Energy.Each functional unit, module in embodiment can be integrated in a processing unit, can also be the independent physics of each unit
In the presence of, it can also be during two or more units be integrated in one unit, hardware both may be used in above-mentioned integrated unit
Form is realized, can also be realized in the form of SFU software functional unit.In addition, the specific name of each functional unit, module also only
It is the protection domain that is not intended to limit this application for the ease of mutually distinguishing.The specific works of unit in above system, module
Process can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
Those of ordinary skill in the art may realize that lists described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, depends on the specific application and design constraint of technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The scope of the present invention.
The unit illustrated as separating component may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple
In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it can also
It is that each unit physically exists alone, it can also be during two or more units be integrated in one unit.Above-mentioned integrated list
The form that hardware had both may be used in member is realized, can also be realized in the form of SFU software functional unit.
If the integrated module/unit be realized in the form of SFU software functional unit and as independent product sale or
In use, can be stored in a computer read/write memory medium.Based on this understanding, the present invention realizes above-mentioned implementation
All or part of flow in example method, can also instruct relevant hardware to complete, the meter by computer program
Calculation machine program can be stored in a computer readable storage medium, the computer program when being executed by processor, it can be achieved that on
The step of stating each embodiment of the method..Wherein, the computer program includes computer program code, the computer program
Code can be source code form, object identification code form, executable file or certain intermediate forms etc..Computer-readable Jie
Matter may include：Can carry the computer program code any entity or device, recording medium, USB flash disk, mobile hard disk,
Magnetic disc, CD, computer storage, read-only memory (ROM, Read-OnlyMemory), random access memory (RAM,
RandomAccessMemory), electric carrier signal, telecommunication signal and software distribution medium etc..It should be noted that the meter
The content that calculation machine readable medium includes can carry out increase and decrease appropriate according to legislation in jurisdiction and the requirement of patent practice,
Such as in certain jurisdictions, according to legislation and patent practice, computer-readable medium does not include electric carrier signal and telecommunications
Signal.
Embodiment described above is merely illustrative of the technical solution of the present invention, rather than its limitations；Although with reference to aforementioned reality
Applying example, invention is explained in detail, it will be understood by those of ordinary skill in the art that：It still can be to aforementioned each
Technical solution recorded in embodiment is modified or equivalent replacement of some of the technical features；And these are changed
Or replace, the spirit and scope for various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution should all
It is included within protection scope of the present invention.
Claims (10)
1. a kind of pulse per second (PPS) stable measurement device, which is characterized in that determine including GPS receiver, combining unit tester, first
When device, second timer, digital signal processor, asynchronous memory interface and display；
The output end of the GPS receiver is connect with the first input end of the first timer, the combining unit tester
Output end connect with the first input end of the second timer, the input terminal of the digital signal processor and described first
The output end of timer is connected with the output end of the second timer, the output end of the digital signal processor with it is described different
The input terminal connection of memory interface is walked, the output end of the asynchronous memory interface is connect with the input terminal of the display；
The GPS receiver sends the first pps pulse per second signal to the first timer；The combining unit tester is to described
Second timer sends the second pps pulse per second signal；
The first timer is counted and is latched and exported to first pps pulse per second signal；
The second timer is counted and is latched and exported to second pps pulse per second signal；
First pps pulse per second signal and described second that the digital signal processor is exported according to the first timer are determined
When device output second pps pulse per second signal, calculate the pulse per second (PPS) stability of the combining unit tester, and by the second
Pulse stabilization degree is sent to the display by the asynchronous memory interface and is shown.
2. pulse per second (PPS) stable measurement device as described in claim 1, which is characterized in that the pulse per second (PPS) stable measurement dress
It further includes crystal to set；
The output end of the crystal and the second input terminal of the first timer and the second input terminal of the second timer
Connection；
The crystal generates base frequency signal, and the base frequency signal is synchronized and is sent to the first timer and institute
State second timer.
3. pulse per second (PPS) stable measurement device as claimed in claim 2, which is characterized in that the pulse per second (PPS) stable measurement dress
It further includes frequency multiplier circuit to set；
The input terminal of the frequency multiplier circuit is connect with the output end of the crystal, the output end of the frequency multiplier circuit and described first
Second input terminal of timer is connected with the second input terminal of the second timer；
The base frequency signal that crystal described in the frequency multiplier circuit frequency multiplication generates, and the base frequency signal after the frequency multiplication is same
Step is sent to the first timer and the second timer.
4. pulse per second (PPS) stable measurement device as claimed in claim 3, which is characterized in that the frequency multiplier circuit includes phase mirror
Phase device, loop filter, voltage controlled oscillator, frequency divider and Clock dividers；
The phase phase discriminator, loop filter, voltage controlled oscillator and Clock dividers are sequentially connected, the voltage controlled oscillator
Output end is connect by the frequency divider with the input terminal of the voltage controlled oscillator；
The phase phase discriminator measures the phase of the output frequency and the base frequency signal of the frequency divider；
The output frequency of the voltage controlled oscillator is directly proportional to the output voltage of the loop filter；
When the frequency of voltage controlled oscillator output is the frequency dividing multiple of the crystal and frequency divider, the Clock dividers
Output frequency is the half of the output frequency of the voltage controlled oscillator.
5. pulse per second (PPS) stable measurement device as described in claim 1, which is characterized in that the first timer or described
Two timers include falling edge detectors, counter and period register；
The first input end of the output end of the falling edge detectors and the input terminal and the period register of the counter
Connection, the output end of the counter are connect with the second input terminal of the period register.
6. pulse per second (PPS) stable measurement device as claimed in claim 5, which is characterized in that the falling edge detectors detect
When the base frequency signal output rising edge, pulse triggering signal is generated；
The falling edge detectors detect the pulse triggering signal output rising edge and the second pulse letter are not detected
Number when, the counter is counted, and count results are latching to the period register；
The falling edge detectors detect the pulse triggering signal output rising edge and detect second pulse signal
When, the counter, which counts, to reset.
7. pulse per second (PPS) stable measurement device as claimed in claim 5, which is characterized in that the pulse per second (PPS) stable measurement dress
It further includes digital signal processing chip to set, the frequency multiplier circuit, first timer, second timer, the Digital Signal Processing
Device and the asynchronous memory interface are integrated on the digital signal processing chip.
8. any one pulse per second (PPS) stable measurement device as described in claim 1 to 7, which is characterized in that according to described first
Second pps pulse per second signal of first pps pulse per second signal and second timer output of timer output, calculates institute
The pulse per second (PPS) stability of combining unit tester is stated, including：
It obtains the first timer in preset time and receives the first count value counted after first pps pulse per second signal；
It is synchronous to obtain the second timer in the preset time and receive the counted after second pps pulse per second signal
Two count values；
The resolution ratio of the combining unit tester is calculated according to first count value and the second count value；
When the resolution ratio reaches preset standard, n times obtain the second counting of the second timer in the preset time
Value records N the second count values of group；Wherein N is the integer more than 1；
The pulse per second (PPS) stability of the combining unit tester is calculated according to second count value of N groups.
9. pulse per second (PPS) stable measurement device as claimed in claim 8, which is characterized in that according to first count value and
Two count values calculate the resolution ratio of the combining unit tester, including：
According to first count value, the time base period of first pps pulse per second signal is calculated, formula is：
The first count value sum total in time base period=preset time/preset time；
It according to the time base period, calculates and obtains the time that second count value uses, formula is：
Second count value sum total × time base period in time=preset time；
According to the when base nominal frequency of the first timer or the second timer, the first timer or second are calculated
The resolution ratio of timer, formula are：
Resolution ratio=1/ (when base nominal frequency × preset time).
10. pulse per second (PPS) stable measurement device as claimed in claim 8, which is characterized in that according to second count value of N groups
The pulse per second (PPS) stability of the combining unit tester is calculated, including：
The correct time of every group of second count value in second count value of N groups is calculated, formula is：
The correct time of N groups=(the second count value sum total of N groups × preset time/the first count value is summed up-is when presetting
Between)/preset time；
According to the correct time, the basic pulse per second (PPS) stability of the combining unit tester is calculated, formula is：
Basic pulse per second (PPS) stability=| the correct time of correct time the-the N groups of N-1 groups |；
The greatest measure in the basic pulse per second (PPS) stability is obtained, the pulse per second (PPS) as the combining unit tester is stablized
Degree.
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