CN108414841B - Pulse per second stability measuring device - Google Patents
Pulse per second stability measuring device Download PDFInfo
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- CN108414841B CN108414841B CN201810194764.7A CN201810194764A CN108414841B CN 108414841 B CN108414841 B CN 108414841B CN 201810194764 A CN201810194764 A CN 201810194764A CN 108414841 B CN108414841 B CN 108414841B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E30/00—Energy generation of nuclear origin
- Y02E30/30—Nuclear fission reactors
Abstract
The invention is suitable for the technical field of electronic instruments and meters, and provides a second pulse stability measuring device which comprises a GPS receiver, a merging unit calibrator, a first timer, a second timer, a digital signal processor, an asynchronous storage interface and a display; the GPS receiver sends a first second pulse signal to a first timer; the merging unit calibrator transmits a second pulse signal to the second timer; the first timer counts and latches the first second pulse signal and outputs the first second pulse signal; the second timer counts and latches the second pulse signal and outputs the second pulse signal; and the digital signal processor calculates the second pulse stability of the merging unit calibrator according to the first second pulse signal and the second pulse signal, and sends the second pulse stability to the display for display through the asynchronous storage interface. The invention can effectively reduce the measuring flow and the measuring time, thereby reducing the measuring cost of the second pulse stability of the merging unit calibrator.
Description
Technical Field
The invention belongs to the technical field of electronic instruments and meters, and particularly relates to a second pulse stability measuring device.
Background
Along with the wide application of the intelligent substation in the process of building the power network in China, the merging units and the intelligent terminals respectively exist as important equipment and contents of constituent structures of the process network in the process of building the intelligent substation, and the merging units are used for synchronously sampling and converting analog quantities of the whole substation into digital quantities under the control of second pulse, so that the internal clock of each merging unit is required to keep certain time keeping precision. The timekeeping precision of the merging unit is finished by a merging unit calibrator, and the accuracy level of the calibration equipment is required to be 2 levels or 1/4 times higher than that of the checked equipment according to the metering rule.
Pulse per second stability measurement for merging-unit proverMeasuring instruments, e.g. 10, requiring higher accuracy -10 A time interval/frequency counter with high level of accuracy. The time interval/frequency counter with high accuracy is high in price and large in equipment, and needs to be calibrated by a professional, so that the measurement cost of the second pulse stability of the merging unit calibrator is high, the flow is complex, and the detection time is long.
Disclosure of Invention
In view of the above, the embodiment of the invention provides a second pulse stability measuring device, which is used for solving the problems of high second pulse stability measuring cost, complex flow and long detection time of a merging unit calibrator in the prior art.
The embodiment of the invention provides a second pulse stability measuring device which comprises a GPS receiver, a merging unit calibrator, a first timer, a second timer, a digital signal processor, an asynchronous storage interface and a display;
the output end of the GPS receiver is connected with the first input end of the first timer, the output end of the merging unit calibrator is connected with the first input end of the second timer, the input end of the digital signal processor is respectively connected with the output end of the first timer and the output end of the second timer, the output end of the digital signal processor is connected with the input end of the asynchronous storage interface, and the output end of the asynchronous storage interface is connected with the input end of the display;
the GPS receiver sends a first second pulse signal to a first timer; the merging unit calibrator transmits a second pulse signal to the second timer;
the first timer counts and latches the first second pulse signal and outputs the first second pulse signal;
the second timer counts and latches a second pulse signal and outputs the second pulse signal;
and the digital signal processor calculates the second pulse stability of the merging unit calibrator according to the first second pulse signal output by the first timer and the second pulse signal output by the second timer, and sends the second pulse stability to the display for display through the asynchronous storage interface.
Optionally, the second pulse stability measuring device further comprises a crystal;
the output end of the crystal is connected with the second input end of the first timer and the second input end of the second timer;
the crystal generates a fundamental frequency signal and synchronously transmits the fundamental frequency signal to the first timer and the second timer.
Optionally, the second pulse stability measuring device further comprises a frequency doubling circuit;
the input end of the frequency doubling circuit is connected with the output end of the crystal, and the output end of the frequency doubling circuit is connected with the second input end of the first timer and the second input end of the second timer;
and the frequency doubling circuit multiplies the basic frequency signal generated by the crystal and synchronously transmits the frequency-doubled basic frequency signal to the first timer and the second timer.
Optionally, the frequency multiplication circuit includes a phase discriminator, a loop filter, a voltage controlled oscillator, a frequency divider and a clock frequency divider;
the phase discriminator, the loop filter, the voltage-controlled oscillator and the clock frequency divider are sequentially connected, and the output end of the voltage-controlled oscillator is connected with the input end of the voltage-controlled oscillator through the frequency divider;
the phase discriminator measures the output frequency of the frequency divider and the phase of the fundamental frequency signal;
the output frequency of the voltage-controlled oscillator is in direct proportion to the output voltage of the loop filter;
when the frequency of the output of the voltage-controlled oscillator is the frequency division multiple of the crystal and the frequency divider, the output frequency of the clock frequency divider is one half of the output frequency of the voltage-controlled oscillator.
Optionally, the first timer or the second timer includes a rising edge detector, a counter, and a period register;
the output end of the rising edge detector is connected with the input end of the counter and the first input end of the period register, and the output end of the counter is connected with the second input end of the period register.
Optionally, when the rising edge detector detects that the basic frequency signal outputs a rising edge, a pulse trigger signal is generated;
when the rising edge detector detects the pulse trigger signal to output rising edge and does not detect the second pulse signal, the counter counts and latches the counting result to the period register;
when the rising edge detector detects the rising edge of the pulse trigger signal output and detects the second pulse signal, the counter counts and clears.
Optionally, the second pulse stability measuring device further comprises a digital signal processing chip, and the frequency doubling circuit, the first timer, the second timer, the digital signal processor and the asynchronous storage interface are integrated on the digital signal processing chip.
Optionally, calculating the second pulse stability of the merging unit calibrator according to the first second pulse signal output by the first timer and the second pulse signal output by the second timer includes:
acquiring a first count value which is counted after a first timer receives a first second pulse signal in preset time;
synchronously acquiring a second count value counted after the second timer receives the second pulse signal in preset time;
calculating the resolution of the merging unit calibrator according to the first count value and the second count value;
when the resolution reaches a preset standard, acquiring second count values of a second timer in preset time for N times, and recording N groups of second count values; wherein N is an integer greater than 1;
and calculating the second pulse stability of the merging unit calibrator according to the N groups of second count values.
Optionally, calculating the resolution of the merging unit calibrator according to the first count value and the second count value includes:
according to the first count value, calculating a time base period of the first second pulse signal, wherein the formula is as follows:
time base period = preset time/first count value aggregate within preset time;
according to the time base period, calculating the time used for obtaining the second count value, wherein the formula is as follows:
time = second count value total x time base period within a preset time;
according to the time base nominal frequency of the first timer or the second timer, calculating the resolution of the first timer or the second timer, wherein the formula is as follows:
resolution=1/(time base nominal frequency x preset time).
Optionally, calculating the second pulse stability of the merging unit calibrator according to the N groups of second count values includes:
calculating the accurate time of each group of second count values in the N groups of second count values, wherein the formula is as follows:
accurate time of the nth group= (second count value total of the nth group x preset time/first count value total-preset time)/preset time;
according to the accurate time, the basic pulse per second stability of the merging unit calibrator is calculated, and the formula is as follows:
basic pulse per second stability= |accurate time of group N-1-accurate time of group n|;
and obtaining the maximum value in the basic pulse per second stability as the pulse per second stability of the merging unit calibrator.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: by means of the non-synchronism of counting trigger and zero clearing trigger in the timer and the periodic characteristic of the second pulse signal, the measurement time reference is established in combination with the long-term stability and accuracy of the GPS, and therefore high-resolution and high-accuracy measurement of the second pulse stability of the merging unit calibrator is achieved. The second pulse stability measuring device provided by the invention can effectively reduce the measuring flow and measuring time, thereby reducing the measuring cost of the second pulse stability of the merging unit calibrator.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a pulse per second stability measurement device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another pulse per second stability measurement device according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a second pulse per second stability measurement device according to a second embodiment of the present invention;
fig. 4 is a schematic diagram of a frequency multiplier circuit according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a first timer or a second timer according to a third embodiment of the present invention;
FIG. 6 is a schematic diagram of a calculation flow of the stability of second pulse according to the fourth embodiment of the present invention;
fig. 7 is a schematic diagram of a specific calculation flow of step S603 in the fourth embodiment of the present invention;
fig. 8 is a schematic diagram of a specific calculation flow of step S605 in the fourth embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to illustrate the technical scheme of the invention, the following description is made by specific examples.
Example 1
Fig. 1 is a schematic structural diagram of a second pulse stability measuring device according to a first embodiment of the present invention, and for convenience of explanation, only the parts related to this embodiment are shown, and the details are as follows:
the second pulse stability measuring device comprises a GPS (global positioning system) receiver 1, a merging unit calibrator 2, a first timer 3, a second timer 4, a digital signal processor 5, an asynchronous storage interface 6 and a display 7;
the output end of the GPS receiver 1 is connected with the first input end of the first timer 3, the output end of the merging unit calibrator 2 is connected with the first input end of the second timer 4, the input end of the digital signal processor 5 is respectively connected with the output end of the first timer 3 and the output end of the second timer 4, after that, the output end of the digital signal processor 5 is connected with the input end of the asynchronous storage interface 6, and the output end of the asynchronous storage interface 6 is connected with the input end of the display 7;
the GPS receiver 1 transmits a first second pulse signal to the first timer 3; the merging unit calibrator 2 sends a second pulse signal to the second timer 4;
the first timer 3 counts and latches the first second pulse signal and outputs the first second pulse signal;
the second timer 4 counts and latches the second pulse signal and outputs the second pulse signal;
the digital signal processor 5 calculates the second pulse stability of the merging unit checking instrument 2 according to the first second pulse signal output by the first timer 3 and the second pulse signal output by the second timer 4, and sends the second pulse stability to the display 7 for displaying through the asynchronous storage interface 6.
Wherein the first timer 3 counts and latches a second pulse signal output by the GPS receiver 1; the second timer 4 counts and latches the second pulse signal output by the merging unit calibrator 2.
In practical applications, after the first timer 3 and the second timer 4 count and latch, the digital signal processor 5 detects the periods of the first timer 3 and the second timer 4 for a long time and calculates the second pulse stability of the second pulse signal output by the merging unit calibration apparatus 2 according to the long-time second pulse stability and accuracy of the GPS by adopting a suitable algorithm (detailed decomposition in the following embodiments), and the digital signal processor 5 sends the calculated second pulse stability of the second pulse signal output by the merging unit calibration apparatus 2 to the display 7 through the asynchronous memory interface 6. Preferably, the GPS receiver 1 uses a GPS receiving module of model NEO-M8 with an accuracy of better than 30 nanoseconds per second.
In the above embodiment, a pulse per second stability measuring device is provided, and by means of the non-synchronism of counting trigger and zero clearing trigger in a timer and the periodic characteristic of a pulse per second signal, a measurement time reference is established in combination with the long-term stability and accuracy of a GPS, so that high-resolution and high-accuracy measurement of the pulse per second stability of a combined unit calibrator is realized. The second pulse stability measuring device provided by the invention can effectively reduce the measuring flow and measuring time, thereby reducing the measuring cost of the second pulse stability of the merging unit calibrator.
Example two
Fig. 2 shows another schematic structure of the pulse per second stability measuring device. The second pulse stability measuring device may further include a crystal 8, as shown in fig. 2, where an output end of the crystal 8 is connected to the second input end of the first timer 3 and the second input end of the second timer 4;
the crystal 8 generates a fundamental frequency signal and synchronously transmits the fundamental frequency signal to the first timer 3 and the second timer 4.
Optionally, the pulse per second stability measuring device may further include a frequency doubling circuit 9, as shown in fig. 3, which is a schematic structural diagram of the pulse per second stability measuring device, where an input end of the frequency doubling circuit 9 is connected to an output end of the crystal 8, and an output end of the frequency doubling circuit 9 is connected to a second input end of the first timer 3 and a second input end of the second timer 4;
the frequency doubling circuit 9 multiplies the fundamental frequency signal generated by the crystal 8, and synchronously transmits the multiplied fundamental frequency signal to the first timer 3 and the second timer 4.
In practical applications, the crystal 8 outputs a 25 mhz fundamental frequency signal to the frequency doubling circuit 9, and the frequency doubling circuit 9 multiplies the 25 mhz clock signal to 125 mhz and synchronously outputs the signals to the first timer 3 and the second timer 4 as count time base inputs. The first timer 3 counts and latches the period of the second pulse signal output from the GPS receiver 1 according to the 125 mhz time base output from the frequency multiplier circuit 9; the second timer 4 counts and latches the period of the second pulse signal outputted from the unit check meter 2 to be combined based on the 125 mhz time base outputted from the frequency multiplier 9.
Fig. 4 shows a schematic diagram of the frequency doubling circuit 9 in fig. 3, and as shown, the frequency doubling circuit 9 includes a phase detector 91, a loop filter 92, a voltage controlled oscillator 93, a frequency divider 94 and a clock divider 95.
The phase discriminator 91, the loop filter 92, the voltage-controlled oscillator 93 and the clock divider 95 are sequentially connected, and the output end of the voltage-controlled oscillator 93 is connected with the input end of the voltage-controlled oscillator 93 through the divider 94; the phase discriminator 91 measures the output frequency of the frequency divider 94 and the phase of the fundamental frequency signal; the output frequency of the voltage-controlled oscillator 93 is proportional to the output voltage of the loop filter 92; when the frequency of the output of the voltage-controlled oscillator 93 is a division multiple of the crystal 8 and the frequency divider 94, the output frequency of the clock divider 95 is one half of the output frequency of the voltage-controlled oscillator 93.
Specifically, the phase discriminator 91 is configured to measure the output frequency of the frequency divider 94 and the output phase of the crystal 8, when there is a phase difference, the output voltage passes through the loop filter 92, and controls the output frequency of the voltage-controlled oscillator 91 to be a frequency signal proportional to the output voltage, and the frequency signal is input to the input end of the frequency divider 94, when the output frequency and the phase of the voltage-controlled oscillator 91 are just the frequency division multiples of the crystal 8 and the frequency divider 94, the clock phase-locked loop is stable, the frequency division multiple of the frequency divider 94 is 10, so the output frequency of the voltage-controlled oscillator 91 is 10 times the output frequency of the crystal 8, the clock frequency divider 95 is a frequency division circuit, the frequency division coefficient is 2, and the output frequency is 1/2 of the output frequency of the voltage-controlled oscillator 93.
Optionally, the second pulse stability measuring device further comprises a digital signal processing chip, and the frequency doubling circuit 9, the first timer 3, the second timer 4, the digital signal processor 5 and the asynchronous memory interface 6 are integrated on the digital signal processing chip.
It is understood that the frequency doubling circuit 9, the first timer 3, the second timer 4, the digital signal processor 5 and the asynchronous memory interface 6 may be external circuits integrated on a circuit board as a digital signal processing chip or may be functional modules integrated on a digital signal processing chip.
Preferably, the digital signal processing chip selects a processing chip with the model number ADSP-BF 533.
In the above embodiment, a second pulse stability measurement device is provided, a base frequency signal is generated through a crystal, the base frequency signal is multiplied by a frequency multiplication circuit, the multiplied base frequency signal is used as a counting time base synchronization input of a first timer and a second timer, the measurement of a GPS receiver and a merging unit calibrator is ensured to be basically synchronous, meanwhile, good periodicity of second pulse signals in the first timer and the second timer is ensured, and the second pulse stability measurement device is a precondition for improving resolution and accuracy of second pulse stability measurement.
Example III
For describing the implementation and working principle of the present invention in more detail, fig. 5 shows a schematic structural diagram of a first timer or a second timer according to a third embodiment of the present invention, and as shown in fig. 5, the schematic structural diagram of the first timer 3 is taken as an example.
The first timer 3 includes a rising edge detector 31, a counter 32, and a period register 33; the output of the rising edge detector 31 is connected to the input of the counter 32 and to the first input of the period register 33, and the output of the counter 32 is connected to the second input of the period register 33.
In a specific application, the rising edge detector 31 is configured to:
when the rising edge of the output of the basic frequency signal is detected, a pulse trigger signal is generated;
when the pulse trigger signal output rising edge is detected and the second pulse signal is not detected, the counter 34 counts and latches the count result to the period register 33;
the counter 34 counts zero when the pulse trigger signal output rising edge is detected and the second pulse signal is detected.
In the process of counting and latching by the first timer 3 or the second timer 4 described above, it is ensured by the rising edge detector 31 that the accumulated value of the counter 34 is synchronized only with the second pulse signal in the GPS transceiver 1, i.e., the first second pulse signal, so that the remainder of the period of the second pulse signal with respect to the period of the second pulse signal in the GPS transceiver 1 is retained in the measurement of the period of the two second pulse signals. The resolution and accuracy of clock measurement can be continuously improved through multiple measurements.
It will be appreciated that the first timer 3 and the second timer 4 have similar structures and functions.
The following shows a specific process of counting by the counter to illustrate the counting mechanism of the first timer or the second timer, and the resolution and accuracy of the clock measurement can be continuously improved through multiple measurements.
Assuming that a time base period SCLK in the timer is Ts;
1. the moment when the second pulse signal of the first GPS arrives;
the counter counts to N, where N is SCLKn+N-SCLKn, and the period T1 is N×Ts, and is sent to the period register 33 for storage, and the counter 34 is cleared.
2. The time when the second pulse signal of the second GPS arrives;
the counter counts to N, where N is SCLKn+2N-SCLKn+N, and the period T2 is N×Ts, and is sent to the period register 33 for storage, and the counter 34 is cleared.
3. The time when the second pulse signal of the third GPS arrives;
the counter counts to N-1, N is SCLKn+3N-1-SCLKn+2N, the period T3 is (N-1) x Ts and is sent to the period register 33 for storage, and the counter 34 is cleared.
The average period is measured for 3 times, and the formula is as follows:
(T1+T2+T3)/3＝(N×Ts+N×Ts+(N-1)×Ts)/3＝(3N-1)/3×Ts＝NTs-1/3Ts
after three oversampling, the resolution is increased from Ts to 1/3Ts.
The time base is a counting unit in the timer, namely a basic unit for instant display; the time base period is the unit of count displayed during a period of time.
The second pulse signal refers to a pulse signal generated by pulse generating equipment every second, and the second pulse signal generated by a GPS receiver has the advantage of long-term high accuracy, and although the GPS has an error of 30 nanoseconds per second, the long-term error is only 30 nanoseconds, so that the second pulse signal is taken as a basic condition for improving the resolution and accuracy by taking the reference and multiple sampling. And by using the GPS receiver, the merging unit calibrator can realize remote or local self calibration, so that the trouble of sending the merging unit calibrator to a metering detection mechanism for calibration once per year is saved, and the calibration cost and the measurement time are saved.
In the above embodiment, a pulse per second stability measuring device is provided, and the resolution of time measurement is improved by sampling multiple times through the asynchronism of counting triggering and zero clearing triggering in a timer and the periodicity characteristic of a pulse per second signal, and a test time reference is established by combining the long-term stability and accuracy of a GPS, so that the high-resolution and high-accuracy measurement of the pulse per second stability of a combined unit calibrator is realized. The second pulse stability measuring device provided by the invention can reduce the measuring flow and measuring time, thereby reducing the measuring cost of the second pulse stability of the merging unit calibrator.
Example IV
Fig. 6 is a schematic diagram of a calculation flow of the stability of the second pulse according to the fourth embodiment of the present invention, which is applied to the stability measuring device of the second pulse, and the structure of the stability measuring device of the second pulse is identical to that of the first embodiment, and is not repeated. The algorithm or the signal processing procedure in the digital signal processor 5, that is, the procedure of calculating the second pulse stability of the merging unit calibration apparatus 2 according to the second pulse signals in the first timer 3 and the second timer 4, may include:
step S601: acquiring a first count value which is counted after the first timer receives the first second pulse signal in preset time;
step S602: synchronously acquiring a second count value which is counted after the second timer receives the second pulse signal in the preset time;
step S603: calculating the resolution of the merging unit calibrator according to the first count value and the second count value;
in the above step S603, a specific calculation flow of the resolution of the merging unit check meter is shown in fig. 7:
step S701: according to the first count value, calculating a time base period of the first second pulse signal, wherein the formula is as follows:
time base period ts=preset time S1/first count value sum Σtgn within the preset time;
step S702: according to the time base period Ts, calculating the time used for obtaining the second count value, wherein the formula is as follows:
time s2=second count value sum Σtmn×time base period Ts in a preset time;
step S703: according to the time base nominal frequency fs of the first timer or the second timer, calculating the resolution P of the first timer or the second timer, wherein the formula is as follows:
resolution p=1/(time base nominal frequency fs×preset time S1).
Step S604: when the resolution reaches a preset standard, acquiring second count values of the second timer in the preset time for N times, and recording N groups of second count values; wherein N is an integer greater than 1;
step S605: and calculating the second pulse stability of the merging unit calibrator according to the N groups of second count values.
In the above step S605, a specific calculation flow of the second pulse stability of the merging unit check meter is shown in fig. 8:
step S801: calculating the accurate time Sa_n of each group of second count values in the N groups of second count values, wherein the formula is as follows:
sa_n= (second count value total Σtmn of nth group×preset time S1/first count value total Σtgn-preset time S1)/preset time S1;
step S802: and calculating the basic second pulse stability e of the merging unit calibrator according to the accurate time Sa_n, wherein the formula is as follows:
basic pulse per second stability e= |accurate time sa_ (N-1) of N-1 th group-accurate time sa_ (N) | of N-th group;
step S803: and obtaining the maximum value in the basic pulse per second stability e as the pulse per second stability D of the merging unit calibrator.
For ease of understanding, the following shows the process of measuring and calculating the stability of the second pulse in practical applications. The above-mentioned preset time is assumed to be 10 minutes, i.e., 600 seconds.
1. Calculating the resolution ratio of the merging unit calibrator;
the GPS receiver is measured for a predetermined time, i.e., s1=10 minutes (600 seconds), and the count value of the first timer is (tgn+1+.+ tgn+600)
S1= (tgn+1+, +tgn+600) ×ts
So ts=s1/(tgn+1+) +tgn+s1
Wherein TGn represents the measured time period of the second pulse of the nth GPS receiver; ts represents the time base period of the second pulse signal output by the GPS receiver.
In the synchronous measurement time, the time S2 used by the second count value is obtained, namely, the time of 600 second pulses generated in the preset time S1 of the merging unit calibrator:
S2＝(TMn+1+...+TMn+600)×Ts；
the formula for calculating Ts is introduced into the formula, and the following is obtained:
S2＝(TMn+1+...+TMn+600)×600/(TGn+1+...+TGn+600)；
since the time base nominal frequency fs of the first or second timer is 125 megahertz, its nominal period is 8 nanoseconds, and the crystal accuracy is one part per million, the range of tgn+1+ & gttgn+600 in the first timer count value is:
125000000×600×(1-0.000001)～125000000×600×(1+0.000001)；
its resolution p≡1/(125000000 ×600) =1.3×10 -11 ；
Since the accuracy of the merging-unit checker output second pulse is 1 microsecond, that is, one part per million, the accuracy of the crystal in the range of Ts of timer count value tmn+1+.+ tmn+600+merging-unit checker output second pulse per second is:
125000000 ×600× (1-0.000002) to 125000000 ×600× (1+0.000002) with a resolution of about 1/(125000000 ×600) =1.3×10 -11 。
By combining the analysis, the whole accuracy and resolution of the calibrating device can reach 1.3 multiplied by 10 -11 +1.3×10 -11 ＝2.6×10 -11 The design requirement is met, so that the second count value of the second timer in the preset time is obtained for N times, and N groups of second count values are recorded; wherein N is an integer greater than 1.
In the measurement scheme provided in this embodiment, the second count value of the second timer is set to be obtained 3 times within the preset time, and the second pulse stability of the merging unit calibrator is continuously calculated.
2. And calculating the second pulse stability of the merging unit calibrator.
The accurate time sa_1 of the merging-unit calibrator in the first set of 10-minute time intervals is:
the accurate time Sa_2 of the merging-unit calibrator in the second set of 10-minute time intervals is:
the accurate time Sa_3 of the merging unit calibrator in the third group of 10-minute time intervals is as follows:
and calculating the stability e of the basic second pulse according to the accurate time:
first base pulse per second stability e1= |sa_1-sa_2|
Second base pulse per second stability e2= |sa_2-sa_3|
Taking the middle maximum value of e1 and e2 as the pulse stability value D of the merging unit calibrator for 10 minutes and seconds.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
It should be understood that, for convenience and brevity, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described function allocation may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules, so as to perform all or part of the functions described above. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. . Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer memory, a Read-only memory (ROM), a random access memory (RAM, randomAccessMemory), an electrical carrier signal, a telecommunication signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (5)
1. The second pulse stability measuring device is characterized by comprising a GPS receiver, a merging unit calibrator, a first timer, a second timer, a digital signal processor, an asynchronous storage interface and a display;
the output end of the GPS receiver is connected with the first input end of the first timer, the output end of the merging unit calibrator is connected with the first input end of the second timer, the input end of the digital signal processor is connected with the output end of the first timer and the output end of the second timer, the output end of the digital signal processor is connected with the input end of the asynchronous storage interface, and the output end of the asynchronous storage interface is connected with the input end of the display;
the GPS receiver sends a first second pulse signal to the first timer; the merging unit calibrator transmits a second pulse signal to the second timer;
the first timer counts and latches the first second pulse signal output by the GPS receiver and outputs the first second pulse signal;
the second timer counts and latches the second pulse signal output by the merging unit calibrator and outputs the second pulse signal;
the digital signal processor calculates the second pulse stability of the merging unit calibrator according to the first second pulse signal output by the first timer and the second pulse signal output by the second timer, and sends the second pulse stability to the display for display through the asynchronous storage interface;
the calculating the second pulse stability of the merging unit calibrator according to the first second pulse signal output by the first timer and the second pulse signal output by the second timer includes:
acquiring a first count value which is counted after the first timer receives the first second pulse signal in preset time;
synchronously acquiring a second count value which is counted after the second timer receives the second pulse signal in the preset time;
calculating the resolution of the merging unit calibrator according to the first count value and the second count value;
when the resolution reaches a preset standard, acquiring second count values of the second timer in the preset time for N times, and recording N groups of second count values; wherein N is an integer greater than 1;
calculating the second pulse stability of the merging unit calibrator according to the N groups of second count values;
the calculating the resolution of the merging unit calibrator according to the first count value and the second count value includes:
according to the first count value, calculating a time base period of the first second pulse signal, wherein the formula is as follows:
time base period = preset time/first count value aggregate within preset time;
according to the time base period, calculating the time used for obtaining the second count value, wherein the formula is as follows:
time = second count value total x time base period within a preset time;
calculating the resolution of the first timer or the second timer according to the time base nominal frequency of the first timer or the second timer, wherein the formula is as follows:
resolution=1/(time base nominal frequency x preset time);
and calculating the second pulse stability of the merging unit calibrator according to the N groups of second count values, wherein the second pulse stability comprises the following steps:
calculating the accurate time of each group of second count values in the N groups of second count values, wherein the formula is as follows:
accurate time of the nth group= (second count value total of the nth group x preset time/first count value total-preset time)/preset time;
and calculating the basic pulse per second stability of the merging unit calibrator according to the accurate time, wherein the formula is as follows:
basic pulse per second stability= |accurate time of group N-1-accurate time of group n|;
obtaining the maximum value in the basic pulse per second stability as the pulse per second stability of the merging unit calibrator;
the second pulse stability measuring device further comprises a crystal;
the output end of the crystal is connected with the second input end of the first timer and the second input end of the second timer;
the crystal generates a basic frequency signal and synchronously transmits the basic frequency signal to the first timer and the second timer;
the second pulse stability measuring device further comprises a frequency doubling circuit;
the input end of the frequency doubling circuit is connected with the output end of the crystal, and the output end of the frequency doubling circuit is connected with the second input end of the first timer and the second input end of the second timer;
and the frequency multiplication circuit multiplies the basic frequency signal generated by the crystal and synchronously transmits the multiplied basic frequency signal to the first timer and the second timer.
2. The pulse per second stability measurement device of claim 1, wherein the frequency multiplier circuit comprises a phase detector, a loop filter, a voltage controlled oscillator, a frequency divider, and a clock divider;
the phase discriminator, the loop filter, the voltage-controlled oscillator and the clock frequency divider are connected in sequence, and the output end of the voltage-controlled oscillator is connected with the input end of the voltage-controlled oscillator through the frequency divider;
the phase discriminator measures the output frequency of the frequency divider and the phase of the fundamental frequency signal;
the output frequency of the voltage-controlled oscillator is in direct proportion to the output voltage of the loop filter;
when the output frequency of the voltage-controlled oscillator is the frequency division multiple of the crystal and the frequency divider, the output frequency of the clock frequency divider is one half of the output frequency of the voltage-controlled oscillator.
3. The pulse per second stability measurement apparatus of claim 1, wherein the first timer or the second timer comprises a rising edge detector, a counter, and a period register;
the output end of the rising edge detector is connected with the input end of the counter and the first input end of the period register, and the output end of the counter is connected with the second input end of the period register.
4. The pulse-per-second stability measurement device of claim 3, wherein the rising edge detector is to:
when the rising edge of the output of the basic frequency signal is detected, a pulse trigger signal is generated;
when the rising edge of the pulse trigger signal output is detected and the second pulse signal is not detected, the counter counts and latches the counting result to the period register;
and when the rising edge of the pulse trigger signal output is detected and the second pulse signal is detected, the counter count is cleared.
5. The pulse-per-second stability measurement apparatus of claim 3, further comprising a digital signal processing chip, the frequency doubling circuit, first timer, second timer, the digital signal processor, and the asynchronous memory interface being integrated on the digital signal processing chip.
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