CN109143832A - A kind of time-to-digit converter of high-precision multi-path - Google Patents
A kind of time-to-digit converter of high-precision multi-path Download PDFInfo
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- CN109143832A CN109143832A CN201810835353.1A CN201810835353A CN109143832A CN 109143832 A CN109143832 A CN 109143832A CN 201810835353 A CN201810835353 A CN 201810835353A CN 109143832 A CN109143832 A CN 109143832A
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
The invention discloses a kind of time-to-digit converter of high-precision multi-path (Time-to-Digital Converter, TDC), the time-to-digit converter uses two-level configuration；First level structure uses the step-by-step counting type time-to-digit converter based on carry lookahead adder, for realizing high working frequency and Larger Dynamic range；Second level structure uses the multichannel time-to-digit converter based on voltage-controlled difference delay unit and true single phase clock trigger, and second level structure reduces measurement error for improving measurement accuracy.The principle of product utilization two-stage measurement, has taken into account dynamic range and resolution ratio.Voltage-controlled differential inverter and true single phase clock trigger (True single phase clocked have been used in the TDC of the second level, TSPC), it ensure that the good linearity of system and low error rate, overall architecture uses triple channel structure simultaneously, the length of single time delay chain is set to reduce 2/3, uncertainty reduces by 43%, effectively improves the performance of system.
Description
Technical field
The present invention relates to IC design, time mode signal processing technology application field, more particularly to one kind are high-precision
Spend the time-to-digit converter of multichannel.
Background technique
Constantly become smaller recently as the line width of integrated circuit fabrication process, Analogous Integrated Electronic Circuits is lower than 100nm in line width
Low-voltage technique under be easy affected by noise, be extremely difficult to expected performance.And digital integrated electronic circuit is with process
Reduction, switching speed, area and have clear improvement to the rejection ability of noise.Digital integrated electronic circuit is in processing time-domain
The advantage of advanced technologies can be given full play to when signal, but cannot directly handle the signal of amplitude domain.In order to digital integration electricity
Road is applied in Analogous Integrated Electronic Circuits and mixed-signal circuit design in the good characteristic under advanced technologies, how to connect analog domain
Continuous voltage signal is converted into continuous time signal as research hotspot in recent years, and proposes and can will believe continuous time
Number it is converted into the time-to-digit converter (Time-to-Digital Converter, TDC) of discrete digital signal.In addition, in height
In the fields such as energy physics, laser ranging, particle physics and laser three-dimensional imaging, digital quantizer (TDC) or split-second precision
The core cell of interval measurement system.Therefore, the research of digital quantizer (TDC) is for IC design and split-second precision
Measurement is all of great significance.
The performance of TDC is usually measured with parameter indexes such as temporal resolution, dynamic range and measurement errors.Its generation respectively
The probability of mistake occurs for the minimum interval that table TDC can be measured, maximum time interval and measurement.Currently, common TDC
Mainly have following three kinds: 1, step-by-step counting type TDC, the digit of its adjustable counter is realized higher dynamic range, but divided
Resolution is lower, is limited by system clock frequency；2, based on the TDC of gate delay, resolution ratio is the delay value of single logic gate,
It is limited by current process, dynamic range depends on the number of logic gate on delay line, but the length for increasing delay line will
Cause chip area to increase severely, while the uncertainty of time interval being made to become larger, introduces biggish measurement error, therefore this kind of TDC
Dynamic range is typically small；3, lower than the TDC of gate delay, the Typical Representative of this kind of TDC is vernier type TDC, need to only adjust two
The delay inequality of delay unit in one time delay chain can reach very high precision, but when dynamic range is larger, the length of time delay chain
Can be elongated, the measurement error of TDC can become larger at this time, reduce its effective accuracy.
In conclusion how to reduce measurement error as small as possible while realizing Larger Dynamic range and high-resolution is
One difficult task.
Summary of the invention
The contradiction between dynamic range, resolution ratio and measurement error in order to overcome Conventional temporal digital quantizer, this hair
Bright to propose a kind of time-to-digit converter of two-level configuration, the first order uses the step-by-step counting type based on carry lookahead adder
TDC, to realize high working frequency and Larger Dynamic range；The second level is used is touched based on voltage-controlled difference delay unit and true single phase clock
The multichannel TDC for sending out device (True single phase clocked, TSPC), is in the nature the TDC based on gate delay, to mention
High measurement accuracy reduces measurement error, described below:
A kind of time-to-digit converter of high-precision multi-path, the time-to-digit converter use two-level configuration；
First level structure uses the step-by-step counting type time-to-digit converter based on carry lookahead adder, for realizing height
Working frequency and Larger Dynamic range；
Second level structure uses the multichannel time number based on voltage-controlled difference delay unit and true single phase clock trigger
Word converter, second level structure reduce measurement error for improving measurement accuracy.
Further, the true single phase clock trigger is used to guarantee that trigger to have and small establishes the retention time.
Preferably, second level structure uses 3 channel designs.
Wherein, 3 channel design described above specifically:
The output of first delay unit is connected to the data input pin of first TSPC register in first passage, for dividing
Distinguish that size is t1Time interval；
The output of first delay unit is connected to the data input pin of second TSPC register in second channel, for dividing
Distinguish that size is t2=2t1Time interval；
The output of first delay unit is connected to the data input pin of third TSPC register in third channel, for dividing
Distinguish that size is t3=3t1Time interval；
The output of second delay unit is connected to the data input pin of the 4th TSPC register in first passage later, uses
It is t in differentiating size3+t1Time interval, recycle according to this.
Preferably, under identical dynamic range, the length of time delay chain is L/3 in each channel, and L is length.
Preferably, the uncertainty of time interval is the 57% of traditional uncertainty.
The beneficial effect of the technical scheme provided by the present invention is that:
1, in first order TDC, coincidence counter is during realization using carry lookahead adder instead of traditional row
Wave carrier adder is effectively prevented because of long conversion time caused by counting digit increase, thus improves the work of circuit
Frequency simultaneously extends dynamic range.
2, in the TDC of the second level: delay unit uses voltage-controlled type differential inverter, and the delay of delay unit is controlled by voltage
Value is effectively relieved because of delay caused by the factors such as technique, voltage, temperature (Process, Voltage, Temperature, PVT)
Unit mismatch problem reduces measurement error.
Since TSPC trigger is established the retention time with small, thus it can reduce the measurement error of TDC.Meanwhile the
The integral frame of second level TDC is triple channel structure, and under identical dynamic range, the length of single time delay chain is only original 1/
3, the uncertainty of time interval is reduced to original 57% or so, therefore has been obviously improved the performance parameter of TDC.
3, the time-to-digit converter that the present invention designs is realized based on standard CMOS process, may be implemented in same core
On piece integrates high performance time-to-digit converter, Signal coding and arithmetic operator module, so that the cost of device is reduced,
Increase powerful amalgamation.
Detailed description of the invention
Fig. 1 is the TDC system structural block diagram that the present invention designs；
Fig. 2 is the detailed construction schematic diagram inside TDC circuit；
Fig. 3 is the measuring principle schematic diagram of TDC module；
Fig. 4 is the logical construction schematic diagram of first order TDC；
Fig. 5 is traditional TDC electrical block diagram based on delay unit；
Fig. 6 is the circuit diagram of the triple channel TDC with edge calibration and delay compensation module；
Fig. 7 is the structural schematic diagram and circuit diagram of voltage-controlled difference delay unit；
Wherein, (a) is the structural schematic diagram of voltage-controlled difference delay unit；It (b) is the circuit diagram of voltage-controlled difference delay unit.
Fig. 8 is the circuit diagram of TSPC trigger.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, embodiment of the present invention is made below further
Ground detailed description.
Embodiment 1
A kind of time-to-digit converter of high-precision multi-path, referring to Fig. 1, the time-to-digit converter (i.e. TDC system)
Specifically include that three TDC circuit, encoder (2) and arithmetic operator unit parts.
Wherein, between the time between STRAT signal and STOP signal that TDC circuit passes through clock signal clk quantization input
Every difference output codons T1、t2And t3, wherein T1It is binary code, indicates that clk cycle is whole between START signal and STOP signal
The time interval of several times, t2And t3For thermometer code, respectively indicate START signal rising edge and STOP signal rising edge and they most
Time interval between close next cycle clock rising edge.T1It is directly inputted in arithmetic operator unit, t2And t3It inputs respectively
Binary code T is converted into thermometer code-binary code encoder2And T3, it is then input in arithmetic operator unit, together with T1
It participates in operation and exports final time interval T, complete entire measurement process.
Embodiment 2
The scheme in embodiment 1 is further introduced below with reference to specific calculation formula, Fig. 2-Fig. 8, is detailed in
It is described below:
Fig. 2 is the detailed construction inside TDC circuit, and in conjunction with the measuring principle of Fig. 3, this TDC circuit is described.This
TDC circuit is two-level configuration.
Wherein, coincidence counter (first order TDC) is used to measure clk cycle integral multiple, i.e. A in time interval to be measured1(such as
Shown in Fig. 3), export binary code T1.Two identical fine TDC (second level TDC) are respectively to the A less than a clock cycle2
And A3(as shown in Figure 3) is measured, output temperature code t2And t3, and encoded device is converted into binary code T2And T3。
T is calculated by arithmetic operator unit later1+T2-T3, obtain the time interval T between START and STOP signal.TDC
Edge calibration module in circuit is to postpone calibration unit for differential signal needed for the thin TDC of error-free real estate production of sperm and be used to
The delay time error introduced between compensation CLK, START and STOP signal by edge calibration module.
Fig. 4 is the logical construction of first order TDC, and carrylook-ahead adder is used to be as the calculating logic of coincidence counter
A kind of special circumstances of adder: an addend of every full adder is 0, and the other is the previous output S in one's own department or uniti, most
The carry C of low level0Permanent during first order TDC work is 1, the carry C of remainingiIt is the logical table of addend on all positions in front
Up to formula (logical relation does not provide in figure).The output S of common full adder i-th bitiWith carry-out CiLogical expression
Are as follows:
Si=Ai⊕Bi⊕Ci-1 (1)
Ci=AiBi+(Ai+Bi)Ci-1=Gi+PiCi-1 (2)
Wherein, Gi=AiBiFunction, P are generated for carryi=Ai+BiFor carry transmission function.It can be obtained according to formula (1) and (2),
G in the designi=0, Pi=Ai, therefore the S of each adderiAnd CiIt is respectively as follows:
Si=Ai⊕Ci-1 (3)
Ci=AiCi-1 (4)
Therefore, the carry-out C of 6 addersiIt can respectively indicate are as follows:
The output expression formula of each adder can be obtained by formula (3).It can be seen that each output of adder and carry
Output is all the logical expression of input signal, they are generated parallel.
Because first order TDC requires the number of included clock cycle between record START and STOP signal, START
It is the control signal of the counter with STOP.Control logic is as follows: when it is also 1 that START, which is 1, STOP, C0=0；Remaining situation
Under, C0=1, it can thus be appreciated that START signal and STOP signal carry out the available C of NAND operation0, i.e. C0=！(START&
STOP).In addition, START signal is also used as the reset signal of coincidence counter, when START signal is high level, counter is clear
It zero and starts counting, when the rising edge of STOP signal arrives, latches the value of nonce counter and export count results.
Fig. 5 is a kind of traditional structure of fine TDC (second level TDC).START signal is propagated along time delay chain above,
Wherein the delay of each delay unit is t, and the clock end of STOP signal connection d type flip flop, is believed the START after each delay
Number sampling, before STOP signal catch up with START signal, d type flip flop output be 1, once STOP signal is caught up with or advanced START
The output of signal, d type flip flop is changing to 0.If the initial phase difference of START signal and STOP signal is Tin, in thermometer code
The last one 1 appears in n-th grade, then:
n·t≤Tin<(n+1)·t (6)
Due to the influence of noise, every stage of time delay unit has certain delay deviation.It is now assumed that i-stage delay unit
Delay deviation is μi(this value can just be born), then the delay t of i-stage delay unitres,iIt can correct are as follows:
tres,i=t+ μi (7)
Therefore, time interval TinIt may be expressed as:
Wherein, μ is the sum of the delay deviation of all delay units on whole time delay chain.
The environment as locating for every grade of delay unit is identical, therefore the standard deviation of every grade of delay unit delay value is also identical, i.e.,
std(tres,i)=std (μi)=std (μ), after n grades of delay units, the uncertainty std (T of time intervalin) are as follows:
It can be seen that the uncertainty std (T of time intervalin) related with by the length n of time delay chain, be delayed chain length
Longer, the uncertainty of the time interval measured is bigger.
Fig. 6 is the structure of fine TDC in the embodiment of the present invention.Its essence is a kind of TDC based on gate delay, in which: is made
It uses voltage-controlled differential inverter as delay unit, guarantees good matching degree between delay unit；It is replaced using TSPC trigger
Common d type flip flop adjudicates the precedence relationship of start and stop signals phase, ensure that trigger has foundations guarantor as small as possible
Hold the time；While in order to reduce the uncertainty of measurement, second level TDC uses a kind of 3 novel channel designs.
Wherein, START signal is propagated in three channels respectively, the delay size of first delay unit in each channel
Relationship be t2=2t1, t3=3t1, the delay size of other remaining delay units is t3.Channel 1 (i.e. first passage)
In the output of first delay unit be connected to the data input pin of first TSPC register, can differentiate size is t1Time
Interval；The output of first delay unit is connected to the data input pin of second TSPC register in channel 2 (i.e. second channel),
It is t that size, which can be differentiated,2=2t1Time interval；The output of first delay unit is connected in channel 3 (i.e. third channel)
The data input pin of third TSPC register, can differentiate size is t3=3t1Time interval；Later second in channel 1
The output of a delay unit is connected to the data input pin of the 4th TSPC register, and can differentiate size is t3+t1Namely 4
t1Time interval, recycle according to this.The temporal resolution that can learn entire fine TDC is t1, and in identical dynamic range
Under, in each channel the length of time delay chain only have traditional implementation 1/3 (that is, if the length of traditional implementation be L, this
Method is then L/3).
It can be obtained by formula (9), when n becomes original 1/3, in the case where other conditions are constant, time interval is not known
DegreeBecome original 57%, accordingly it can be concluded that the suggested plans time interval of the embodiment of the present invention
Uncertainty be only 57% or so of traditional uncertainty, be obviously improved the performance of TDC.
In the TDC of the second level, it is input between the START signal of voltage-controlled differential inverter and its reverse signal to eliminate
Phase difference that may be present needs that START signal and its reverse signal are first input to progress edge pair in edge calibration module
Neat processing.However edge calibration module may introduce additional delay, cause measurement result bigger than normal.
In order to compensate for this delay, STOP signal before being input to second level TDC, need by delay calibration unit into
Line delay compensation.Second level TDC is a part the most key in time-to-digit converter, to the delay value of delay unit
And d type flip flop establishes the retention time and has higher requirement, it is introduced respectively below.
Fig. 7 (a) gives the structural schematic diagram of voltage-controlled difference reverser.Wherein In+ and In- is two differential input ends,
Two opposite differential signals of state are inputted, Out+ and Out- are signal output ends, and output signal is equally the opposite difference of state
Sub-signal, so the difference output of upper level just can be used as the difference of next stage when multiple voltage-controlled differential inverters are connected
Input.For simplest reverser, although input signal becomes two by original one, differential configuration is mentioned
Stronger anti-interference ability is supplied.Fig. 7 (b) is the circuit structure of voltage-controlled difference reverser, it can be seen that each unit only has 5
Transistor ensure that small chip area.Its course of work are as follows: when In+ input high level, In- input low level, M3 is led
It is logical, M4 cut-off, and M5 is in the conductive state always under the control of Vbias, so Out- exports low level, M2 conducting, Out+
Export high level.In+ input low level, analysis is same as above when In- input high level, and which is not described herein again.
When specific implementation, such as: it can grid by controlling the size of the adjustable unit delay value of grid voltage of M5, on M5
Pressure is bigger, and delay value is smaller, to guarantee the good linearity of time delay chain, reduces measurement error.
Fig. 8 is the circuit structure of TSPC trigger.Its course of work are as follows: when CLK is low level, first order phase inverter exists
Nodes X up-samples the inverse value of input signal IN, and second level phase inverter is in pre-charge state, and node Y is charged to power supply electricity
Pressure, third level phase inverter are in hold mode, i.e. the current potential of Z point remains unchanged, and output OUT keeps original value；When CLK becomes
When high level, second level phase inverter is started to work, if X node in CLK rising edge being temporarily high level, Y node is put
Electricity, otherwise the value of Y node keeps original state, due to CLK be high level when third level phase inverter work normally, Y node
Value is sent to output end OUT.
For discrimination precision, the settling time of TSPC trigger is the delay of first order phase inverter, and the retention time is
The delay of second level phase inverter, such as: as small as possible build can be realized by adjusting the breadth length ratio of transistor in this two-stage phase inverter
It the vertical retention time, avoids data sampling from mistake occur, further improves the precision of system.
In conclusion the time-to-digit converter of high-precision multi-path described in the embodiment of the present invention is measured using two-stage
Principle, taken into account dynamic range and resolution ratio.Voltage-controlled differential inverter and TSPC have been used in the TDC of the second level, ensure that
The good linearity of system and low error rate, while overall architecture uses triple channel structure, makes the length of single time delay chain
2/3 is reduced, uncertainty reduces by 43%, effectively improves the performance of system.
The embodiment of the present invention to the model of each device in addition to doing specified otherwise, the model of other devices with no restrictions,
As long as the device of above-mentioned function can be completed.
It will be appreciated by those skilled in the art that attached drawing is the schematic diagram of a preferred embodiment, the embodiments of the present invention
Serial number is for illustration only, does not represent the advantages or disadvantages of the embodiments.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of time-to-digit converter of high-precision multi-path, which is characterized in that
The time-to-digit converter uses two-level configuration；
First level structure uses the step-by-step counting type time-to-digit converter based on carry lookahead adder, for realizing height work
Frequency and Larger Dynamic range；
Second level structure is turned using the multichannel time figure based on voltage-controlled difference delay unit and true single phase clock trigger
Parallel operation, second level structure reduce measurement error for improving measurement accuracy.
2. a kind of time-to-digit converter of high-precision multi-path according to claim 1, which is characterized in that described very single
Phase clock trigger is used to guarantee that trigger to have and small establishes the retention time.
3. a kind of time-to-digit converter of high-precision multi-path according to claim 1, which is characterized in that described second
Level structure uses 3 channel designs.
4. a kind of time-to-digit converter of high-precision multi-path according to claim 3, which is characterized in that described 3 is logical
Road structure specifically:
The output of first delay unit is connected to the data input pin of first TSPC register in first passage, big for differentiating
Small is t1Time interval；
The output of first delay unit is connected to the data input pin of second TSPC register in second channel, big for differentiating
Small is t2=2t1Time interval；
The output of first delay unit is connected to the data input pin of third TSPC register in third channel, big for differentiating
Small is t3=3t1Time interval；
The output of second delay unit is connected to the data input pin of the 4th TSPC register in first passage later, for point
Distinguish that size is t3+t1Time interval, recycle according to this.
5. a kind of time-to-digit converter of high-precision multi-path according to claim 4, which is characterized in that identical
Under dynamic range, the length of time delay chain is L/3 in each channel, and L is length, and the uncertainty of time interval is original
57%.
6. a kind of time-to-digit converter of high-precision multi-path described in any claim in -5 according to claim 1,
It is characterized in that, the time-to-digit converter guarantees small measurement error while realizing Larger Dynamic range and high-resolution.
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| CN110794668A (en) * | 2019-11-14 | 2020-02-14 | 中电科仪器仪表有限公司 | Time interval measuring device and method based on multi-channel interpolation |
| CN114280912A (en) * | 2020-09-28 | 2022-04-05 | 宁波飞芯电子科技有限公司 | Method for measuring flight time and time-to-digital converter |
| CN113835332A (en) * | 2021-09-29 | 2021-12-24 | 东南大学 | High-resolution two-stage time-to-digital converter and conversion method |
| CN113835332B (en) * | 2021-09-29 | 2022-08-23 | 东南大学 | High-resolution two-stage time-to-digital converter and conversion method |
| CN115902835A (en) * | 2021-09-30 | 2023-04-04 | 深圳市速腾聚创科技有限公司 | Radar data receiving and transmitting device, distance measuring method and laser radar |
| CN115902835B (en) * | 2021-09-30 | 2024-02-27 | 深圳市速腾聚创科技有限公司 | Radar data receiving and transmitting device, ranging method and laser radar |
| CN114967409A (en) * | 2022-03-28 | 2022-08-30 | 中山大学 | High-precision time-to-digital converter resisting PVT change and implementation method thereof |
| CN116991227A (en) * | 2023-09-26 | 2023-11-03 | 北京中科昊芯科技有限公司 | Device for acquiring high-precision signals, soC chip and electronic equipment |
| CN116991227B (en) * | 2023-09-26 | 2024-01-26 | 北京中科昊芯科技有限公司 | Device for acquiring high-precision signals, soC chip and electronic equipment |
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