CN112838851A - Residual time sampling circuit based on differential sampling and time-to-digital converter - Google Patents

Residual time sampling circuit based on differential sampling and time-to-digital converter Download PDF

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CN112838851A
CN112838851A CN202110211488.2A CN202110211488A CN112838851A CN 112838851 A CN112838851 A CN 112838851A CN 202110211488 A CN202110211488 A CN 202110211488A CN 112838851 A CN112838851 A CN 112838851A
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signal
time
circuit
arbiter
output
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张彪
白雪飞
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University of Science and Technology of China USTC
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University of Science and Technology of China USTC
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching

Abstract

The invention discloses a residual time sampling circuit and a time digital converter based on differential sampling, wherein the time digital converter comprises a CTDC (computer to digital converter), an FTDC (fiber to the digital converter), a residual time sampling circuit, a thermometer code/binary code conversion circuit, a serial output circuit and a voltage-controlled phase-locked loop circuit; the residual time sampling circuit can sample the opposite signal of the CTDC output and the Stop signal for arbitration output symmetry through an arbiter based on a sensitive amplifier as a control signal; quantizing an input time interval, namely a time difference between rising edges of a Start signal and a Stop signal, by using a CTDC (computer to digital converter), and outputting 4 most significant bits by a decoder according to a quantization result; the residual time sampling circuit extracts the residual time of the CTDC, converts the residual time into a time difference between rising edges of a signal SE and a signal FE, inputs the time difference into the FTDC for re-quantization, and generates 7-bit least significant bits by a decoder according to a quantization result; the control circuit turns off the FTDC quantization action after detecting the FTDC quantization end signal and turns on the output of the serial circuit.

Description

Residual time sampling circuit based on differential sampling and time-to-digital converter
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and in particular, to a differential sampling based residual Time sampling circuit and a gated ring oscillator based two-stage Time-to-Digital Converter (TDC).
Background
The residual time sampling circuit is applied to the design of a two-stage or multi-stage time-to-digital converter, and the time margin acquisition in the coarse quantization TDC is transferred to the fine quantization TDC. The time-to-digital converter is used for converting the time interval between the signals into corresponding numbers and outputting the corresponding numbers. At present, the TDC is widely applied to scientific research fields such as laser ranging, 3D imaging, quantum communication, nuclear physics, and the like, and TDCs of various structures emerge endlessly to meet the requirements of various engineering and scientific research fields.
With the great improvement of the semiconductor process level, the measurement precision of time is gradually improved and the femtosecond resolution is gradually achieved. Meanwhile, the time delay and low power consumption of the digital gate circuit are reduced along with the process, so the performance and power consumption performance of the time domain and digital domain circuit are continuously improved, and higher resolution and better linearity can be obtained in the time domain and the digital domain.
Disclosure of Invention
In order to solve the technical problems, the invention provides a low-power consumption, high-precision and high-precision residual time sampling circuit based on differential sampling and a time-to-digital converter with high resolution, high linearity, large range and automatic reset, which can accurately quantize an input time interval and output a corresponding digital signal. Meanwhile, a specific MOS tube is added in the rising edge/falling edge arbiter, so that the automatic reset function of the circuit is realized. In addition, compared with the traditional serial output circuit, the serial output circuit realized by adopting the improved trigger has simpler circuit structure and higher output frequency.
The purpose of the invention is realized by the following technical scheme: 1. a differentially sampled residual time sampling circuit, comprising: the circuit comprises an arbiter based on a sensitive amplifier, a buffer and an inverter formed by connecting four MOS in series, wherein the output of the arbiter and the output of the buffer are used as input signals of the inverter, and in order to enable the input signals to be correctly sampled, the time for the signals to pass through the buffer needs to be ensured to be longer than the time for the signals to pass through the arbiter; a symmetrical structure is adopted, so that the delay introduced in the process of extracting the coarse quantization TDC output signal is equal to the delay introduced in the process of extracting the Stop signal, and the finally acquired time margin is equal to the actual residual time; and comparing the coarse quantization TDC output signal with the Stop signal by the sensitive amplifier-based arbiter, and outputting a symmetrical opposite signal as a switch control signal of an inverter formed by four MOS tubes.
According to another aspect of the present invention, a time-to-digital converter for performing differential sampling by using the remaining time sampling circuit is provided, which is characterized by comprising a coarse quantization TDC, a fine quantization TDC, a remaining time sampling circuit, a thermometer code/binary code conversion circuit, a serial output circuit, and a voltage-controlled phase-locked loop circuit;
quantizing an input time interval, namely a time difference between rising edges of a Start signal and a Stop signal through a coarse quantization TDC, and outputting 4 most significant bits from a quantization result through a decoder; the residual time sampling circuit extracts the residual time of the coarse quantization TDC, converts the residual time into a time difference between rising edges of a signal SE and a signal FE, inputs the time difference into the fine quantization TDC to be quantized again, and generates 7-bit least significant bits through a decoder according to a quantization result; the control circuit closes the fine quantization TDC quantization action after detecting the fine quantization TDC quantization end signal and starts the output of the serial circuit.
Further, the method comprises the following steps: a voltage-controlled delay chain is used as a high-section TDC structure to enlarge the measurement range, a vernier caliper type ring oscillator structure is used for realizing high resolution of the low-section TDC structure, a counter is added to reduce the circuit area, and meanwhile, an end signal is fed back to an enable signal generating circuit to reduce the circuit power consumption.
Furthermore, the same buffer unit is added behind the delay units of the coarse quantization TDC and the delay phase-locked loop circuit, so that the loads of the delay units in the two circuits are the same, the load capacity of the delay units in the coarse quantization TDC is improved, the influence of different input states of the arbiter on the delay of the delay units in the coarse quantization TDC is blocked, and the linearity of the coarse quantization TDC is improved.
Further, the fine quantization TDC includes: a fast ring oscillator, a rising edge arbiter, a falling edge arbiter, a slow ring oscillator, and a four bit counter; before quantization, a reset signal EVEN _ R resets the output of an EVEN-level delay unit in the fast/slow ring oscillator to zero, and a signal ODD _ R sets an ODD-level delay unit to one; after the coarse quantization TDC is quantized, generating SE/SB and FE/FB signals as starting signals of a fast ring oscillator and a slow ring oscillator respectively; meanwhile, the output of the fast ring oscillator and the output of the slow ring oscillator are input into a rising edge arbiter and a falling edge arbiter, and whether the rising edge or the falling edge of the output signal of the fast ring oscillator arrives earlier than the rising edge or the falling edge of the output signal of the slow ring oscillator is judged; the counter starts counting on the trigger of the slow ring oscillator output S0.
Furthermore, the rising edge arbiter adds two PMOS tubes in the arbiter based on the sensitive amplifier, and resets the arbiter output to zero when the quantization starts; and an NMOS tube is added into the falling edge arbiter.
Further, a serial output circuit stores the output of the arbiter in the coarse quantization TDC and the fine quantization TDC after the quantization of the fine quantization TDC is finished, and outputs data under the trigger of a specified clock; the circuit adopts a TSPC register, and two MOS tubes M1 and M2 are added to the circuit for sampling the result of the arbiter. The input port J of the register is connected to the output of the arbiter, and the input port T is connected to a fine quantization TDC quantization end flag signal R _ SIG; when the flag signal R _ SIG is equal to zero, the register reads the result of the arbiter; when the flag signal R _ SIG is equal to one, the register serially outputs data triggered by the clock CLK, and the signal TC is generated by the signal R _ SIG.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
(1) the same buffer unit is added behind the delay units of the coarse quantization TDC and the delay phase-locked loop circuit, so that the loads of the delay units in the two circuits are ensured to be the same, the load capacity of the delay units in the coarse quantization TDC is increased, the influence of different input states of the arbiter on the delay of the delay units in the coarse quantization TDC is blocked, and the linearity of the coarse quantization TDC is improved;
(2) the invention reduces the power consumption of the time-to-digital converter by feeding back the end signal to the enable signal circuit;
(3) in the invention, a specific reset system is adopted, and an extra reset MOS tube is added in a rising edge/falling edge arbiter to ensure that the output of the arbiter is zero before quantization;
(4) the residual time sampling circuit adopts a symmetrical structure, and simultaneously, the control of a plurality of signals is utilized to ensure that a path cannot be formed in the circuit, so that the power consumption of the circuit is reduced;
(5) the serial output circuit realizes two modes of data sampling and transmission through the specific control circuit and the trigger, and compared with the traditional serial output circuit, the circuit has simpler structure and higher output frequency.
Drawings
FIG. 1 is a schematic diagram of the overall circuit structure of a time-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a timing diagram of an embodiment of the present invention;
FIG. 3 is a coarse quantization TDC and residual time sampling circuit provided by an example of the present invention;
fig. 4 is a schematic diagram of a control circuit according to an embodiment of the present invention, (a) is a schematic diagram of generating a reset signal RST by inverting a Stop signal and performing an and operation with a Start signal; (b) the interval time Ti between the Stop signal and the Start signal is very small;
FIG. 5 is a generation circuit of a fine quantized TDC enable signal;
FIG. 6 is a circuit for generating an end signal R _ SIG signal;
FIG. 7 is a schematic diagram of a fine-scaled TDC circuit using a gated vernier caliper ring oscillator mechanism;
FIG. 8 is a rising edge arbiter circuit and a falling edge arbiter circuit of the present invention; (a) an arbiter circuit for a rising edge; (b) a falling edge arbiter circuit;
fig. 9 is a serial output circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without any inventive step, are within the scope of the present invention.
According to an embodiment of the present invention, a time-to-digital converter based on differential sampling is shown in fig. 1, and includes a Coarse quantization TDC (Coarse TDC, CTDC), a Fine quantization TDC (Fine TDC, FTDC), a residual time sampling circuit, a thermometer code/binary code conversion circuit, a serial output circuit, and a voltage-controlled phase-locked loop circuit.
Quantizing an input time interval, namely a time difference between rising edges of a Start signal and a Stop signal, by using a CTDC (computer to digital converter), and outputting 4 most significant bits by a decoder according to a quantization result; the residual time sampling circuit extracts the residual time of the CTDC, converts the residual time into a time difference between rising edges of a signal SE and a signal FE, inputs the time difference into the FTDC for re-quantization, and generates 7-bit least significant bits by a decoder according to a quantization result; the control circuit turns off the FTDC quantization action after detecting the FTDC quantization end signal and turns on the output of the serial circuit.
In order to avoid the influence of the external environment on the circuit, the voltage-controlled phase-locked loop circuit is added into the system, so that the stability and the accurate delay time of the system are improved. Fig. 2 is a timing diagram of the TDC of the present invention, in which the time difference between the rising edges of the Start signal and the Stop signal is the input time interval. The voltage controlled phase locked loop equally divides the period of the reference clock Fref with the frequency of 100MHz into fifty parts, and the delay value of each delay unit in the CTDC is maintained at 200 ps. The remaining time sampling circuit transmits the remaining time, i.e., the rising edge of the Stop signal and the rising edge of the first delay unit located after the Stop signal in the CTDC to the FTDC, wherein the FTDC includes two delay chains with different delays, a fast delay chain and a slow delay chain, i.e., an F-chain and an S-chain, as shown in fig. 7. And subtracting the delay difference t of the two delay units every time the residual time passes through one delay unit in the F chain until the rising edge or the falling edge of the output signal Fn of the F chain delay unit is earlier than that of the output signal Sn (n is 0,1.. 6) of the S chain delay unit, and indicating that the quantization is finished. The quantization result is calculated as:
Tin＝T×(Nc+1)-(T1-T2)×Nf (1)
wherein N iscAnd NfThe output of CTDC and the output of FTDC are binary codes obtained by a decoding circuit, and T is CTDC delayDelay of time cell, T1、T2The delay of the delay unit of the slow delay chain and the fast delay chain in the FTDC respectively. Fig. 3 is a schematic diagram of a CTDC and remaining time sampling circuit according to an embodiment of the present invention. The device comprises an arbiter based on a sensitive amplifier, a buffer with larger time delay and an inverter formed by connecting four MOS in series, wherein the output of the arbiter and the buffer is used as an input signal of the inverter. In order to correctly sample the input signal, it is necessary to ensure that the signal passes through the buffer for a longer time than the arbiter.
Before each quantization, the reset signal R of the arbiter turns on the MOS transistors M1 and M4, pulling C0 and D0 high, and the outputs P and Q of the arbiter are reset to low through the inverter. Therefore, the MOS transistors P1 and P2 in the sampling unit are in the on state, pulling StartL and StopL high, and the output signals StopN and StartN are also reset to low. The output In (N ═ 1,2.. 14) of each delay cell of the CTDC at quantization is connected to the D port of the corresponding arbiter and compared with the SP signal input to the C port of the arbiter, and when the rising edge of In is located after the rising edge of the signal SP, the output Q of the corresponding arbiter rises high, so that the connected sampling cell pulls the signal StartL low through the MOS transistors N1 and N2, and the output signal StopN also rises high accordingly. Because each delay unit in the CTDC is connected with an arbiter and a residual time sampling circuit, in order to ensure that the load of the delay unit in the CTDC is the same as that of the delay unit in the voltage-controlled phase-locked loop, a buffer unit is connected to the delay unit in the two circuits, and the buffer unit is connected to other circuits. Meanwhile, the addition of the buffer unit increases the load capacity of each delay unit and avoids the influence of different states of the arbiter on the delay. The residual time sampling circuit ensures the balance of the system by using a symmetrical structure and reduces errors. To ensure that the time margin can be correctly collected, it is necessary to ensure that the time for the Stop to reach Y through the arbiter is less than the time t for the Stop to reach X through the buffer.
Before each measurement, the circuit needs to be ensured to be in an original state, so that a reset signal is generated to reset the FTDC, the arbiter, the counter and the like before the measurement. In fig. 4(a), the reset signal RST is generated by inverting the Stop signal and performing an and operation with the Start signal. Since the reset of the circuit requires a certain time, it has to be ensured that the reset pulse of the reset signal can be larger than the minimum reset time of the circuit. As shown in fig. 4(b), when the interval time Ti between the Stop signal and the Start signal is small, it is necessary to make the delay T of the inverter larger than the reset time of the circuit in order to ensure that the circuit can be reset.
Fig. 5 is a circuit for generating an FTDC enable signal, in order to ensure that the oscillator can automatically stop oscillation after FTDC quantization is finished to reduce power consumption, a quantization end signal R _ SIG is added to the circuit to control generation of the enable signal, that is, when R _ SIG is equal to zero, the StartN and StopN signals can generate the enable signal.
Fig. 6 shows a circuit for generating an R _ SIG signal, where circuit input signals Qn and Pn (n is 0,1.. 6) are output signals of arbiters in the FTDC, and when an output of one of the arbiters is at a high level, a circuit output thereof becomes a high level, which indicates that the FTDC quantization is finished.
FIG. 7 is a schematic diagram of an FTDC circuit employing a gated vernier caliper ring oscillator mechanism, comprising: fast ring oscillator 1, rising edge arbiter 2, falling edge arbiter 3, slow ring oscillator 4, and four bit counter 5. Before quantization, the reset signal EVEN _ R resets the output of the EVEN stage delay cells in the fast/slow ring oscillator to zero, and the signal ODD _ R sets the ODD stage delay cells to one. After CTDC quantization is finished, SE/SB and FE/FB signals are generated as starting signals of the fast ring oscillator and the slow ring oscillator respectively. And simultaneously inputting outputs Fn and Sn (n is 0.. 6) of the fast ring oscillator and the slow ring oscillator into a rising edge and falling edge arbiter, and judging whether the rising edge or the falling edge of the output signal of the fast ring oscillator arrives earlier than the rising edge or the falling edge of the output signal of the slow ring oscillator. The counter starts counting as triggered by the slow ring oscillator output S0, and increments every time the signal goes through the S oscillator for one cycle, the final result being decremented by one because the counter automatically increments each time the FTDC starts quantizing. The quantization result of FTDC can thus be expressed as:
TFO＝((NC-1)×14+NF)×(TS-TF) (2)
wherein N isCRepresenting the output of a counter, NFRepresenting the count of the oscillator, TSIndicating S-oscillator delay unit delay, TFRepresenting the F oscillator delay unit delay.
The rising edge arbiter 2 adds two PMOS transistors P1 and P2 to a conventional sense amplifier based arbiter, as shown in fig. 8(a), with the source of the MOS transistor connected to the supply voltage, the drain connected to C0 or D0, and the gate R2 connected to the reset signal EVEN _ R, resetting the arbiter output to zero at the start of quantization. Similarly, NMOS transistors N1 and N2 are added between C0, D0 and ground in the falling edge arbiter shown in fig. 8(b), while the gate R2 is connected to the reset signal ODD _ R. The minimum time difference between the input signals that can be detected determines the accuracy of the arbiter. In order to improve the accuracy of the arbiter, a MOS transistor is added between the arbiter nodes C1 and D1.
Fig. 9 is a serial output circuit as used herein. The serial output circuit stores the outputs of the arbiters in the CTDC and the FTDC after the FTDC quantization is finished, and outputs data under the trigger of a specified clock. The circuit adopts a TSPC register, and two MOS tubes M1 and M2 are added to the circuit for sampling the result of the arbiter. The register input port J is connected to the output of the arbiter, and the input port T is connected to the FTDC quantization end flag signal R _ SIG. When the flag signal R _ SIG is equal to zero, the register reads the result of the arbiter; when the flag signal R _ SIG is equal to one, the register serially outputs data triggered by the clock CLK. The signal TC is generated by the signal R _ SIG.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (7)

1. A differentially sampled residual time sampling circuit, comprising: the circuit comprises an arbiter based on a sensitive amplifier, a buffer and an inverter formed by connecting four MOS in series, wherein the output of the arbiter and the output of the buffer are used as input signals of the inverter, and in order to enable the input signals to be correctly sampled, the time for the signals to pass through the buffer needs to be ensured to be longer than the time for the signals to pass through the arbiter; a symmetrical structure is adopted, so that the time delay introduced in the CTDC output signal extraction process is equal to the time delay introduced in the Stop signal extraction process, and the finally acquired time margin is equal to the actual residual time; and the sensitive amplifier-based arbiter compares the CTDC output signal with the Stop signal and outputs a symmetrical opposite signal as a switch control signal of an inverter formed by four MOS tubes.
2. A two-stage time-to-digital converter based on a gated ring oscillator designed by using the residual time sampling circuit of claim 1, comprising a CTDC, an FTDC, a residual time sampling circuit, a thermometer code/binary code conversion circuit, a serial output circuit, a voltage-controlled phase-locked loop circuit;
quantizing an input time interval, namely a time difference between rising edges of a Start signal and a Stop signal, by using a CTDC (computer to digital converter), and outputting 4 most significant bits by a decoder according to a quantization result; the residual time sampling circuit extracts the residual time of the CTDC, converts the residual time into a time difference between rising edges of a signal SE and a signal FE, inputs the time difference into the FTDC for re-quantization, and generates 7-bit least significant bits by a decoder according to a quantization result; the control circuit turns off the FTDC quantization action after detecting the FTDC quantization end signal and turns on the output of the serial circuit.
3. A time-to-digital converter as claimed in claim 2, comprising: a voltage-controlled delay chain is used as a high-section TDC structure to enlarge the measurement range, a vernier caliper type ring oscillator structure is used for realizing high resolution of the low-section TDC structure, a counter is added to reduce the circuit area, and meanwhile, an end signal is fed back to an enable signal generating circuit to reduce the circuit power consumption.
4. The time-to-digital converter according to claim 2, wherein the same buffer unit is added after the delay units of the CTDC and the delay-locked loop circuit to ensure that the loads of the delay units in the two circuits are the same, and the buffer unit is used for improving the load capability of the delay units in the CTDC, blocking the influence of different input states of the arbiter on the delay of the delay units in the CTDC, and improving the linearity of the CTDC.
5. A time-to-digital converter according to claim 2, wherein FTDC comprises: a fast ring oscillator, a rising edge arbiter, a falling edge arbiter, a slow ring oscillator, and a four bit counter; before quantization, a reset signal EVEN _ R resets the output of an EVEN-level delay unit in the fast/slow ring oscillator to zero, and a signal ODD _ R sets an ODD-level delay unit to one; after CTDC quantization is finished, generating SE/SB and FE/FB signals as starting signals of a fast ring oscillator and a slow ring oscillator respectively; meanwhile, the output of the fast ring oscillator and the output of the slow ring oscillator are input into a rising edge arbiter and a falling edge arbiter, and whether the rising edge or the falling edge of the output signal of the fast ring oscillator arrives earlier than the rising edge or the falling edge of the output signal of the slow ring oscillator is judged; the counter starts counting on the trigger of the slow ring oscillator output S0.
6. A time-to-digital converter as claimed in claim 2, wherein the rising edge arbiter adds two PMOS transistors to the sense amplifier based arbiter, resetting the arbiter output to zero at the start of quantization; and an NMOS tube is added into the falling edge arbiter.
7. A time-to-digital converter as claimed in claim 2, wherein the serial output circuit stores the outputs of the arbiters in CTDC and FTDC after the FTDC quantization is completed, and outputs the data under the trigger of a specified clock; the circuit adopts a TSPC register, and two MOS tubes M1 and M2 are added to the circuit for sampling the result of the arbiter. The input port J of the register is connected to the output of the arbiter, and the input port T is connected to an FTDC quantization end flag signal R _ SIG; when the flag signal R _ SIG is equal to zero, the register reads the result of the arbiter; when the flag signal R _ SIG is equal to one, the register serially outputs data triggered by the clock CLK, and the signal TC is generated by the signal R _ SIG.
CN202110211488.2A 2021-02-25 2021-02-25 Residual time sampling circuit based on differential sampling and time-to-digital converter Pending CN112838851A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113552791A (en) * 2021-06-08 2021-10-26 西安电子科技大学 Ultra-high speed time encoder and encoding method based on transmission line traveling wave quantization
CN113552792A (en) * 2021-06-08 2021-10-26 西安电子科技大学 Ultra-high-speed time encoder and encoding method based on transmission line phase hedging
CN114047682A (en) * 2021-11-16 2022-02-15 华南理工大学 Time-to-digital converter with PVT robustness based on fully differential ring oscillator
CN117674853A (en) * 2023-11-14 2024-03-08 北京中科海芯科技有限公司 Sample hold circuit and time digital converter

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113552791A (en) * 2021-06-08 2021-10-26 西安电子科技大学 Ultra-high speed time encoder and encoding method based on transmission line traveling wave quantization
CN113552792A (en) * 2021-06-08 2021-10-26 西安电子科技大学 Ultra-high-speed time encoder and encoding method based on transmission line phase hedging
CN113552792B (en) * 2021-06-08 2022-05-13 西安电子科技大学 Ultra-high speed time encoder and encoding method based on transmission line phase hedging
CN113552791B (en) * 2021-06-08 2022-05-24 西安电子科技大学 Ultra-high speed time encoder and encoding method based on transmission line traveling wave quantization
CN114047682A (en) * 2021-11-16 2022-02-15 华南理工大学 Time-to-digital converter with PVT robustness based on fully differential ring oscillator
CN114047682B (en) * 2021-11-16 2022-08-12 华南理工大学 Time-to-digital converter with PVT robustness based on fully differential ring oscillator
CN117674853A (en) * 2023-11-14 2024-03-08 北京中科海芯科技有限公司 Sample hold circuit and time digital converter

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