CN110958019A - Three-stage TDC based on DLL - Google Patents

Three-stage TDC based on DLL Download PDF

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Publication number
CN110958019A
CN110958019A CN201911323460.7A CN201911323460A CN110958019A CN 110958019 A CN110958019 A CN 110958019A CN 201911323460 A CN201911323460 A CN 201911323460A CN 110958019 A CN110958019 A CN 110958019A
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counting
signal
stage
delay
fine
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CN110958019B (en
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张源涛
吕延歌
常玉春
蒋佳奇
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Jilin University
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Jilin University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/097—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters

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Abstract

The invention discloses a three-stage TDC based on DLL, belonging to the technical field of integrated circuits, and comprising a coarse counting phase, a middle counting phase, a fine counting phase and a delay phase-locked loop; the DLL-based three-stage TDC realizes the high quantization precision of 10ps while realizing the dynamic range of 52 mus, is compatible with the wide dynamic range and the high quantization precision, and reduces the area consumption; the middle-stage counting edge detector extracts the rising edge of the clock CLK corresponding to the middle-stage counting, so that the clock CLK is prevented from being delayed, and the power consumption is reduced; the fine counting edge detector is realized by adopting a multi-path selector, so that the metastable state problem caused by DFF is avoided; the edge detector adopted by the invention introduces delay correction, can perfectly connect all levels of TDC, and avoids the generation of coarse quantization to fine quantization transmission delay; the Encoder adopted by the invention converts thermometer codes into Gray codes, so that the decoding accuracy is greatly improved, the measurement accuracy and stability are improved by using DLL, and the anti-interference capability of TDC is improved.

Description

Three-stage TDC based on DLL
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a three-level TDC based on DLL.
Background
The TDC (Time-to-Digital Converter) is a bridge between an analog Time signal and a Digital signal which is convenient to process, and can complete the conversion between the two and process the Time interval between two asynchronous signals. The time quantum is the most basic of seven basic quantities in the international system of units, the universality, the high-precision measurement and the universality of the seven basic quantities are not possessed by other physical quantities, and the time quantum is often converted into the time quantum for measurement in order to explore the properties and the mutual relations of some physical quantities.
In the field of high-precision measurement, the TDC is often required to reach ps-level time measurement precision, and the research of the high-performance TDC is particularly important. TDC is often used in the fields of laser ranging and radar ranging, etc., due to its high-precision measurement and superior performance.
In recent research on TDCs, there are main methods for implementing TDCs: the existing TDC structure is mostly a single mode or two-section structure, and when ps-level precision is realized, the dynamic range can be mostly ns-level for saving area, so that the realization of high precision and high dynamic range simultaneously is always the bottleneck of TDC research and the development direction of TDC. In addition, the stability and accuracy of the TDC are also important factors to be considered in the research process, and at present, all the methods such as a full-digital self-calibration method, reducing the delay chain length, adding an auxiliary test circuit and the like all achieve some achievements, however, the methods only reduce the influence to a certain extent, and more effective methods are yet to be researched and found.
Disclosure of Invention
In order to solve the above problems in the prior art, the invention provides a DLL based three-stage TDC, so as to realize compatibility of a dynamic range and high precision, and ensure stability and accuracy of a high-frequency lower delay unit on the basis, wherein a timing schematic diagram of the DLL based three-stage TDC is shown in fig. 1; the TDC provides stable control voltage for a single delay chain of middle-stage counting (MTDC) and a double-voltage control delay chain of fine counting (FTDC) in the TDC through a Delay Locked Loop (DLL), accurate measurement of the TDC on the measured time is guaranteed, and finally, the stored results of all parts of circuits are output through a Data Storage Unit.
The invention is realized by the following technical scheme:
a three-level TDC based on DLL comprises a coarse counting Unit (CTDC), a Middle counting Unit (MTDC), a Fine counting Unit (FTDC) and a Delay Locked Loop (DLL), wherein the coarse counting Unit and the Middle counting Unit are connected through a Middle counting edge Detector (middleledge Detector), the Middle counting Unit and the Fine counting Unit are connected through a Fine counting edge Detector (Fine edge Detector), the delay locked loop is used for providing control voltage for a voltage-controlled delay chain of the Middle counting Unit and the Fine counting Unit, the Middle counting Unit is connected with a Middle counting decoder (Middle Encoder), the Fine counting Unit is connected with a Fine counting decoder (Fine Encoder), and the outputs of the Middle counting decoder, the Fine counting decoder and the coarse counting Unit are connected with a Data Storage Unit (Data Storage Unit), as shown in FIG. 2; the Coarse counting receives an external clock signal and photon pulse START and STOP signals from the detector, and generates a Coarse counting result Coarse Data; the mid-stage counting edge detector receives an external clock signal and a STOP signal and generates STARTM and STOPM signals; the Middle stage counting receives STARTM and STOPM signals of the Middle stage counting edge detector, generates delay signals D <0:7> and 8-bit thermometer codes M <0:7>, and transmits the 8-bit thermometer codes M <0:7> to the Middle stage counting decoder, and generates a Middle stage counting result Middle Data; the fine counting edge detector receives an STOPM signal of the Middle counting edge detector, a delay signal D <0:7> of the Middle counting and Middle counting result Middle Data to generate STARTF and STOPF signals; the Fine count receives STARTF and STOPF signals of the edge detector, generates a 20-bit thermometer code F <0:19>, transmits the thermometer code F <0:19>, and generates a Fine count result Fine Data; the coarse counting result, the middle-level counting result and the fine counting result are all transmitted to a data storage unit; the delay phase-locked loop receives an external clock signal, generates a control voltage Vctrl and provides the control voltage for the voltage-controlled delay chain of the intermediate-stage counting and the fine counting.
Further, the coarse count is used to count the number of clocks between START and STOP, measuredIs T in FIG. 1CA time period, i.e., a time interval between a START signal and a STOP signal, which are pulse signals generated by the detector after detecting a photon, and a next clock rising edge; the coarse count is composed of an 8-bit counter, an 8-input AND gate, a 7-bit counter, and a trigger (DFF), as shown in FIG. 3; the 8-bit counter receives a START signal and an externally provided 640MHz clock signal, and an 8-bit output result Q generated by the 8-bit counter<0:7>Transmitting to 8-input AND gate, transmitting to 7-bit counter carry signal CO generated by 8-input AND gate and RST signal provided from outside, and outputting result QC by 7-bit generated by 7-bit counter<0:6>8-bit output result Q generated by 8-bit counter<0:7>And the STOP signal is transmitted to the trigger, and the trigger outputs a Coarse counting result Coarse Data.
Further, the mid-stage count edge detector is configured to generate a new set of START and STOP signals-STARTM and STOPM based on the coarse count, which are sent to the MTDC for MTDC counting; the mid-stage counting edge detector consists of two 2-input AND gates A1, A2 and a flip-flop DFF, as shown in FIG. 4; the 2-input AND gate A1 receives an external clock signal and a STOP signal, an output signal S1 of the 2-input AND gate and a high-level VDD signal are transmitted to the flip-flop, and an output signal of the flip-flop is a new STOP signal, namely a STOPM signal; the 2-input and gate a2 receives the high level VDD and STOP signals and generates a new START signal, the STARTM signal.
Further, the time interval of the middle stage count measurement is T in FIG. 1MThe time period, i.e., the time interval between the STARTM signal and the last delayed signal before the STOPM signal arrives; the middle stage count includes two parts, namely a voltage controlled delay chain (VCDL) and a comparator array composed of flip-flops, as shown in fig. 5, the voltage controlled delay chain is composed of 8 delay units (the number of the delay units is different according to the resolution of the middle stage count), receives the STARTM signal of the middle stage count edge detector, and generates a corresponding delay signal D after passing through i (i is 1, 2<i-1>Delayed signal D<i-1>And the STOPM signal is transmitted to the comparatorArray, comparator array producing 8-bit thermometer code data M<0:7>And the intermediate-level counting code is transmitted to an intermediate-level counting decoder, the 8-bit thermometer code is transcoded into 3-bit Gray code Data, and an intermediate-level counting result Middle Data is generated.
Further, the fine count edge detector is used to generate a new set of START and STOP signals-STARTF and STOPF-based on the mid-level counts that are sent to the FTDC for FTDC counting; the fine count edge detector consists of 10 one-out-of-two multiplexers MUX (M0-M9), as shown in FIG. 6; the said multiplexer M0 receives the STOPM signal of the Middle-stage counting edge detector, the delay signal D <0> of the Middle-stage counting and the output result Middle Data <0>, M1 receives the delay signals D <1> and D <2> of the Middle-stage counting and the output result Middle Data <0> of the Middle-stage counting decoder, M2 receives the delay signals D <3> and D <4> of the Middle-stage counting and the output result Middle Data <0> of the Middle-stage counting decoder, M3 receives the delay signals D <5> and D <6> of the Middle-stage counting and the output result Middle Data <0> of the Middle-stage counting decoder, and then the output result S1 of M0, the output result S2 of M1 and the output result Middle Data <1> of the Middle-stage counting decoder are transmitted to M4, the output result S3 of M2, the output result S4 of M3 and the output result Middle Data <1> of the Middle-stage counting decoder are transmitted to M5, then the output result S5 of M4, the output result S6 of M5 and the output result Middle Data <2> of the Middle-stage counting decoder are transmitted to M6, and the output signal of M6 is a new START signal, namely a STARTF signal; the multiplexer M7 receives the STOP pm signal and the low level GND signal of the middle-stage counting edge detector, the output result S7 and the low level GND of M7 are transmitted to M8, the output result S8 and the low level GND of M8 are transmitted to M9, and the output signal of M9 is the new STOP signal, i.e., the STOP signal.
Further, the time interval of the fine count measurement is T of FIG. 1FThe time period, i.e., the time interval between the STOPM signal and the last delayed signal before the STOPM signal arrives; the fine count includes two voltage-controlled delay chains and a comparator array composed of flip-flops, as shown in fig. 7;the voltage-controlled delay chain V1 is composed of 20 voltage-controlled delay units (the number of the delay units may also be different according to the FTDC resolution), each delay unit has a delay size τ 1, receives a STARTF signal of the fine count edge detector, and generates a corresponding delay signal DF each time i (i is 1, 2<i-1>(ii) a The voltage-controlled delay chain V2 is also composed of 20 voltage-controlled delay units, each delay unit has a delay value τ 2, receives the STOPF signal of the fine count edge detector, and generates a corresponding delay signal DS each time the signal passes through i (i is 1, 2.., 20) delay units<i-1>(ii) a Time delay signal DF<i-1>And DS<i-1>Transmitted to a comparator array which generates 20-bit thermometer code data F<0:19>And transmitting the Data to a Fine counting decoder, transcoding the 20-bit thermometer code into 5-bit Gray code Data, and generating a Fine counting result Fine Data.
Further, the delay locked loop DLL is configured to provide a control voltage for the voltage-controlled delay chain of the middle-stage counting and the fine counting, and is composed of a Phase Frequency Detector (PFD), a Charge Pump (CP) and a voltage-controlled delay chain (VCDL), as shown in fig. 8; the phase frequency detector receives an external clock signal and a clock signal fed back by a voltage-controlled delay chain, generates a corresponding output result according to the phase difference of the two clocks, and defines the output result as an UP signal, a DN signal and an inverted signal UP _ B, DN _ B signal, if the phase of a reference clock is ahead of a feedback clock, the UP signal is at a high level, otherwise, the DN signal is at a high level; UP, UP _ B, DN and DN _ B signals are transmitted to a charge pump CP to control the current sink of the charge pump and the turn-off and turn-on of a current source, the output end of the charge pump is connected to a loop filter, the loop filter is only composed of a capacitor, a voltage signal is generated by charging and discharging the capacitor and is input into a voltage-controlled delay chain, the voltage-controlled delay chain generates a plurality of high-frequency clock signals with equal frequency and uniform phase according to the size of input voltage, and finally when the phase of a clock fed back to a phase frequency detector by the voltage-controlled delay chain is the same as that of a reference clock, a stable control voltage Vctrl is output by a delay phase-locked loop.
Compared with the prior art, the invention has the following advantages:
the invention is measured under 640MHz clock, the dynamic range can reach 52 mus, the resolution is about 10 ps. The three-level TDC based on the DLL provided by the invention adopts a hierarchical architecture, and the purpose of compatibility of a measurement range and measurement precision is achieved by hierarchical classification. In the structure adopted by the invention, the first-stage CTDC adopts a Counter architecture which is mainly used for achieving the purpose of high dynamic range, the resolution of the first-stage architecture is lower, and the size of the first-stage architecture depends on the clock period of an adopted clock source; the second-stage MTDC adopts a single delay chain structure, the achievable dynamic range is one clock cycle, and the achievable resolution is limited by gate delay and is not too high; the third-level FTDC adopts a double-delay chain structure, the resolution is the delay difference of the two delay chains, and the limit of gate delay can be broken through; by adopting the three-level architecture, the purposes of being compatible with dynamic range and precision can be achieved, and the area can be saved. In addition, the invention is designed based on the DLL, and provides stable control voltage for a single delay chain of the MTDC and a double delay chain of the FTDC in the TDC through the DLL, so as to achieve the purpose of improving the stability and the accuracy.
Drawings
FIG. 1 is a timing diagram of a DLL based three stage TDC of the present invention;
FIG. 2 is a schematic diagram of a DLL based three stage TDC of the present invention;
FIG. 3 is a schematic illustration of the coarse count of the present invention;
FIG. 4 is a schematic diagram of an intermediate stage count edge detector of the present invention;
FIG. 5 is a schematic illustration of the mid-level counting of the present invention;
FIG. 6 is a schematic diagram of a Fine Edge Detector of the present invention;
FIG. 7 is a schematic diagram of an FTDC of the present invention;
FIG. 8 is a DLL schematic of the present invention;
FIG. 9 is a schematic diagram of a charge pump according to the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Example 1
The embodiment of the invention provides a three-stage TDC based on a DLL (delay locked loop), wherein the DLL is used for providing stable control voltage for a single delay chain of an MTDC (maximum transmission digital converter) and a double delay chain of an FTDC (fiber to the digital converter) in the TDC so as to ensure the TDC can accurately measure the measured time, and finally, a data result of each part of stored circuits is output through a data storage unit, wherein a timing chart is shown in FIG. 1;
the utility model provides a three level TDC based on DLL, includes coarse count (CTDC), intermediate level count (MTDC), thin count (FTDC) and time delay phase-locked loop (DLL), connect through intermediate level count edge Detector (middleledge Detector) between coarse count and the intermediate level count, connect through thin count edge Detector (Fine edge Detector) between intermediate level count and the thin count, time delay phase-locked loop is used for providing control voltage for the voltage-controlled delay chain of intermediate level count and thin count, intermediate level count and intermediate level count decoder (Middle Encoder) are connected, thin count and thin count decoder (Fine Encoder) are connected, and the output of intermediate level count decoder, thin count decoder and thick count all is connected with Data Storage Unit (Data Storage Unit), as shown in FIG. 2. The Coarse counting receives an external clock signal and photon pulse START and STOP signals from the detector, and generates a Coarse counting result Coarse Data; the mid-stage counting edge detector receives an external clock signal and a STOP signal and generates STARTM and STOPM signals; the Middle stage counting receives STARTM and STOPM signals of the Middle stage counting edge detector, generates delay signals D <0:7> and 8-bit thermometer codes M <0:7>, and transmits the 8-bit thermometer codes M <0:7> to the Middle stage counting decoder, and generates a Middle stage counting result Middle Data; the fine counting edge detector receives an STOPM signal of the Middle counting edge detector, a delay signal D <0:7> of the Middle counting and Middle counting result Middle Data to generate STARTF and STOPF signals; the Fine count receives STARTF and STOPF signals of the edge detector, generates a 20-bit thermometer code F <0:19>, transmits the thermometer code F <0:19>, and generates a Fine count result Fine Data; the coarse counting result, the middle-level counting result and the fine counting result are all transmitted to a data storage unit; the delay phase-locked loop receives an external clock signal, generates a control voltage Vctrl and provides the control voltage for the voltage-controlled delay chain of the intermediate-stage counting and the fine counting.
The coarse count is composed of an 8-bi counter, an 8-input AND gate, a 7-bit counter and a flip-flop DFF, as shown in FIG. 3, and is used to count the number of clocks between START and STOP, and the measured time interval is T in FIG. 1CA time period; the 8-bit counter receives the START signal and 640MHz clock signal provided from outside, when the START signal arrives, the 8-bit counter STARTs to count the number of clocks, and 8-bit data Q output by the 8-bit counter<0:7>Transmitting to 8-input AND gate to generate a carry signal CO, inputting the carry signal CO and externally provided RST signal into 7-bit counter, and generating 7-bit output result QC by 7-bit counter<0:6>The number of carry signals CO is represented, and the number of times of the 8-bit counter for completing cycle counting is indicated; the 15-bit data Q<0:7>And QC<0:6>Inputting the result into a trigger DFF, and outputting a corresponding 15-bit result when a STOP signal arrives, namely a Coarse counting result, namely Coarse Data; the dynamic range that the coarse count CTDC can reach is 52 μ s, which is the dynamic range that the whole TDC can reach, the resolution that can reach is the size of the clock period, which is 1.5625ns, and the product of the decimal value corresponding to the coarse count result coarserdata and the resolution is the measured time interval.
The middle stage count edge detector consists of two-input AND gates A1, A2 and a flip-flop DFF, as shown in FIG. 4, receiving the CLK signal and the STOP signal; the CLK _640 signal and the STOP signal are ANDed through a two-input AND gate A1, the generated results S1 and VDD are respectively used as a clock signal and input data to be input into a trigger DFF, the next clock rising edge after the STOP signal arrives is found, a new STOP signal, namely a STOPM signal, is generated, in order to ensure accurate delay, the VDD and the STOP signal are ANDed through a two-input AND gate A2, a new START signal, namely a STARTM signal, is generated, the CLK rising edge can be extracted by the module, the direct delay of the CLK by a rear face is avoided, and power consumption is reduced.
The middle stage count includes voltage controlled delay chain VCDL and triggeredTwo parts of a comparator array formed by DFFs, as shown in FIG. 5, receive STARTM and STOPM signals from an intermediate stage count edge detector, and measure the time interval T in FIG. 1MA time period for processing a residual error of the coarse count; the voltage-controlled delay chain is composed of 8 voltage-controlled delay units, the resolution ratio which can be achieved by MTDC is the delay time of each delay unit, the delay time is 200ps, the STARTM signal is delayed by the delay chain, and a corresponding delay signal D is generated after i (i is 1, 2<i-1>With each time delay cell passes, the comparator array pair D<i-1>And comparing the result with the STOPM signal, finally generating 8-bit thermometer code Data by the comparator array, transmitting the 8-bit thermometer code Data to an intermediate-level counting decoder for transcoding operation, transcoding the 8-bit thermometer code into 3-bit gray code Data, outputting the 3-bit gray code Data as a result of intermediate-level counting, namely Middle Data, wherein the product of a decimal value corresponding to the Middle-level counting result Middle Data and the resolution ratio is the time interval measured by the MTDC.
The fine count edge detector consists of 10 one-out-of-two multiplexers MUX (M0-M9), as shown in FIG. 6, which receives the delay signals D <0:7> from the MTDC, the STOPM signal of the middle level count edge detector, and the middle level count result MiddleData; the said multiplexer M0 receives the STOPM signal of the Middle-stage counting edge detector, the delay signal D <0> of the Middle-stage counting and the output result Middle Data <0>, M1 receives the delay signals D <1> and D <2> of the Middle-stage counting and the output result Middle Data <0> of the Middle-stage counting decoder, M2 receives the delay signals D <3> and D <4> of the Middle-stage counting and the output result Middle Data <0> of the Middle-stage counting decoder, M3 receives the delay signals D <5> and D <6> of the Middle-stage counting and the output result Middle Data <0> of the Middle-stage counting decoder, and then the output result S1 of M0, the output result S2 of M1 and the output result Middle Data <1> of the Middle-stage counting decoder are transmitted to M4, the output result S3 of M2, the output result S4 of M3 and the output result Middle Data <1> of the Middle-stage counting decoder are transmitted to M5, then the output result S5 of M4, the output result S6 of M5 and the output result Middle Data <2> of the Middle-stage counting decoder are transmitted to M6, and the output signal of M6 is a new START signal, namely a STARTF signal; in order to ensure accurate time delay, the multiplexer M7 receives the STOP pm signal and the low GND signal of the middle-stage counting edge detector, the output result S7 and the low GND of M7 are transmitted to M8, the output result S8 and the low GND of M8 are transmitted to M9, and the output signal of M9 is the new STOP signal, i.e., the STOP signal.
The fine count comprises two voltage-controlled delay chains V1, V2 and a comparator array composed of flip-flops DFF, as shown in FIG. 7, which receive STARTF and STOPF signals of the fine count edge detector, and measure a time interval T of FIG. 1FA time period for processing the residual error of the middle stage count. The voltage-controlled delay chain V1 is composed of 20 voltage-controlled delay units (the number of the delay units may also be different according to the FTDC resolution), each delay unit has a delay size τ 1, receives a STARTF signal of the fine count edge detector, and generates a corresponding delay signal DF each time i (i is 1, 2<i-1>(ii) a The voltage-controlled delay chain V2 is also composed of 20 voltage-controlled delay units, each delay unit has a delay value τ 2, receives the STOPF signal of the fine count edge detector, and generates a corresponding delay signal DS each time the signal passes through i (i is 1, 2.., 20) delay units<i-1>(ii) a Using DFF comparator array pairs DF each time a delay element is passed<i-1>And DS<i-1>Comparing to generate 20-bit thermometer code Data, transmitting the 20-bit thermometer code to a Fine counting decoder to transcode the 20-bit thermometer code into 5-bit gray code Data, and outputting the 5-bit gray code Data as a Fine counting result, namely Fine Data; the dynamic range of the Fine counting FTDC is 200ps, the achievable resolution is the delay difference of delay units of two chains, 10ps, the achievable resolution of the Fine counting is the achievable resolution of the whole TDC, and the product of the decimal value corresponding to the Fine counting result Fine Data and the resolution is the measured time interval.
The Delay Locked Loop (DLL) consists of a Phase Frequency Detector (PFD), a Charge Pump (CP) and a voltage controlled delay chain (VCDL), and as shown in fig. 8, provides a control voltage for the voltage controlled delay chain of the middle-stage counting and the fine counting; the phase frequency detector receives two clocks, one is a reference clock provided by an external system clock source, the other is a clock fed back by a voltage-controlled delay chain, the phase frequency detector compares the phases of the two clocks, and generates corresponding UP, DN and inverted signals UP _ B, DN _ B, UP _ B, DN and DN _ B according to the phase difference between the two signals, the UP, UP _ B, DN and DN _ B signals are input into the charge pump, the charge pump adopts a differential structure, as shown in figure 9, the UP, UP _ B, DN and DN _ B signals respectively control the on and off of MP2, MP1, MN1 and MN2 tubes, thereby controlling the on and off of the current sink MN3 and the current source MP3 of the charge pump, the two differential branches of the charge pump are connected through a unity gain amplifier, so that the common mode levels of the two branches are kept the same, thereby stabilizing the output node current of the charge pump, the output node current flows into a loop filter only composed of a capacitor, a voltage signal is generated by charging and discharging a capacitor, the voltage signal is input into a voltage-controlled delay chain, the voltage-controlled delay chain generates a plurality of high-frequency clock signals with equal frequency and uniform phase corresponding to the voltage according to the magnitude of the input voltage, and finally when a clock fed back to the phase frequency detector by the voltage-controlled delay chain is in phase with a reference clock, a delay phase-locked loop outputs a stable control voltage Vctrl.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.

Claims (7)

1. The three-stage TDC based on the DLL is characterized by comprising a coarse counting (CTDC), a middle counting (MTDC), a fine counting (FTDC) and a Delay Locked Loop (DLL), wherein the coarse counting and the middle counting are connected through a middle counting edge detector, the middle counting and the fine counting are connected through a fine counting edge detector, the delay locked loop is used for providing control voltage for a voltage-controlled delay chain of the middle counting and the fine counting, the middle counting is connected with a middle counting decoder, the fine counting is connected with a fine counting decoder, and the outputs of the middle counting decoder, the fine counting decoder and the coarse counting are connected with a data storage unit; the coarse count receives an external clock signal and photon pulse START and STOP signals from the detector, and generates a coarse count result; the mid-stage counting edge detector receives an external clock signal and a STOP signal and generates STARTM and STOPM signals; the middle-stage counting receives STARTM and STOPM signals of the middle-stage counting edge detector to generate a delay signal and a thermometer code, and the thermometer code is transmitted to the middle-stage counting decoder to generate a middle-stage counting result; the fine counting edge detector receives the STOPM signal of the middle counting edge detector, the delay signal D <0:7> of the middle counting and the middle counting result to generate STARTF and STOPF signals; the fine count receives STARTF and STOPF signals of the edge detector of the fine count, generates thermometer codes, transmits the thermometer codes to a fine count decoder, and generates a fine count result; the coarse counting result, the middle-level counting result and the fine counting result are all transmitted to a data storage unit; the delay phase-locked loop receives an external clock signal, generates a control voltage Vctrl and provides the control voltage for the voltage-controlled delay chain of the intermediate-stage counting and the fine counting.
2. The DLL-based three-stage TDC of claim 1, wherein the coarse count is used to calculate the number of clocks between START and STOP, and the measured time interval is TCA time period, i.e., a time interval between a START signal and a STOP signal, which are pulse signals generated by the detector after detecting a photon, and a next clock rising edge; the coarse countThe system is composed of an 8-bit counter, an 8-input AND gate, a 7-bit counter and a trigger (DFF); the 8-bit counter receives a START signal and an externally provided 640MHz clock signal, and an 8-bit output result Q generated by the 8-bit counter<0:7>Transmitting to 8-input AND gate, transmitting to 7-bit counter carry signal CO generated by 8-input AND gate and RST signal provided from outside, and outputting result QC by 7-bit generated by 7-bit counter<0:6>8-bit output result Q generated by 8-bit counter<0:7>And the STOP signal is transmitted to the trigger, and the trigger outputs a Coarse counting result Coarse Data.
3. A DLL based three stage TDC of claim 1, wherein the mid stage count edge detector is configured to generate a new set of START and STOP signals-STARTM and STOPM based on the coarse count for sending to the MTDC for MTDC counting; the middle-stage counting edge detector consists of two 2-input AND gates A1 and A2 and a trigger DFF; the 2-input AND gate A1 receives an external clock signal and a STOP signal, an output signal S1 of the 2-input AND gate and a high-level VDD signal are transmitted to the flip-flop, and an output signal of the flip-flop is a new STOP signal-STOPM signal; the 2-input and gate a2 receives the high VDD and STOP signals and generates a new START signal, the STARTM signal.
4. The DLL based three stage TDC of claim 1, wherein the time interval of the middle stage count measurement is TMThe time period, i.e., the time interval between the STARTM signal and the last delayed signal before the STOPM signal arrives; the middle stage counting comprises a voltage-controlled delay chain (VCDL) and a comparator array consisting of flip-flops, wherein the voltage-controlled delay chain consists of 8 delay units, receives a STARTM signal of the middle stage counting edge detector, and generates a corresponding delay signal D after passing through i (i is 1, 2, 8) delay units<i-1>Delayed signal D<i-1>And the STOPM signal is transmitted to a comparator array, and the comparator array generates 8-bit thermometer code data M<0:7>Transmitting to the middle-stage counting decoder to transcode the 8-bit thermometer code into 3-bit Gray code data to generateThe intermediate stage counts the result.
5. A DLL based three stage TDC of claim 1, wherein the fine count edge detector is configured to generate a new set of START and STOP signals-START f and STOPF-based on the mid-stage count for sending to the FTDC for FTDC counting; the fine count edge detector consists of 10 one-out-of-two multiplexers MUX (M0-M9); the said multiplexer M0 receives the STOPM signal of the Middle-stage counting edge detector, the delay signal D <0> of the Middle-stage counting and the output result Middle Data <0>, M1 receives the delay signals D <1> and D <2> of the Middle-stage counting and the output result Middle Data <0> of the Middle-stage counting decoder, M2 receives the delay signals D <3> and D <4> of the Middle-stage counting and the output result Middle Data <0> of the Middle-stage counting decoder, M3 receives the delay signals D <5> and D <6> of the Middle-stage counting and the output result Middle Data <0> of the Middle-stage counting decoder, and then the output result S1 of M0, the output result S2 of M1 and the output result Middle Data <1> of the Middle-stage counting decoder are transmitted to M4, the output result S3 of M2, the output result S4 of M3 and the output result Middle Data <1> of the Middle-stage counting decoder are transmitted to M5, then the output result S5 of M4, the output result S6 of M5 and the output result Middle Data <2> of the Middle-stage counting decoder are transmitted to M6, and the output signal of M6 is a new START signal, namely a STARTF signal; the multiplexer M7 receives the STOP pm signal and the low level GND signal of the middle-stage counting edge detector, the output result S7 and the low level GND of M7 are transmitted to M8, the output result S8 and the low level GND of M8 are transmitted to M9, and the output signal of M9 is the new STOP signal, i.e., the STOP signal.
6. The DLL based three stage TDC of claim 1, wherein the fine count measurement has a time interval TFThe time period, i.e., the time interval between the STOPM signal and the last delayed signal before the STOPM signal arrives; the fine count comprises two voltage-controlled delay chains and a comparator array composed of flip-flopsColumns; the voltage-controlled delay chain V1 is composed of 20 voltage-controlled delay units, each delay unit has a delay size τ 1, receives a STARTF signal of the fine count edge detector, and generates a corresponding delay signal DF after passing through i (i is 1, 2.., 20) delay units<i-1>(ii) a The voltage-controlled delay chain V2 is also composed of 20 voltage-controlled delay units, each delay unit has a delay value τ 2, receives the STOPF signal of the fine count edge detector, and generates a corresponding delay signal DS each time the signal passes through i (i is 1, 2.., 20) delay units<i-1>(ii) a Time delay signal DF<i-1>And DS<i-1>Transmitted to a comparator array which generates 20-bit thermometer code data F<0:19>And transmitting the data to a fine counting decoder, transcoding the 20-bit thermometer code into 5-bit Gray code data, and generating a fine counting result.
7. The DLL-based three-stage TDC of claim 1, wherein the delay locked loop DLL is configured to provide a control voltage for a voltage-controlled delay chain for middle-stage counting and fine counting, and comprises a Phase Frequency Detector (PFD), a Charge Pump (CP) and a voltage-controlled delay chain (VCDL); the phase frequency detector receives an external clock signal and a clock signal fed back by a voltage-controlled delay chain, generates a corresponding output result according to the phase difference of the two clocks, and defines the output result as an UP signal, a DN signal and an inverted signal UP _ B, DN _ B signal, if the phase of a reference clock is ahead of a feedback clock, the UP signal is at a high level, otherwise, the DN signal is at a high level; UP, UP _ B, DN and DN _ B signals are transmitted to a charge pump CP to control the current sink of the charge pump and the turn-off and turn-on of a current source, the output end of the charge pump is connected to a loop filter, the loop filter is only composed of a capacitor, a voltage signal is generated by charging and discharging the capacitor and is input into a voltage-controlled delay chain, the voltage-controlled delay chain generates a plurality of high-frequency clock signals with equal frequency and uniform phase according to the size of input voltage, and finally when the phase of a clock fed back to a phase frequency detector by the voltage-controlled delay chain is the same as that of a reference clock, a stable control voltage Vctrl is output by a delay phase-locked loop.
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