CN116991227B - Device for acquiring high-precision signals, soC chip and electronic equipment - Google Patents
Device for acquiring high-precision signals, soC chip and electronic equipment Download PDFInfo
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The embodiment of the application provides a device for acquiring high-precision signals, a SoC chip and electronic equipment, wherein the device comprises: the delay calibration unit is configured to determine the total number of delay units corresponding to one clock period in the delay circuit, and obtain the delay time length of each delay unit in the delay circuit according to the total number of delay units and the time length of the one clock period to obtain the delay time length of the delay unit; the delay unit quantity acquisition unit is configured to determine the total quantity of delay units required for acquiring the target high-precision signal according to the delay time length of the delay units, so as to obtain the target delay unit quantity; the high-precision signal acquisition module is configured to delay the input signal by adopting delay units with the number corresponding to the number of the target delay units in the delay circuit so as to obtain the target high-precision signal. The embodiment of the application uses the low-frequency clock to generate the high-precision signal, thereby effectively saving the dynamic power consumption of the chip.
Description
Technical Field
The present invention relates to the field of signal processing, and in particular, to a device for acquiring a high-precision signal, an SoC chip, and an electronic device.
Background
In chip design, a method that is generally used in the prior art for improving the precision of digital circuit design is to use a method of generating a high-frequency clock by using a phase-locked loop PLL (Phase Locked Loop) to design and implement a higher precision digital circuit, however, the method of generating a high-precision clock signal by using a PLL phase-locked loop has the following defects:
first, the design cost is increased by employing a design in which a PLL generates a clock of a higher frequency. By adding the analog PLL module, the clock design with higher precision is realized, so that the labor cost for designing the front end and the back end of the analog PLL is increased, and the area cost of the chip is increased.
Secondly, by adopting a mode of lifting the clock frequency by the PLL, the clock frequency in the digital circuit is lifted, and the period of the clock is reduced. This requires that the register-to-register path delay become more critical, making the chip more difficult to implement in design. In addition, under certain low-performance processes, due to the characteristics of the device, the time sequence of the circuit is difficult to meet, so that the functions cannot be realized.
Finally, using a high frequency PLL to place the operating clock of the chip in a higher frequency operating state increases the dynamic power consumption of the chip.
Disclosure of Invention
An object of the embodiment of the application is to provide a device for obtaining a high-precision signal, an SoC chip and an electronic device, by which the embodiment of the application does not generate a high-frequency clock when generating the high-precision signal, and the embodiment of the application uses a low-frequency clock to design a circuit for realizing higher precision, so that the dynamic power consumption of the chip is effectively saved, that is to say, the high-frequency clock in the whole system can be avoided when the high-precision signal is generated by the technical scheme of some embodiments of the application, and the power consumption of the chip is reduced.
In a first aspect, an embodiment of the present application provides an apparatus for acquiring a high-precision signal, where the apparatus includes: the delay calibration unit is configured to determine the total number of delay units corresponding to one clock period in the delay circuit, and obtain the delay time length of each delay unit in the delay circuit according to the total number of delay units and the time length of the one clock period to obtain the delay time length of the delay unit, wherein the delay circuit comprises a plurality of delay units connected in series; the delay unit quantity acquisition unit is configured to determine the total quantity of delay units required for acquiring the target high-precision signal according to the delay time length of the delay units, so as to obtain the target delay unit quantity; the high-precision signal acquisition module is configured to delay the input signal by adopting delay units with the number corresponding to the number of the target delay units in the delay circuit so as to obtain the target high-precision signal.
According to the embodiment of the application, the corresponding high-precision signal is obtained based on the delay circuit formed by the plurality of delay units according to the precision requirement of the target high-precision signal, and it is easy to understand that the technical scheme of some embodiments of the application can avoid the high-frequency clock in the whole system while generating the high-precision signal, so that the power consumption of the chip is reduced.
In some embodiments, the delay calibration unit further comprises: a delay control information acquisition unit configured to provide delay control information; the delay calibration circuit comprises a delay circuit, a first register and a second register, and is configured to obtain and provide information stored in the first register and the second register according to the delay control information, wherein the first register is used for storing a first signal value obtained by sampling from an output end of an i-th delay unit in the delay circuit, and the second register is used for storing a second signal value obtained by sampling from an output end of an i+j-th delay unit in the delay circuit, and both i and j are integers larger than zero; and a delay calculation unit configured to determine a total number of delay units corresponding to the one clock cycle through a plurality of cycles and according to the first signal value and the second signal value.
According to some embodiments of the method and the device, the total number of delay units corresponding to one clock cycle is accurately determined through multiple cycles, the number of delay units needed correspondingly can be determined according to the duration of the clock cycle, and then the delay corresponding to one delay unit is obtained by dividing the total number of delay units corresponding to one clock cycle by the duration of one clock cycle.
In some embodiments, the delay control information comprises: a delay unit starting point and a delay calculation phase difference; in the first cycle, the number j of the delay units at intervals between the ith delay unit and the ith+j delay unit is equal to the delay calculated phase difference; and in the first cycle, taking the starting point of the delay unit as the initial value of the ith delay unit.
Some embodiments of the present application determine the total number of delay cells corresponding to one clock cycle by designing two delay control information.
In some embodiments, the delay computation unit is configured to: in the kth cycle, if the values of the first signal value and the second signal value are both confirmed to be 0, performing self-increasing operation on the value of i and performing self-increasing operation on the value of i+j to obtain the value of i and the value of i+j in the kth+1 cycle, wherein k is an integer greater than or equal to 1; in the kth cycle, if the first signal value and the second signal value are both 1, performing a self-subtraction operation on the value of i and performing a self-subtraction operation on the value of i+j to obtain the value of i and the value of i+j in the kth+1 cycle, wherein k is an integer greater than or equal to 1; repeating the steps until the acquired first signal value is 1 and the acquired second signal value is 0, and calculating the total number of delay units corresponding to the clock period.
According to some embodiments of the method and the device, the specific positions of the delay registers for acquiring the signal values stored in the two registers next time are determined according to the first signal value and the second signal value, so that the total number of delay units corresponding to one clock period can be found finally through repeated adjustment, the delay time length of one delay unit can be determined, and the needed high-precision signals can be realized by adopting the plurality of delay units.
In some embodiments, the calculation formula of the total number of delay units corresponding to one clock cycle is:
step= x+ (phase_sel/2)
wherein step represents the total number of delay units corresponding to one clock cycle, x represents the value of i corresponding to the first signal value being 1 and the second signal value being zero, and phase_sel represents the delay calculation phase difference corresponding to the first signal value being 1 and the second signal value being zero.
Some embodiments of the present application determine the total number of delay units corresponding to one clock cycle through the above calculation formula.
In some embodiments, the delay unit number obtaining unit is configured to calculate each rising edge delay and each falling edge delay to obtain the target delay unit number according to a high-precision control parameter and the delay time length of the delay unit.
Some embodiments of the present application implement high-precision designs by controlling parameters and the delay time length of the delay unit with high precision and using rising edge delay or falling edge delay.
In some embodiments, the high precision control parameters include: at least one of period, duty cycle, and phase.
Some embodiments of the present application may adjust the period, duty cycle, and phase of the signal to obtain a variety of desired target high precision signals.
In some embodiments, the high precision signal acquisition module comprises: the delay circuit is configured to delay the input signal by adopting delay units with the number equal to that of the target delay units in the delay circuit, so as to obtain a delay signal; and the logic operation module is configured to perform logic operation on the delay signal and the input signal to obtain the target high-precision signal.
According to the embodiment of the application, various high-precision signals can be realized under the low-frequency condition through the delay circuit and the logic processing circuit after delay calibration, and the power consumption for generating the high-precision signals is effectively reduced.
In a second aspect, some embodiments of the present application provide a method for acquiring a high-precision signal, which is applied to the apparatus of the first aspect, where the method includes: starting a delay calibration unit, obtaining the number of delay units corresponding to one clock period through the delay calibration unit, and calculating the delay time of one delay unit according to the clock frequency and the number of the delay units to obtain the delay time of the delay unit; calculating the time required to delay each rising edge and/or falling edge according to the total delay time and the delay time of the delay units, and determining the number of the required delay units according to the time to obtain the number of target delay units; and selecting a corresponding number of delay units from the delay circuit according to the number of the target delay units, and carrying out delay processing on an input signal to obtain a target high-precision signal.
In a third aspect, some embodiments of the present application provide a SoC chip including an apparatus as described in any of the embodiments of the first aspect.
In a fourth aspect, some embodiments of the present application provide an electronic device comprising a SoC chip as set forth in the third aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is one of the block diagrams of an apparatus for acquiring a high-precision signal according to an embodiment of the present application;
FIG. 2 is a second block diagram of an apparatus for acquiring high precision signals according to an embodiment of the present application;
fig. 3 is a block diagram of a delay calibration unit and an input/output signal schematic diagram according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a delay calibration circuit according to an embodiment of the present disclosure;
fig. 5 is a block diagram of a delay unit number acquisition unit according to an embodiment of the present application;
fig. 6 is a schematic diagram of a high-precision signal acquisition module according to an embodiment of the present application;
FIG. 7 is a timing diagram for generating a first target high precision signal according to an embodiment of the present application;
fig. 8 is a timing chart of generating a second target high-precision signal according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
Some embodiments of the present application provide a device for high precision signal and a method implemented based on the device, where the device includes a delay calibration unit, a delay unit number acquisition unit, and a high precision signal acquisition module, where the delay calibration unit mainly completes calculation and dynamic adjustment of a step size of the delay unit (that is, determines a delay time length of each delay unit) (for example, when a temperature rises or an environment changes, a delay time of the delay unit becomes longer or shorter, and at this time, the delay calibration unit updates a step value according to an actual situation), the delay unit number acquisition unit completes calculation of high precision delay according to a high precision control parameter, and the high precision signal acquisition module completes high precision processing of an input signal according to a total number of delay units required by the delay unit in the delay calibration unit and the delay unit number acquisition unit, so as to obtain a high precision signal.
Compared with the existing scheme of using the PLL in the high-precision design, the three functional units are added, so that dependence on the PLL can be reduced, design frequency of the PLL can be reduced, or the design of a high-precision circuit can be realized without using the PLL. Embodiments of the present application use this design approach to avoid the use of PLLs in certain SoC chip (also known as system-on-chip or system-on-a-chip) designs, reducing the chip area. Some embodiments of the present application may reduce power consumption of the chip, as well as reduce the cost of the entire chip production. For example, if a clock using a PLL of the related art generates a high-precision duty signal, the minimum clock frequency required is f=1/t_delay=2 GHz, and such a high-frequency clock is extremely high in process requirements as a master clock in the SoC, which increases production costs and also causes a drastic increase in dynamic power consumption of the chip. Different from a related method, when the embodiment of the application is adopted to realize the high-precision duty ratio signal, the clock frequency can be reduced to 100MHz or even 10MHz, and the design difficulty, the power consumption and the cost are greatly reduced when the high-precision duty ratio signal is obtained.
Fig. 1 is a device for acquiring a high-precision signal according to an embodiment of the present application.
As shown in fig. 1, an embodiment of the present application provides an apparatus for acquiring a high-precision signal, where the apparatus includes: delay calibration unit 110, delay unit number acquisition unit 120, and high-precision signal acquisition module 130.
The delay calibration unit 110 is configured to determine a total number of delay units corresponding to one clock cycle in a delay circuit, and obtain a delay time length of each delay unit in the delay circuit according to the total number of delay units and a time length of the one clock cycle, so as to obtain a delay time length of the delay unit, wherein the delay circuit comprises a plurality of delay units connected in series.
And the delay unit number acquisition unit 120 is configured to determine the total number of delay units required for acquiring the target high-precision signal according to the delay time length of the delay units, so as to obtain the target delay unit number.
The high-precision signal acquisition module 130 is configured to perform delay processing on an input signal by adopting delay units with the number corresponding to the number of the target delay units in the delay circuit, so as to obtain the target high-precision signal.
It is easy to understand that the embodiment of the application obtains the corresponding high-precision signal through the delay circuit formed by the plurality of delay units according to the precision requirement of the target high-precision signal, and it is easy to understand that the technical solutions of some embodiments of the application can avoid the high-frequency clock in the whole system while generating the high-precision signal, and reduce the power consumption of the chip.
The modules or units of fig. 1 are exemplarily described below.
As shown in fig. 2, in some embodiments of the present application, the delay calibration unit 110 further includes: the delay control information acquisition unit, the delay calibration circuit and the delay calculation unit.
And a delay control information acquisition unit configured to provide delay control information.
The delay calibration circuit comprises a delay circuit, a first register and a second register, and is configured to obtain and provide information stored in the first register and the second register according to delay control information, wherein the first register is used for storing a first signal value obtained by sampling from an output end of an i-th delay unit in the delay circuit, and the second register is used for storing a second signal value obtained by sampling from an output end of an i+j-th delay unit in the delay circuit, and i and j are integers larger than zero.
And a delay calculation unit configured to determine a total number of delay units corresponding to the one clock cycle through a plurality of cycles and according to the first signal value and the second signal value.
It is to be understood that in some embodiments of the present application, the total number of delay units corresponding to one clock cycle is precisely determined in multiple cycles, so that the number of delay units corresponding to the need can be determined according to the duration of the clock cycle, and further, the delay corresponding to one delay unit is obtained by dividing the total number of delay units corresponding to one clock cycle by the duration of one clock cycle.
Some embodiments of the present application provide input signals and output signals of the delay calibration unit 110 as exemplarily described below in connection with fig. 3.
It should be noted that, in some embodiments of the present application, the delay control information includes: a starting point of the delay unit and a delay calculated phase difference (the delay calculated phase difference sets an initial value, if the initial value cannot be locked, the phase difference is increased to be circulated once again, namely, corresponding adjustment is carried out when normal locking cannot be carried out); in the first cycle, the number j of the delay units at intervals between the ith delay unit and the ith+j delay unit is equal to the delay calculated phase difference; and in the first cycle, taking the starting point of the delay unit as the initial value of the ith delay unit. Some embodiments of the present application determine the total number of delay cells corresponding to one clock cycle by designing two delay control information. The delay calculation phase difference is default to a phase difference value at the beginning, and the phase difference value is minimum to 1, namely j is 1 larger than i.
As shown in fig. 3, the signals input to and output from the delay calibration unit 110 include:
clock: the clock (one cycle of the clock, i.e., one clock cycle) is input.
rst_n, reset signal.
start_en, delay calibration enabled.
phase_sel [ n:0]: phase selection (or delay-computed phase difference), where n belongs to a data signal of multi-bit width such as: n=1, 2,3.
start_point [ n:0]: delay element start point (or delay element start point).
step [ n:0]: the number of delay elements required for one clock cycle.
status [1:0]: time delay calibration state.
In some embodiments of the present application, the delay calibration unit is specifically implemented as follows:
first, a specific logic unit is selected to form a delay unit, such as: two NOT devices are selected as one to form a delay unit, namely, two NOT devices are connected in series to form the delay unit. And serially connecting a plurality of delay units to form a multi-stage delay circuit.
Secondly, the path delay of each delay unit needs to be adjusted to be consistent when the chip layout and wiring design is carried out, namely the delay of the signal passing through each delay unit is the same.
Again, the delay cell start point of the delay circuit is selected and the phase difference is calculated by delay according to the delay control information (as the number of delay cell differences for detecting phase lock, i.e. the number of delay cell intervals in clock_dx and clock_ds in fig. 4).
In some embodiments of the present application, the process of calculating the number of delay units needed for one clock cycle (i.e., the number of delay units step corresponding to one clock cycle) includes:
as shown in fig. 4, clock is passed through a delay circuit, wherein the phase difference between clock_dx (as the first signal value stored in the first register) and clock_ds (as the second signal value stored in the second register) is phase_sel, i.e. the number of delay units that clock_ds passes over compared to clock_dx, the difference between dx and ds being adjustable.
When start_en is enabled, calibration of the delay unit is started, and calibration is started from the start_point, that is, the start point of clock_dx is the start_point (x) th delay unit. The starting point of clock_ds is the start_point+phase_sel delay unit. For example, if start_point is 5 and phase_sel=2, the clock_dx position is the output of the 5 th delay cell and the clock_ds is the output of the 7 th delay cell.
The clock is used for sampling signals at the output ends of the corresponding delay units respectively to obtain a first signal value clock dx and a second signal value clock ds of fig. 4, sampling values are correspondingly latched into a first register r_clock dx and a second register r_clock ds of fig. 4, and if two sampling values r_clock dx (serving as a first signal value) and r_clock ds (serving as a second signal value corresponding to the first signal value) are both 0, the positions of the two sampled delay units are shifted to the right by one delay unit. It can be understood that, in the next cycle, the first signal value clock_dx acquired is at the output end of the start_point+1 delay unit, and the second signal value clock_ds acquired by the sampling unit is at the output end of the start_point+phase_sel+1 delay unit. If the values of the two signals are sampled, the two delay units to be sampled at this time need to be shifted to the left by one delay unit at the same time if both values are 1.
Repeating the above steps until the first signal value r_clock_dx=1 obtained by sampling and the second signal value r_clock_ds=0 obtained by sampling are found, stopping the calibration, setting status to 1, and marking as a locking state. At this time, the number of delay units passing through the sampling point of the first signal value, namely the number x of delay units where clock_dx is located, is recorded, and at this time, the total number of delay units corresponding to one clock period is: step=x+ (phase_sel/2). That is, if the position where clock_dx is located is 49 th cell of the delay circuit, phase_sel=2, and step=50 at this time.
The first delay unit d1, the second delay unit d2, the third delay unit d3, the fourth delay unit d4, the fifth delay unit d5, the xth delay unit dx, the s-th delay unit ds and the n-th delay unit dn in fig. 4 are respectively one delay unit in a delay circuit, and fig. 4 further comprises two registers, namely a first register and a second register, which are respectively used for storing a first signal value and a second signal value obtained by each cycle.
That is, in some embodiments of the present application, the delay calculation unit is configured to: in the kth cycle, if the values of the first signal value r_clock_dx and the second signal value r_clock_ds are confirmed to be 0, performing self-increasing operation on the value of i and performing self-increasing operation on the value of i+j to obtain the value of i and the value of i+j in the kth+1 cycle, wherein k is an integer greater than or equal to 1; in the kth cycle, if the first signal value and the second signal value are both 1, performing a self-subtraction operation on the value of i and performing a self-subtraction operation on the value of i+j to obtain the value of i and the value of i+j in the kth+1 cycle, wherein k is an integer greater than or equal to 1; repeating the steps until the acquired first signal value is 1 and the acquired second signal value is 0, and calculating the total number of delay units corresponding to the clock period. It is to be understood that, in some embodiments of the present application, the specific positions of the delay units that collect the signal values stored in the two registers next time are determined according to the magnitudes of the first signal value and the second signal value, and then the total number of delay units corresponding to one clock period can be found finally by repeatedly adjusting the positions of the sampled delay units in the delay circuit, so that the delay time of one delay unit can be determined, and further the required high-precision signal can be realized by adopting such a plurality of delay units.
That is, in some embodiments of the present application, the calculation formula of the total number of delay units corresponding to one clock cycle is:
step= x+ (phase_sel/2)
wherein step represents the total number of delay units corresponding to one clock cycle, x represents the value of i corresponding to the first signal value being 1 and the second signal value being zero, and phase_sel represents the delay calculation phase difference corresponding to the first signal value being 1 and the second signal value being zero. Some embodiments of the present application determine the total number of delay units corresponding to one clock cycle through the above calculation formula.
The delay unit number obtaining unit provided in some embodiments of the present application is exemplarily described below with reference to fig. 5.
It should be noted that, in some embodiments of the present application, the delay unit number obtaining unit is configured to calculate, according to a high-precision control parameter and the delay time length of the delay unit, each rising edge delay and each falling edge delay to obtain the target delay unit number. For example, in some embodiments, the high precision control parameters include: at least one of period, duty cycle, and phase.
It will be appreciated that some embodiments of the present application achieve high precision designs by controlling parameters and the delay time length of the delay unit with high precision and using rising edge delays or falling edge delays. Some embodiments of the present application may adjust the period, duty cycle, and phase of the signal to obtain a variety of desired target high precision signals.
As shown in fig. 5, the delay unit number obtaining unit in some embodiments of the present application includes two selectors that are alternatively selected and a calculating unit, and the corresponding input signals and output signals are respectively:
step, the number of delay units needed for one clock cycle (the value comes from the delay calibration unit).
rise_delay_cnt number of rising edge delays
fall_delay_cnt, number of falling edge delays
bypass function, when 1, the rising edge delay and falling edge delay of the output are selected by the selector of fig. 5 by using the input rise_delay_cnt and fall_delay_cnt.
High-precision control parameters: including periodic_ctrl, duty_ctrl, phase_ctrl, etc.
period_ctrl including normal period configuration period, high precision period period_hr portion
duty_ctrl including a normal period configuration duty, high precision duty_hr portion
phase_ctrl phase adjustment configuration phase, high precision phase_hr.
The operation of the corresponding unit of fig. 5 is described below.
When using the bypass function of fig. 5, the rise_delay_cnt and fall_delay_cnt directly use the input values; when bypass is not bypassed, the rise delay and the fall delay are calculated separately using high precision parameters.
The high-precision control parameters include, but are not limited to, processing related to the period, duty cycle, phase and common delay of the signal (such as the period module, the vacuum ratio module, the phase module and other modules included in the calculating unit in fig. 5), and the calculating unit in fig. 5 calculates, according to different high-precision control parameters, a corresponding output signal rise_cnt (the number of delay units required to pass through by the rising edge) and a fall_cnt (the number of delay units required to pass through by the falling edge).
For example, a system period T clk For 100Mhz, step=100, the duty cycle of the signal is adjusted, and a duty cycle signal having a duty cycle of 50% for a signal having a period of 100ns is adjusted to a signal having a duty cycle of 50.5%. With embodiments of the present application, delay event Δt=t for each delay cell clk The high level of the periodic signal of 100ns with the duty ratio of 50.5% is 50.5ns, and the falling edge delay time fall_delay_cnt=5 is only needed to be adjusted at the moment.
First, the following information is configured on the system: period=t pulse /T clk =100 ns/10 ns=10, duty=50.5% ×period=0.505×10=5.05 rounded up to 5, duty_hr (assuming register configuration bit width is assumed to be 8 bits, i.e. duty [ 7:0:0 ]]) The configuration value of duty_hr needs to be 0.05 cycles=0.05×2 8 =12.8 (rounded) =13, duty_hr [ n:0]The configuration value should be a decimal part.
Next, the automatic calculation mode (i.e., the following process is performed by the calculation unit of fig. 5):
the number of the falling edge time delay units is as follows: duty_hr/2 n ×step = 13/256×100=5
When the environment changes, for example, when step becomes 200, that is, the delay of each delay cell becomes 0.05ns, the number of delay cells required is:
duty_hr/2 n ×step = 13/256×200=10
the system automatically updates the corresponding information according to the change of the environment.
That is, the specific implementation procedure of the delay unit number acquisition unit in some embodiments of the present application is as follows: when using bypass function, the base_delay_cnt and the fall_delay_cnt directly use the inputted values. When bypass is not used, the rise delay and the fall delay are calculated respectively by using high-precision parameters.
The high precision control parameters of some embodiments of the present application include, but are not limited to, correlating the period, duty cycle, phase, and general delay of the signal. Such as: when clock is 100Mhz, step=100, the duty ratio of the signal is adjusted, and the duty ratio of the signal with one period of 100ns is adjusted to the signal with 50% duty ratio of 50.5%. The delay event Δt=tclock/step=0.1 ns for each delay cell at this time, and the high level of the periodic signal of 100ns with a duty cycle of 50.5% is 50.5ns. At this time, only the falling edge delay time fall_delay_cnt=5 needs to be adjusted.
The structure of the high-precision signal acquisition module is exemplarily described below in conjunction with fig. 6 and 7.
As shown in fig. 6, the high-precision signal acquisition module includes a delay circuit, which is the same as the delay circuit calibrated in fig. 4, and a logic operation module, the input signal in fig. 6 includes the output signal in fig. 5 and the input signal, and the output signal output at the output end in fig. 6 is characterized as o_signal.
The high-precision signal acquisition module of fig. 6 contains a delay circuit which is identical to the delay calibration unit, and the delay information of each unit is identical to the delay information of the delay calibration unit.
The high-precision signal acquisition module of fig. 6 carries out delay processing on the input signal by respectively carrying out rising edge and falling edge on the signal through the delay circuit of fig. 6, outputs the delayed output signal to the logic operation module for processing, and then outputs the finally required signal according to the requirement to obtain the target high-precision signal.
As shown in fig. 7, in the high-precision signal acquisition module, when the required falling edge delay is calculated to be 5 delay units, the input signal i_signal outputs a signal_delay signal after a delay of t_delay=5Δt=0.5 ns. Since the falling edge is delayed, the falling edge needs to be added with a delay time, that is, the output o_signal is one of the input signal i_signal and the delay signal siginal_delay of fig. 7, and the waveform is specifically shown in fig. 7.
That is, the workflow of the apparatus for acquiring a high-precision signal as shown in fig. 1 according to some embodiments of the present application includes:
firstly, starting a delay calibration unit to calculate step (namely the number of delay units needed by one clock cycle), so that the delay time of one delay unit can be calculated according to the frequency of the clock (the embodiment of the application can realize high-precision signal output through the delay unit), and the method is characterized by the following formula:
Δt= T clk /step
wherein Δt is used to characterize the time of the delay of each delay element (i.e., delay element delay duration), T clk Characterizing the duration of one clock cycle, step is used to characterize the total number of delay elements corresponding to one clock cycle (the value of step is obtained by means of the precise calibration of some embodiments of the present application).
And secondly, calculating the time for which the rising edge and the falling edge of the signal need to be delayed according to design requirements, and configuring a delay register through hardware automatic calculation or software calculation.
For example, the system period is 10ns, Δt=1 ns (i.e., step=10), and a certain signal needs to be configured to be 2 when a delay of 2ns is required.
Finally, the high-precision signal acquisition module according to fig. 6 performs delay processing and logic operation on the input signal to be processed to obtain the target high-precision signal.
That is, in some embodiments of the present application, the high-precision signal acquisition module includes: the delay circuit is configured to delay the input signal by adopting delay units with the number equal to that of the target delay units in the delay circuit, so as to obtain a delay signal; and the logic operation module is configured to perform logic operation on the delay signal and the input signal to obtain the target high-precision signal.
The operation of the apparatus of fig. 1 is described below taking the acquisition of a high precision periodic signal as an example, for example, a signal with a period of 100ns (i.e., one example of an input signal) is adjusted to a signal with a period of 101ns (i.e., one example of a target high precision signal). First, the delay step of the delay unit is calibrated by the delay calibration unit (e.g. step=100 at 100MHz clock, i.e. each step delay is 0.1 ns), and the rising edge and the falling edge need to be delayed respectively. In fig. 8, the 1 st falling edge is delayed for 5 unit time (i.e. t_delay=5Δt), the 2 nd rising edge update delay value is 10 unit time (i.e. t_delay=10Δt), the 2 nd falling edge delay update delay value is 15 delay units (i.e. t_delay=15Δt), and so on, and finally the required output o_signal signal with high precision period is generated, as shown in fig. 8.
According to the embodiment of the application, various high-precision signals can be realized under the low-frequency condition through the delay circuit and the logic processing circuit after delay calibration, and the power consumption for generating the high-precision signals is effectively reduced.
Some embodiments of the present application provide a method for acquiring a high-precision signal, which is applied to an apparatus for acquiring a high-precision signal as described above, and the method includes: starting a delay calibration unit, obtaining the number of delay units corresponding to one clock period through the delay calibration unit, and calculating the delay time of one delay unit according to the clock frequency and the number of the delay units to obtain the delay time of the delay unit; calculating the time required to delay each rising edge and/or falling edge according to the total delay time and the delay time of the delay units, and determining the number of the required delay units according to the time; and selecting a corresponding number of delay units from the delay circuits according to the number of the delay units required, and carrying out delay processing on an input signal to obtain a target high-precision signal.
Some embodiments of the present application provide a SoC chip including an apparatus as described in the above embodiments.
Some embodiments of the present application provide an electronic device including a SoC chip as described above.
It should be noted that the delay unit of some embodiments of the present application may be implemented using different types of logic units of a process library, for example, one or more of different types of gates such as and gate, or gate, not gate, buffer (buffer) and so on may be used to form a delay unit. When the delay unit number obtaining unit of some embodiments of the present application performs delay calculation, the period, duty cycle, and phase of the signal may be combined to calculate the corresponding delay. Some embodiments of the present application implement high-precision designs using only rising edge delays or falling edge delays, and some embodiments of the present application incorporate high-precision computing units and signal processing units to implement signal processing.
Reference may be made to the foregoing description for specific structures of the electronic device or the Soc chip, and redundant descriptions and descriptions are not repeated here.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (7)
1. An apparatus for acquiring a high precision signal, the apparatus comprising:
the delay calibration unit is configured to determine the total number of delay units corresponding to one clock period in the delay circuit, and obtain the delay time length of each delay unit in the delay circuit according to the total number of delay units and the time length of the one clock period to obtain the delay time length of the delay unit, wherein the delay circuit comprises a plurality of delay units connected in series;
the delay unit quantity acquisition unit is configured to determine the total quantity of delay units required for acquiring the target high-precision signal according to the delay time length of the delay units, so as to obtain the target delay unit quantity;
the high-precision signal acquisition module is configured to delay the input signal by adopting delay units with the number corresponding to the number of the target delay units in the delay circuit so as to acquire the target high-precision signal; wherein,
the delay calibration unit further comprises:
a delay control information acquisition unit configured to provide delay control information, wherein,
the delay calibration circuit comprises a delay circuit, a first register and a second register, and is configured to obtain and provide information stored in the first register and the second register according to the delay control information, wherein the first register is used for storing a first signal value obtained by sampling from an output end of an i-th delay unit in the delay circuit, and the second register is used for storing a second signal value obtained by sampling from an output end of an i+j-th delay unit in the delay circuit, and both i and j are integers larger than zero;
a delay calculation unit configured to determine a total number of delay units corresponding to the one clock cycle by a plurality of cycles and according to the first signal value and the second signal value;
the delay control information includes: a delay unit starting point and a delay calculation phase difference;
in the first cycle, the number j of the delay units at intervals between the ith delay unit and the ith+j delay unit is equal to the delay calculated phase difference;
in the first cycle, taking the starting point of the delay unit as the initial value of the ith delay unit;
the delay computation unit is further configured to:
in the kth cycle, if the values of the first signal value and the second signal value are both confirmed to be 0, performing self-increasing operation on the value of i and performing self-increasing operation on the value of i+j to obtain the value of i and the value of i+j in the kth+1 cycle, wherein k is an integer greater than or equal to 1;
in the kth cycle, if the first signal value and the second signal value are both 1, performing a self-subtraction operation on the value of i and performing a self-subtraction operation on the value of i+j to obtain the value of i and the value of i+j in the kth+1 cycle, wherein k is an integer greater than or equal to 1;
repeating the steps until the first signal value acquired is 1 and the second signal value acquired is 0, and calculating the total number of delay units corresponding to the clock period;
the delay calibration unit is configured to:
passing a clock through the delay circuit;
when enabling the start_en, starting calibration of the delay units, starting calibration from a start_point, taking the starting point of the clock_dx as a start_point (x) th delay unit and taking the starting point of the clock_ds as a start_point+phase_sel th delay unit;
sampling signals at the output ends of the corresponding delay units by using a clock to obtain a first signal value clock dx and a second signal value clock ds, correspondingly latching sampling values into the first register r_clock dx and the second register r_clock ds, and shifting the positions of the two sampled delay units to the right by one delay unit if the first signal value r_clock dx and the second signal value r_clock ds are 0; in the next cycle, the acquired first signal value clock_dx is at the output end of the start_point+1 delay unit, the sampled second signal value clock_ds is at the output end of the start_point+phase_sel+1 delay unit, and if the values of the two signals are 1, the two delay units to be sampled need to be simultaneously moved to the left by one delay unit; repeating the steps until the first signal value r_clock_dx=1 obtained by sampling is found and the second signal value r_clock_ds=0 obtained by sampling is found, stopping calibration, setting status as 1, and marking as a locking state; at this time, the number of delay units passing through the sampling point of the first signal value, namely the number x of delay units where clock_dx is located, is recorded, and at this time, the total number of delay units corresponding to one clock period is: step=x+ (phase_sel/2), where step represents the total number of delay cells corresponding to one clock cycle, x represents the value of i corresponding to when the first signal value is 1 and the second signal value is zero, and phase_sel represents the delay calculation phase difference corresponding to when the first signal value is 1 and the second signal value is zero.
2. The apparatus of claim 1, wherein the delay element number acquisition unit is configured to calculate each rising edge delay and each falling edge delay to obtain the target delay element number based on a high-precision control parameter and the delay element delay duration, respectively.
3. The apparatus of claim 2, wherein the high precision control parameters comprise: at least one of period, duty cycle, and phase.
4. The apparatus of claim 1, wherein the high precision signal acquisition module comprises:
the delay circuit is configured to delay the input signal by adopting delay units with the number equal to that of the target delay units in the delay circuit, so as to obtain a delay signal;
and the logic operation module is configured to perform logic operation on the delay signal and the input signal to obtain the target high-precision signal.
5. A method of acquiring a high precision signal for use in the apparatus of any of claims 1-4, the method comprising:
starting a delay calibration unit, obtaining the number of delay units corresponding to one clock period through the delay calibration unit, and calculating the delay time of one delay unit according to the clock frequency and the number of the delay units to obtain the delay time of the delay unit;
calculating the time required to delay each rising edge and/or falling edge according to the total delay time and the delay time of the delay units, and determining the number of the required delay units according to the time to obtain the number of target delay units;
and selecting a corresponding number of delay units from the delay circuit according to the number of the target delay units, and carrying out delay processing on an input signal to obtain a target high-precision signal.
6. A SoC chip comprising the apparatus of any of claims 1-4.
7. An electronic device comprising the SoC chip of claim 6.
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