CN111598727A - Method for improving metering clock synchronization of intelligent substation based on code phase counting method - Google Patents
Method for improving metering clock synchronization of intelligent substation based on code phase counting method Download PDFInfo
- Publication number
- CN111598727A CN111598727A CN202010716001.1A CN202010716001A CN111598727A CN 111598727 A CN111598727 A CN 111598727A CN 202010716001 A CN202010716001 A CN 202010716001A CN 111598727 A CN111598727 A CN 111598727A
- Authority
- CN
- China
- Prior art keywords
- clock
- frequency
- phase
- module
- counting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000005259 measurement Methods 0.000 claims abstract description 44
- 239000013078 crystal Substances 0.000 claims abstract description 40
- 238000012937 correction Methods 0.000 claims abstract description 34
- 238000012545 processing Methods 0.000 claims description 23
- 230000000630 rising effect Effects 0.000 claims description 18
- 238000005070 sampling Methods 0.000 claims description 10
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 230000007774 longterm Effects 0.000 claims description 5
- 101100464927 Bacillus subtilis (strain 168) ppsB gene Proteins 0.000 claims description 4
- 238000004364 calculation method Methods 0.000 claims description 4
- 238000000691 measurement method Methods 0.000 claims description 4
- 101100137463 Bacillus subtilis (strain 168) ppsA gene Proteins 0.000 claims description 3
- 101100342406 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) PRS1 gene Proteins 0.000 claims description 3
- 239000000284 extract Substances 0.000 claims description 3
- 101150056693 pps1 gene Proteins 0.000 claims description 3
- 238000001308 synthesis method Methods 0.000 claims description 3
- 238000011156 evaluation Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000003786 synthesis reaction Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000012356 Product development Methods 0.000 abstract 1
- 230000010355 oscillation Effects 0.000 abstract 1
- 238000013461 design Methods 0.000 description 10
- 230000005540 biological transmission Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q50/00—Information and communication technology [ICT] specially adapted for implementation of business processes of specific business sectors, e.g. utilities or tourism
- G06Q50/06—Energy or water supply
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
Landscapes
- Business, Economics & Management (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Economics (AREA)
- Strategic Management (AREA)
- General Business, Economics & Management (AREA)
- General Health & Medical Sciences (AREA)
- Human Resources & Organizations (AREA)
- Marketing (AREA)
- Primary Health Care (AREA)
- Public Health (AREA)
- Tourism & Hospitality (AREA)
- Physics & Mathematics (AREA)
- Water Supply & Treatment (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Electric Clocks (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
Abstract
The invention provides a method for improving the synchronization of a metering clock of an intelligent substation based on a code phase counting method. The frequency deviation of the crystal oscillator clock adopts direct frequency measurement and frequency synthesis technology, divides frequency signals into oscillations with different frequency components according to a certain frequency point standard, identifies high-frequency noise components, calculates frequency control words according to the acquired output frequency and the counter value, realizes multipath frequency division by the frequency control words, identifies and filters frequency errors, achieves the effect of calibrating the clock frequency, and solves the problem of frequency deviation of the crystal oscillator clock. The FPGA method is used for realizing the correction function of the phase and the frequency, the measurement control is accurate, the realization is easy, the clock synchronization signal is improved to 1.25ns, and the requirements of field application and product development are met.
Description
Technical Field
The invention relates to a method for improving the synchronization of a metering clock of an intelligent substation based on a code phase counting method, and belongs to the field of digital metering processing of substations.
Background
The difference between the target and the function of the intelligent substation metering information acquisition system and the household intelligent ammeter information acquisition is large, the substation occupies a crucial position in the whole power grid system, and plays a role in managing high-voltage power transmission and medium-low voltage power distribution electric energy. Besides basic energy conversion quantity metering settlement, important guarantee is provided for operating electric energy quality guarantee, so that the measuring accuracy and stability of a metering system in a transformer substation are high, a 0.2 s-level mutual inductor is generally adopted to collect high-voltage current and voltage, and the numerical accuracy of sampling signals is improved through control processing of a merging unit. However, with the development of the construction characteristics of the transformer substation towards the direction of integration and miniaturization, various complex bus cascading, internal bridging and other modes appear inside the transformer substation, the metering mode changes from the original single-interval to multi-interval cascading, data acquired by a plurality of mutual inductors are transmitted to a dispatching control system after being cascaded by merging units, the problem of synchronism of the metering and acquiring data of the cross-interval is highlighted, the output value of the metering data of the merging unit at the last stage is inaccurate due to system interference and change of the position of an interstellar synchronous signal in the process of multi-stage operation, and the asynchronous error can seriously affect the stable transmission of the electric energy of the power grid. Therefore, a clock synchronization control function module is added on the basis of the traditional metering mode, the change condition of the reference clock is tracked in real time, a proper method is selected for measuring the clock change characteristic parameters and calculating errors, error data is compensated in real time, and the accuracy and the stability of the output absolute clock are guaranteed.
Disclosure of Invention
The invention designs a method for improving the synchronization of the metering clock of an intelligent substation based on a code phase counting method, solves the problem of errors generated by a metering system of the intelligent substation due to synchronous time service data receiving or running process, respectively measures and corrects the errors from two dimensions of phase and frequency, and ensures the consistency of multi-channel electric energy parameter signals received by a merging unit.
A method for improving the synchronization of a metering clock of an intelligent substation based on a code phase counting method is characterized in that a high-precision clock adjusting module is added on the basis of a traditional substation metering system in order to improve the accuracy of data acquisition of high-voltage electric energy metering information of the intelligent substation, the high-precision clock adjusting module has the main function of adjusting the non-synchronization of an external clock and a satellite clock signal, when a satellite clock receiving signal fails, the satellite clock receiving signal can be smoothly switched to an external on-time clock channel, the synchronous triggering and transmission of a voltage signal and a current signal acquired from a mutual inductor to a merging unit are ensured, the error phenomenon of power transmission sampling value energy caused by the non-synchronization is avoided, and the accuracy of external triggering synchronous time synchronization when the satellite signal is lost in triggering can be effectively ensured.
In order to realize the error compensation function, the high-precision clock adjusting module extracts the pulse-per-second signals from the satellite and the external signals, obtains the corrected pulse-per-second signals after comparison and calculation of the microprocessor, simultaneously inputs the pulse-per-second signals into the sampling data processing unit and the merging unit, sets the trigger conditions of current and voltage values, and ensures that the processing processes of the internal data of the metering system all use the same accurate reference clock as reference; the high-precision clock adjusting module is located at an auxiliary decision position in the metering system, provides basic data for running error evaluation for a plurality of mutual inductor groups and cascaded merging units, tracks running deviation of an external clock signal source in real time, adjusts and compensates in time, and continuously maintains data accuracy in the metering loop system.
Furthermore, the high-precision clock adjusting module is mainly embodied in an FPGA (field programmable gate array) form, rich circuit interfaces of the FPGA respectively receive second pulse information of the GPS/Beidou dual-mode time service and the external auxiliary clock module, and when satellite signal receiving fails, the interface of the external optical receiving module is automatically switched to extract second pulse signals; the method comprises the steps that an active crystal oscillator is selected as a reference clock, an MCU is an external assisting control unit, online or failure control information for processing external clock signals is transmitted to a control module, a phase error measuring and correcting module and a frequency error measuring and correcting module are designed in the control module and are quickly realized by using a logic gate circuit, a circuit expandable space is reserved, an input external second pulse signal PPS1 is subjected to series processing to obtain a precise second clock pulse value PPS2, the delay precision is generally in the order of a few nanoseconds, and a plurality of second pulses are formed to be driven to provide alignment clock information for a voltage acquisition unit, a current acquisition unit and a merging unit.
Furthermore, the phase error measurement and correction module mainly comprises phase measurement and phase correction, the phase delay measurement error between a satellite synchronous clock and a crystal oscillator clock is calculated by measuring the phase shift of an n-minute code word to obtain a phase control word, the phase error of the satellite clock is corrected on the basis of the phase control word serving as a reference, the phase error measurement adopts a method of counting the delay error between a second pulse code of the satellite and the crystal oscillator clock, and a counting rule is defined as that counting is started when a rising edge of the second pulse code/the crystal oscillator clock code is a falling edge, counting is 1 until the rising edge of the next second pulse code comes, and counting is sequentially accumulated until the rising edges of the second pulse code and the crystal oscillator clock come simultaneously and is stopped.
Furthermore, the frequency error measurement and correction module comprises frequency measurement and frequency correction, mainly overcomes the change of the frequency of an atomic clock caused by long-term operation of a crystal oscillator and an external clock, measures the frequency offset error according to a direct frequency measurement method, acquires a frequency control word, realizes frequency division by using the frequency control word as a reference through a frequency synthesis method, identifies the frequency of high-frequency noise, and obtains the correction frequency by using a low-pass filter circuit.
The invention has the beneficial effects that:
the invention designs a method for improving the synchronization of a metering clock of an intelligent substation based on a code phase counting method, wherein the sequential scheme execution outputable period is
The second pulse signal and the clock frequency adjusting scheme can correct the clock offset of the input crystal oscillator clock in the long-term running environment, and the precision can be improved to 10-13A rank. The asynchronous problem of clock synchronization signals under the metering (especially cross-interval) scene of the intelligent substation at present is well solved, and the asynchronous intelligent substation has high practical value.
Drawings
FIG. 1 is a design diagram of a high-precision metering control system of an intelligent substation;
FIG. 2 is a layout diagram of a high-precision clock adjustment circuit;
FIG. 3 is a hardware circuit layout of a phase error measurement and correction module;
FIG. 4 is a PPS pulse clock data clock adjustment process flow;
FIG. 5 is a frequency correction module design based on frequency synthesis;
fig. 6 is a flow of frequency offset measurement and correction processing.
Detailed Description
The design principles and embodiments of the present invention are explained in detail below with reference to the accompanying drawings.
The method for improving the synchronization of the metering clock of the intelligent substation based on the code phase counting method is shown in fig. 1, a module marked in a virtual frame is a newly added part, the measuring and adjusting method designed in the invention is realized in the module in an FPGA (field programmable gate array) architecture form, and the main purpose is to ensure the consistency of all data transmission and processing time adopted in a metering system by adjusting the phase and frequency of an external clock signal. The scheme design process of the high-precision clock adjustment module starts from requirements, a bus bridge connection and merging unit cascade connection mode is adopted for saving construction space based on a future large-scale transformer substation, sampling data can generate large time delay in a cascade system, in addition, the frequency stability of a reference crystal oscillator clock is not stable by an external clock, frequency drift can be generated in the long-term operation process, the slight change of the frequency can change the phase to influence the time synchronization effect, and therefore the module design scheme measures and corrects two parameters according to the idea that two dimensions of the phase and the frequency are processed simultaneously. Therefore, the module comprises a phase measurement, phase correction and frequency measurement and frequency correction sub-module, the phase processing part measures the error value between the rising edge of the external clock and the crystal oscillator clock, outputs a phase control word to the micro-server pair to correct the phase delay and outputs the corrected PPS. The frequency processing part extracts the interference frequency through a frequency corrector sub-module by measuring the error between the crystal oscillator frequency and an external clock, finally filters the interference frequency, outputs the accurate crystal oscillator frequency, and re-inputs the accurate crystal oscillator frequency into the crystal oscillator to replace the original clock frequency signal. The microprocessor is used for converting error data output by the measuring module into control words and inputting the control words into the correcting module, so that the cooperative control of the whole module is realized. The internal circuit layout of the high-precision clock adjustment module is shown in fig. 2, and the module needs to realize various clock access, measurement and correction processes, and can involve functional calculation of different logic circuits related to clock processing, so that the adjustment function is realized on the basis of selecting a semi-formulated circuit architecture of an FPGA (field programmable gate array). Abundant circuit interfaces of the FPGA respectively receive second pulse information of the GPS/Beidou dual-mode time service and the external auxiliary clock module, and when satellite signal receiving fails, the second pulse information can be automatically switched to an external light receiving module interface to extract second pulse signals. The method comprises the steps that a 50MHz active constant-temperature crystal oscillator is selected as a reference clock, an MCU is an external assisting control unit, online or failure control information for processing external clock signals is transmitted to a control module, a phase error measurement and correction module and a frequency error measurement and correction module are designed inside the control module and are all rapidly realized by using a logic gate circuit, a circuit expandable space is reserved, an input external second pulse signal PPS1 is subjected to series processing to obtain a precise clock second pulse value PPS2, the delay precision is generally in a few nanoseconds, and a plurality of second pulses are formed to drive a voltage acquisition unit and a current acquisition and combination unit to provide alignment clock information. On one hand, the high-precision clock adjusting module provides an absolute clock for the current/voltage ADC acquisition unit of the mutual inductor, and the clock consistency of sampled data is ensured; on the other hand, a time logic relationship is indirectly provided for the merging unit, an absolute clock is used as a trigger condition, the data logic dislocation and disorder relationship is avoided, and the newly added clock adjusting module plays a critical role in the whole transformer substation metering and sampling system.
The phase error measurement and correction module adopts a method of delay error counting between a satellite second pulse code and a crystal oscillator clock code, and the counting rule is defined as that counting is started when the rising edge of the second pulse code/the crystal oscillator clock code is a falling edge, the counting is 1 until the rising edge of the next second pulse code comes, and the counting is sequentially accumulated until the rising edges of the second pulse code and the crystal oscillator clock code come simultaneously, and the counting is stopped. The higher the general clock frequency is, the lower the delay error is, but the crystal oscillator clock can not be infinitely high, and the circuit design and the component material can not be realized, so the 50MHz active crystal oscillator is selected. In order to further improve the precision of the time delay error, a phase shifting method is adopted, n division code words are selected for phase shifting, n rows of same-frequency counting code word sequences can be obtained, n frequency multiplication can be improved for an original clock, the time delay error value is the average value of n paths of errors, and the obtained measurement error value is greatly improved. In the same way, the larger the n value is, the larger the promotion amplitude is, but the difficulty in realizing the FPGA logic is also considered comprehensively, so that n =8 is selected through continuous debugging, and the comprehensive application effect is relatively met.
The phase error measurement and correction module is designed as shown in fig. 3, and mainly comprises phase measurement and phase correction, wherein the phase delay measurement error between a satellite synchronous clock and a crystal oscillator clock is calculated through measuring in a code phase shifting mode to obtain a phase control word, and the phase control word is used as a reference basis to correct the phase error of the satellite clock, so that the processing conflict of data on a time axis is avoided. 8 paths of common-frequency clock code words are adopted to form periodically spaced reference clock code word links with the phase difference of 45 degrees, wherein the links are respectively c1, c2, c3, a., c8, the assumed frequency is 50MHz, the period is 20ns, the second pulse signal period is 1s, the pulse width is 10ns, each path of code word signal is used for comparing and counting the input satellite signal and the crystal oscillator signal, the delay error value is generally a few ns and is far less than the second pulse period, the clock counting clock frequency is improved through 8 components for measurement, the error ratio is further reduced, and the value of the error value can be ignored. The number of counts of each counter is aiThe total time delay is measured as:
wherein
Respectively, the time interval from the start of the counting clock to the arrival of the first rising edge and the time interval from the end to the last rising edgeThe time interval at which each rising edge arrives. When the rising edge of the first counting clock arrives, the mark starts counting by the counter, a mark signal flag =1 is set according to the level state of the other path of second pulse corresponding to the rising edge, accumulation is continued, the counting value is continuously increased until the rising edges of the two paths of comparison second pulse links arrive in alignment, the counter stops counting, the counting is reset, and the flag = 1. According to the known condition, the theoretical error of the system source is 2ns, and the error measured by the method is
And the precision is improved by 37.5%. According to
The value and the count value generate a correction control word m, the correction module mainly comprises a count enable control part and a clock delay adjustment part, a clock adjustment action is started through a comparator, and when the delay value is smaller than a certain value, the enable control zone bit 0 is not adjusted; when the time delay is larger than a certain value, the time delay is advanced according to the control word m
。
The frequency error measuring and correcting module mainly overcomes the defect that the frequency of an atomic clock is changed due to long-term operation of a crystal oscillator and an external clock, although the frequency deviation value is generally small, the stability and the accuracy of a synchronous system are influenced, and the frequency deviation value generally reaches 10-13Magnitude. Measuring frequency deviation error according to a direct frequency measurement method, obtaining a frequency control word, taking the frequency control word as a reference, realizing frequency division through a frequency synthesis method, identifying the frequency of high-frequency noise, and obtaining a correction frequency by using a low-pass filter circuit.
The frequency error measurement and correction module mainly comprises frequency measurement and frequency correction, and is used for adjusting the frequency of an input crystal oscillator clock. The frequency deviation and the frequency measurement period have a close relation, and the crystal oscillator clock is basically synchronous with the external pulse per second, so that the clock frequency parameter is extracted by sampling the external pulse per second, the frequency control word n is obtained by calculating the frequency error, the frequency error is compensated, and finally the high-precision clock frequency is output after digital-to-analog conversion. Since the frequency of the satellite clock does not substantially change, the error measurement of the crystal oscillator frequency can be directly compared with the satellite clock frequency to calculate a relative error value. Frequency measurement basic principle:
quantization frequency error value:
relative frequency error value:
where T is the frequency period of the satellite clock signal, f is the measurement frequency,
to measure the error. N is a measurement value of a clock frequency counter, a first term in a relative frequency error formula is an error caused by a counting process and related to a system, a second term is a frequency change error which is directly related to a clock gate time period, the larger T is, the smaller the correction frequency error is, the higher the frequency accuracy is, and the metering frequency accuracy of a transformer substation is generally 10-12Assume that accuracy is to be improved to 10-13The crystal oscillator frequency is 50MHz, according to the formula (5), the measurement of frequency error can be realized through the calculation process of a 30-bit counter, a frequency control word is calculated according to the error value, the error frequency is extracted and filtered by adopting a frequency synthesis technology, the frequency synthesis technology is used for synthesizing the frequencies of different waveforms from the phase angle, the phase adjustment of the phase control word can be directly utilized, and the correction efficiency can be improved. The specific correction process is shown in fig. 5: inputting the frequency control word into a phase register, accumulating the phase control word to obtain the value of the phase register, and outputting the value of the phase registerThe value changes the clock frequency in the sine lookup table, changes the frequency of the output signal by changing the addressed phase increment, outputs different digital waveforms, and then passes through a digital-to-analog conversion module to form a plurality of frequency components such as sine waveforms. The interference frequency of crystal oscillator is generally noise-like frequency with high frequency value, the low-pass filter has low gain to high-frequency signal and can directly filter out the high-frequency signal, and the frequency output from the filter is 10-13The crystal oscillator frequency of 50MHz is input to the starting end again, and the clock frequency of the crystal oscillator is reset.
After the functional module is designed, the next step is to execute the algorithm flow to realize the work. Aiming at the fact that a large amount of logic gate compiling requirements are found in the phase and frequency processing process, the clock synchronization data processing flow is designed in detail, and FPGA hardware program compiling is utilized to achieve the logic gate processing function. The phase measurement and correction logic flow design is shown in fig. 4:
firstly, a phase measurement module starts to receive GPS/Beidou satellite clock signals, and can position satellite source signals within specified time sampling time; if the time is exceeded, the satellite signal reception is invalid; the measuring module starts an external clock receiving mode, and the external clock is used as a backup means, so that the effect of reading and taking at any time can be ensured. The final measurement module can output a stable pulse per second signal PPS 1; the phase measurement module simultaneously acquires crystal oscillator signals as error comparison signals, and second pulse signals are correspondingly extracted;
② inputting counting clock signal to the measuring module, performing 8-division phase shift processing on the counting clock with each phase at 45 deg. interval to form different codeword link data, measuring and counting the error between external clock and crystal oscillator clock by 8-division codeword link, and measuring and counting each link to obtain the result
After summing and averaging, obtaining the average time delay error of a certain rising edge
；
According to the counting rule, accumulating the counting until the two rising edges come in alignment, stopping counting, and resetting the counter to zero; otherwise, the flag bit flag is continuously increased, when the counter is reset, the final delay error is obtained, and the microprocessor generates a phase control word m according to the value and sends the phase control word m to the correction module;
④ the correction module shifts the measured pulse-per-second error signal backwards so the incoming pulse-per-second should be shifted backwards
Compensating the error clock;
finally, outputting the adjusted pulse per second information PPS2 from the correction module, and ending the process.
The multi-division code word measurement mode is applied to the pulse synchronization measurement and correction module, the error precision is greatly improved, the error clock is compensated through a backward delay scheme after the error measurement is realized by utilizing the FPGA logic circuit, the expected synchronization requirement is met, the flow design is simple, and the implementation is easy.
The clock frequency measurement and the adjustment process are performed synchronously, the frequency difference between the two is measured and compensated based on the satellite clock frequency, and the logic flow design of the frequency adjustment submodule is as shown in fig. 6:
reading frequency values of a crystal oscillator clock and a satellite clock in parallel;
judging whether the frequency value is in a normal offset range, if the adopted value exceeds the normal range, indicating that the previous frequency moment is not corrected, and omitting steps, so that the detected frequency is directly sent to a frequency synthesis checking module for readjustment; if the sampling value is in the normal range, entering a frequency error measurement stage;
thirdly, calculating the frequency error between the two signals by adopting a direct frequency measurement method through frequency period and phase counting; the microprocessor obtains a frequency control word n according to the error value;
and fourthly, the frequency synthesizer is guided to generate frequency waveforms with different characteristics according to the frequency control words, the interference frequency generally belongs to high-frequency signals, the interference signals can be directly filtered out through a low-pass filter, the corrected accurate frequency waveforms are reserved, and the process is finished.
And the corrected phase and frequency clock signals are transmitted to a metering sampling module of the transformer substation, and all data take a uniform high-precision clock as a trigger standard, so that the consistency of the data processing process is promoted, and the clock accuracy and stability of the whole metering system are improved.
The foregoing merely represents preferred embodiments of the invention, which are described in some detail and detail, and therefore should not be construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, various changes, modifications and substitutions can be made without departing from the spirit of the present invention, and these are all within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (4)
1. A method for improving the synchronization of the metering clock of an intelligent substation based on a code phase counting method is characterized by comprising the following steps: a high-precision clock adjusting module is added on the basis of a traditional transformer substation metering system, the high-precision clock adjusting module has the main function of adjusting the non-synchronism of an external clock and a satellite clock signal, and when a satellite clock receiving signal fails, the satellite clock receiving signal can be smoothly switched to an external punctual clock channel; the high-precision clock adjusting module extracts a pulse per second signal from a satellite and an external signal, obtains the corrected pulse per second signal after comparison and calculation of the microprocessor, simultaneously inputs the pulse per second signal into the sampling data processing unit and the merging unit, sets triggering conditions of current and voltage values, and ensures that the processing processes of internal data of the metering system all use the same precise reference clock as reference; the high-precision clock adjusting module is located at an auxiliary decision position in the metering system, provides basic data for running error evaluation for a plurality of mutual inductor groups and cascaded merging units, tracks running deviation of an external clock signal source in real time, adjusts and compensates in time, and continuously maintains data accuracy in the metering loop system.
2. The method for improving the synchronization of the metering clock of the intelligent substation based on the code phase counting method according to claim 1, is characterized in that: the high-precision clock adjusting module is mainly embodied in an FPGA (field programmable gate array) form, rich circuit interfaces of the FPGA respectively receive second pulse information of a GPS/Beidou dual-mode time service and an external auxiliary clock module, and when satellite signal receiving fails, the high-precision clock adjusting module can be automatically switched to an external light receiving module interface to extract second pulse signals; the method comprises the steps that an active crystal oscillator is selected as a reference clock, an MCU is an external assisting control unit, online or failure control information for processing external clock signals is transmitted to a control module, a phase error measuring and correcting module and a frequency error measuring and correcting module are designed in the control module and are quickly realized by using a logic gate circuit, a circuit expandable space is reserved, an input external second pulse signal PPS1 is subjected to series processing to obtain a precise second clock pulse value PPS2, the delay precision is generally in the order of a few nanoseconds, and a plurality of second pulses are formed to be driven to provide alignment clock information for a voltage acquisition unit, a current acquisition unit and a merging unit.
3. The method for improving the synchronization of the metering clock of the intelligent substation based on the code phase counting method according to claim 2, is characterized in that: the phase error measurement and correction module mainly comprises phase measurement and phase correction, phase delay measurement errors between a satellite synchronous clock and a crystal oscillator clock are calculated through n-minute code word phase shifting, phase control words are obtained, the phase errors of the satellite clock are corrected on the basis of the phase delay measurement words, a method for counting the delay errors between a satellite second pulse code and the crystal oscillator clock code is adopted for phase error measurement, a counting rule is defined as that counting is started when a second pulse code rising edge/the crystal oscillator clock code is a falling edge, the counting is 1 until the next second pulse code rising edge comes, the counting is sequentially accumulated until the rising edges of the second pulse code and the crystal oscillator clock come simultaneously, and the counting is stopped.
4. The method for improving the synchronization of the metering clock of the intelligent substation based on the code phase counting method according to claim 2, is characterized in that: the frequency error measuring and correcting module comprises frequency measurement and frequency correction, mainly overcomes the change of the frequency of an atomic clock caused by long-term operation of a crystal oscillator and an external clock, measures the frequency deviation error according to a direct frequency measurement method, acquires a frequency control word, takes the frequency control word as a reference, realizes frequency division through a frequency synthesis method, identifies the frequency of high-frequency noise, and obtains the correction frequency by using a low-pass filter circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010716001.1A CN111598727A (en) | 2020-07-23 | 2020-07-23 | Method for improving metering clock synchronization of intelligent substation based on code phase counting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010716001.1A CN111598727A (en) | 2020-07-23 | 2020-07-23 | Method for improving metering clock synchronization of intelligent substation based on code phase counting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111598727A true CN111598727A (en) | 2020-08-28 |
Family
ID=72183048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010716001.1A Pending CN111598727A (en) | 2020-07-23 | 2020-07-23 | Method for improving metering clock synchronization of intelligent substation based on code phase counting method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111598727A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111901938A (en) * | 2020-08-31 | 2020-11-06 | 深圳市明微电子股份有限公司 | LED driving signal processing method and circuit, LED driving device and lamp |
| CN112433469A (en) * | 2020-11-12 | 2021-03-02 | 中国船舶重工集团公司第七0七研究所 | 1PPS time synchronization system and method based on feedback mechanism |
| CN112485519A (en) * | 2020-12-03 | 2021-03-12 | 成都市精准时空科技有限公司 | Method, system, device and medium for measuring absolute frequency difference based on delay line |
| CN112506268A (en) * | 2020-12-15 | 2021-03-16 | 杭州和利时自动化有限公司 | Time synchronization method, device, equipment and storage medium among multiple FPGA (field programmable Gate array) |
| CN113177007A (en) * | 2021-05-20 | 2021-07-27 | 湖北工业大学 | High-reliability Arbiter PUF circuit based on deviation compensation |
| CN113341679A (en) * | 2021-06-15 | 2021-09-03 | 郑州轻大产业技术研究院有限公司 | High-precision signal frequency control method and system based on Beidou space rubidium atomic clock |
| CN113552794A (en) * | 2021-06-24 | 2021-10-26 | 南方电网科学研究院有限责任公司 | Automatic calibration device and method for clock signal in power chip |
| CN114089020A (en) * | 2021-11-10 | 2022-02-25 | 许继集团有限公司 | High-resolution remote signaling acquisition device and method based on double MCUs |
| CN114528998A (en) * | 2022-01-26 | 2022-05-24 | 山东浪潮科学研究院有限公司 | Multi-board-card signal synchronization method, device and medium for quantum measurement and control system |
| CN114567869A (en) * | 2022-02-23 | 2022-05-31 | 东南大学 | FPGA-based intelligent vehicle road system multi-target evaluation device and method |
| CN115065360A (en) * | 2022-08-17 | 2022-09-16 | 中国船舶重工集团公司第七0七研究所 | Second pulse high-precision synchronization method and system based on dynamic phase shifting |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345886A (en) * | 2008-09-03 | 2009-01-14 | 华为技术有限公司 | Method and device for phase error correction |
| US20100080210A1 (en) * | 2008-09-29 | 2010-04-01 | Samsung Electronics Co., Ltd. | System clock synchronization apparatus and method for mobile communication system |
| CN101799658A (en) * | 2010-02-24 | 2010-08-11 | 华中科技大学 | Backup clock calibrated by GPS |
| CN103095446A (en) * | 2011-10-28 | 2013-05-08 | 上海贝尔股份有限公司 | Switch-over method of multimode clock and corresponding multimode clock |
| CN103616814A (en) * | 2013-12-09 | 2014-03-05 | 东南大学 | Synchronous sampling clock closed loop correcting method and system based on FPGA |
| CN104330966A (en) * | 2014-10-22 | 2015-02-04 | 中国人民解放军信息工程大学 | Multi-mode high-precision time and frequency standard equipment |
| CN104485947A (en) * | 2014-12-30 | 2015-04-01 | 中南民族大学 | Digital phase discriminator used for GPS tame crystal oscillator |
| CN105242127A (en) * | 2014-07-03 | 2016-01-13 | 英特尔公司 | Apparatuses, methods, and systems for jitter equalization and phase error detection |
| CN106027187A (en) * | 2016-04-29 | 2016-10-12 | 国家电网公司 | GPS (Global Positioning System) synchronizing signal frequency source circuit |
| CN106154816A (en) * | 2016-07-14 | 2016-11-23 | 南京国电南自电网自动化有限公司 | A kind of punctual method of automaton high accuracy |
| CN107147395A (en) * | 2017-04-26 | 2017-09-08 | 西安空间无线电技术研究所 | A kind of quadrature modulator output DAC synchronous circuits based on bicyclic frequency synthesis |
| CN109116289A (en) * | 2018-11-15 | 2019-01-01 | 国网山东省电力公司电力科学研究院 | A kind of real-time acquisition system of high-voltage mutual inductor group operating status |
| CN110297208A (en) * | 2019-07-26 | 2019-10-01 | 国网安徽省电力公司电力科学研究院 | Digitize live various dimensions test method and test macro across interval metering system |
| CN111208727A (en) * | 2020-01-17 | 2020-05-29 | 深圳市风云实业有限公司 | High-precision satellite pulse-per-second synchronous time keeping device and method |
-
2020
- 2020-07-23 CN CN202010716001.1A patent/CN111598727A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345886A (en) * | 2008-09-03 | 2009-01-14 | 华为技术有限公司 | Method and device for phase error correction |
| US20100080210A1 (en) * | 2008-09-29 | 2010-04-01 | Samsung Electronics Co., Ltd. | System clock synchronization apparatus and method for mobile communication system |
| CN101799658A (en) * | 2010-02-24 | 2010-08-11 | 华中科技大学 | Backup clock calibrated by GPS |
| CN103095446A (en) * | 2011-10-28 | 2013-05-08 | 上海贝尔股份有限公司 | Switch-over method of multimode clock and corresponding multimode clock |
| CN103616814A (en) * | 2013-12-09 | 2014-03-05 | 东南大学 | Synchronous sampling clock closed loop correcting method and system based on FPGA |
| CN105242127A (en) * | 2014-07-03 | 2016-01-13 | 英特尔公司 | Apparatuses, methods, and systems for jitter equalization and phase error detection |
| CN104330966A (en) * | 2014-10-22 | 2015-02-04 | 中国人民解放军信息工程大学 | Multi-mode high-precision time and frequency standard equipment |
| CN104485947A (en) * | 2014-12-30 | 2015-04-01 | 中南民族大学 | Digital phase discriminator used for GPS tame crystal oscillator |
| CN106027187A (en) * | 2016-04-29 | 2016-10-12 | 国家电网公司 | GPS (Global Positioning System) synchronizing signal frequency source circuit |
| CN106154816A (en) * | 2016-07-14 | 2016-11-23 | 南京国电南自电网自动化有限公司 | A kind of punctual method of automaton high accuracy |
| CN107147395A (en) * | 2017-04-26 | 2017-09-08 | 西安空间无线电技术研究所 | A kind of quadrature modulator output DAC synchronous circuits based on bicyclic frequency synthesis |
| CN109116289A (en) * | 2018-11-15 | 2019-01-01 | 国网山东省电力公司电力科学研究院 | A kind of real-time acquisition system of high-voltage mutual inductor group operating status |
| CN110297208A (en) * | 2019-07-26 | 2019-10-01 | 国网安徽省电力公司电力科学研究院 | Digitize live various dimensions test method and test macro across interval metering system |
| CN111208727A (en) * | 2020-01-17 | 2020-05-29 | 深圳市风云实业有限公司 | High-precision satellite pulse-per-second synchronous time keeping device and method |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111901938A (en) * | 2020-08-31 | 2020-11-06 | 深圳市明微电子股份有限公司 | LED driving signal processing method and circuit, LED driving device and lamp |
| CN112433469B (en) * | 2020-11-12 | 2022-04-12 | 中国船舶重工集团公司第七0七研究所 | 1PPS time synchronization system and method based on feedback mechanism |
| CN112433469A (en) * | 2020-11-12 | 2021-03-02 | 中国船舶重工集团公司第七0七研究所 | 1PPS time synchronization system and method based on feedback mechanism |
| CN112485519A (en) * | 2020-12-03 | 2021-03-12 | 成都市精准时空科技有限公司 | Method, system, device and medium for measuring absolute frequency difference based on delay line |
| CN112506268A (en) * | 2020-12-15 | 2021-03-16 | 杭州和利时自动化有限公司 | Time synchronization method, device, equipment and storage medium among multiple FPGA (field programmable Gate array) |
| CN112506268B (en) * | 2020-12-15 | 2023-03-14 | 杭州和利时自动化有限公司 | Time synchronization method, device, equipment and storage medium among multiple FPGA (field programmable Gate array) |
| CN113177007A (en) * | 2021-05-20 | 2021-07-27 | 湖北工业大学 | High-reliability Arbiter PUF circuit based on deviation compensation |
| CN113177007B (en) * | 2021-05-20 | 2023-02-21 | 湖北工业大学 | High-reliability arbiterPUF circuit based on deviation compensation |
| CN113341679B (en) * | 2021-06-15 | 2022-04-12 | 郑州轻大产业技术研究院有限公司 | High-precision signal frequency control method and system based on Beidou space rubidium atomic clock |
| CN113341679A (en) * | 2021-06-15 | 2021-09-03 | 郑州轻大产业技术研究院有限公司 | High-precision signal frequency control method and system based on Beidou space rubidium atomic clock |
| CN113552794A (en) * | 2021-06-24 | 2021-10-26 | 南方电网科学研究院有限责任公司 | Automatic calibration device and method for clock signal in power chip |
| CN114089020A (en) * | 2021-11-10 | 2022-02-25 | 许继集团有限公司 | High-resolution remote signaling acquisition device and method based on double MCUs |
| CN114089020B (en) * | 2021-11-10 | 2023-11-14 | 许继集团有限公司 | High-resolution remote signaling acquisition device and method based on double MCUs |
| CN114528998A (en) * | 2022-01-26 | 2022-05-24 | 山东浪潮科学研究院有限公司 | Multi-board-card signal synchronization method, device and medium for quantum measurement and control system |
| CN114528998B (en) * | 2022-01-26 | 2023-05-12 | 山东浪潮科学研究院有限公司 | Multi-board card signal synchronization method, equipment and medium for quantum measurement and control system |
| CN114567869A (en) * | 2022-02-23 | 2022-05-31 | 东南大学 | FPGA-based intelligent vehicle road system multi-target evaluation device and method |
| CN115065360A (en) * | 2022-08-17 | 2022-09-16 | 中国船舶重工集团公司第七0七研究所 | Second pulse high-precision synchronization method and system based on dynamic phase shifting |
| CN115065360B (en) * | 2022-08-17 | 2022-11-01 | 中国船舶重工集团公司第七0七研究所 | Second pulse high-precision synchronization method and system based on dynamic phase shifting |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111598727A (en) | Method for improving metering clock synchronization of intelligent substation based on code phase counting method | |
| CN107863967B (en) | Multichannel synchronous output calibration device and method | |
| US6943714B2 (en) | Method and apparatus of obtaining power computation parameters | |
| US10075172B2 (en) | Timing-difference measurement | |
| CN202256483U (en) | GPS (Global Positioning System) second-based real-time self-adaptive evenly-spaced sampling synchronous data acquisition device | |
| CN102253358A (en) | Method for correcting electric energy meter by using correction system, and correction system | |
| CN103941622B (en) | Occur frequently again the method for sampling pulse based on the high accuracy pulse per second (PPS) of FPGA | |
| CN106681127B (en) | Shift-register circuit, phase difference calculating method and time-to-digit converter | |
| CN104460311A (en) | Time calibration method and device | |
| CN102236048A (en) | Method for measuring phasor frequency of electric system | |
| CN102662107B (en) | Micro control unit (MCU) built-in reference temperature compensation method based on system on chip (SOC) electric meter | |
| CN110244116A (en) | The metering circuit of direct current instantaneous power and its plesiochronous calculation method | |
| CN108445735B (en) | Method for correcting hierarchical TDC (time-to-digital converter) by adopting delay chain structure | |
| CN111064536A (en) | Power distribution network monitoring device and method based on clock synchronization | |
| CN116931658A (en) | Multi-board synchronous clock architecture and method based on digital-to-analog converter | |
| WO2014155706A1 (en) | Signal processing device | |
| CN111010174B (en) | Method and circuit for improving time-keeping metering precision | |
| CN103684358A (en) | Sampling pulse generation method and device | |
| CN103618501A (en) | Alternating current sampling synchronous frequency multiplier based on FPGA | |
| CN101188422A (en) | Interleaving synchronization sampling real time compensation device and its method based on phase locked loop | |
| CN110912556B (en) | TIADC system sampling time mismatch error estimation method based on difference equalization | |
| CN109656123B (en) | High-precision time difference measuring and generating method based on mathematical combination operation | |
| CN116299566A (en) | High-precision frequency synchronization method of time service type receiver based on phase accumulator | |
| CN105846939A (en) | System for method for accurately keeping synchronization of multiple modules | |
| CN115967398A (en) | Method, system and equipment for updating conversion coefficient of time-to-digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200828 |
|
| RJ01 | Rejection of invention patent application after publication |