CN110912556B - TIADC system sampling time mismatch error estimation method based on difference equalization - Google Patents
TIADC system sampling time mismatch error estimation method based on difference equalization Download PDFInfo
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Abstract
The invention discloses a difference value equalization-based TIADC system sampling moment mismatch error estimation method which is used for solving the problem of extraction of sampling moment mismatch errors among channels in a TIADC system. By arranging the zero-crossing detection unit in the digital domain and simultaneously calculating and comparing the average absolute difference value output by the ADC of the adjacent channels, the sampling clock mismatch condition of the ADC of each channel can be easily judged. Therefore, the error compensation module can be guided to correct the mismatch of the sampling moment according to the judged mismatch information. The invention can realize accurate estimation to the error caused by sampling moment mismatch in the TIADC, can obviously improve the dynamic performance of the TIADC system, has the advantages of high estimation speed, simple structural design, no limitation of the number of channels and the like, and has good effectiveness, universality and practicability.
Description
Technical Field
The invention relates to the technical field of high-speed time-interleaved analog-to-digital converters, in particular to a method for estimating mismatch errors of sampling moments of a TIADC system based on difference equalization.
Background
A high-speed high-precision analog-to-digital converter (ADC) is an indispensable loop in a modern broadband communication system and is widely applied to systems such as 4G/5G wireless base stations and broadband radars. However, the increasing data throughput makes it difficult for single channel analog-to-digital converters to meet the design requirements of today's systems. Thus, a multi-channel time-interleaved analog-to-digital converter (TIADC) has emerged as a more efficient design choice.
The TIADC adopts a plurality of single-channel ADCs for sampling circularly, and each channel ADC is driven by a multiphase clock respectively, so that the plurality of channel ADCs form an integral TIADC, and the effect of increasing the sampling rate by times is realized. The design pressure of a single-channel ADC is greatly relieved, and the sampling rate can be effectively improved to meet the design requirements of various communication systems. Unfortunately, since the interleaved sampling structure has some inherent defects, as shown in fig. 1, that is, the problem of mismatch between channels (Offset), gain (Gain), and sampling time (Timing skew) is present, which results in greatly reduced overall dynamic performance of the TIADC, in order to design a TIADC meeting the requirement, the mismatch problem therein must be solved, and the most direct way is to estimate and correct the mismatch error therein. The current technology development is already mature for estimating Offset and Gain mismatch, but the error extraction for Timing skew is still a problem that is difficult to solve, and thus is a hotspot concerned in the industry.
The traditional Timing skew error estimation algorithm is generally carried out in a foreground mode of injecting test signals, generally, single-tone sinusoidal signals are injected, and then mismatch parameters are estimated by fitting at an output end through a least square method. However, this foreground method requires interruption of the normal sampling process of the TIADC, and is not applicable in many communication systems requiring real-time operation. Therefore, some background error estimation algorithms are proposed to avoid this problem, but some of these background algorithms need to use a special auxiliary channel, which increases the circuit area and power consumption; some background algorithms based on signal autocorrelation operation often need to perform complex digital operation, and further optimization is needed in complexity.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a method for estimating the mismatch error of the sampling time of the TIADC system based on difference equalization, so that the influence caused by mismatch of Timing skew in the TIADC system is solved, and the extraction of the mismatch error of the sampling time among channels in the TIADC is realized.
The invention adopts the following technical scheme for solving the technical problems:
the invention provides a difference equalization-based TIADC system sampling moment mismatch error estimation method, which comprises the following steps of:
D i ＝|y i+1 -y i |
D i-1 ＝|y i -y i-1 |；
wherein the content of the first and second substances,
y i+1 representing the output value, y, of the (i + 1) th channel ADC i-1 Representing the input of an i-1 th channel ADCThe value of the obtained value is obtained,
D i output value and adjacent y representing zero crossing region of ith channel ADC i+1 The absolute value of the difference of (a),
D i output value and adjacent y representing zero crossing region of ith channel ADC i-1 The absolute value of the difference of (a);
step 3, repeating the operation of the step 2 until N D are counted i And D i-1 The average value after N times of statistics is obtained, namely:
wherein D is i (k) Representing the calculated kth D i The numerical value is calculated for N times to obtain N D i Value of (D) i-1 (k) Representing the calculated kth D i-1 The total number of times of calculating N times to obtain N numbers of D i-1 The value of (a) is,
E i1 denotes N numbers of D i The average of the values of the number of points,
E i2 represents N numbers of D i-1 The average of the values;
and 5, compensating and correcting the mismatched sampling time according to the information judged in the step 4, and finally obtaining the calibrated TIADC output signal.
As a further optimization scheme of the difference equalization-based TIADC system sampling time mismatch error estimation method, a digital zero-crossing detection module only needs to set a threshold range, and the size of the threshold is determined by the number of bits of a designed TIADC; and the digital zero-crossing detection module is used for selecting sampling points near zero values.
As a further optimization scheme of the sampling time mismatch error estimation method of the TIADC system based on the difference equalization, if E in step 4 i1 <E i2 If the channel is in the ideal sampling time position, the actual sampling time position of the channel lags behind the ideal sampling time position, namely the sampling time is a negative value; if E i1 >E i2 Then the actual sampling instant position of the channel is advanced from the ideal sampling instant position, i.e. the sampling instant is positive.
As a further optimization scheme of the difference equalization-based TIADC system sampling moment mismatch error estimation method, in step 5, an error compensation module is adopted to compensate and correct sampling moment mismatch, and finally calibrated TIADC output signals are obtained.
As a further optimization scheme of the difference equalization-based TIADC system sampling moment mismatch error estimation method, an error compensation module is a numerical control adjustable delay line or an adjustable fractional delay filter.
As a further optimization scheme of the difference equalization-based TIADC system sampling time mismatch error estimation method, zero-crossing areas of upper and lower ten LSBs of a zero value are near the zero value.
As a further optimization scheme of the difference equalization-based TIADC system sampling moment mismatch error estimation method, N is 4096.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
(1) According to the method, zero-crossing detection, zero-crossing point adjacent absolute difference calculation and mean value calculation are carried out on each channel output of the TIADC so as to extract sampling time mismatch information, and the estimated mismatch information can be compensated in a mode of adjusting a numerical control adjustable delay line and the like;
(2) The invention can accurately extract the mismatch error of sampling time existing in the TIADC system; therefore, the dynamic performances of the TIADC system such as SNDR, SFDR and the like are effectively improved, the improvement degree of the SNDR and the SFDR is obvious, and the estimation speed is high; meanwhile, the estimation algorithm is realized in a full digital mode, has a simple and clear structure, is easy to realize, is not limited by the interference of PVT and other factors and the number of TIADC channels, and has good effectiveness, universality and practicability.
Drawings
Fig. 1 is a system model of a time-interleaved analog-to-digital converter with mismatch error.
FIG. 2 is a schematic diagram of the method of the present invention.
Fig. 3 is a flowchart of the method of the present invention.
Fig. 4 is a block diagram of an implementation of the method of the present invention.
FIG. 5 is a graph of the output signal spectrum of a TIADC simulation system before applying the method of the present invention.
FIG. 6 is a graph of the output signal spectrum of a TIADC simulation system after applying the method of the present invention.
FIG. 7 is a graph showing the convergence of the method of the present invention in estimating errors.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 2, 3 and 4, the invention designs a method for estimating sampling moment mismatch errors among TIADC system channels based on difference equalization, which specifically comprises the following steps:
D i ＝y i+1 -y i
D i-1 ＝y i -y i-1
step 3, repeating the operation of the step 2 until N D are counted i And D i-1 The average value after N times of statistics is obtained, namely:
And 5, guiding an error compensation module (a numerical control adjustable delay line or an adjustable fractional delay filter) to compensate and correct mismatched Timing skew according to the information judged in the step 4, and finally obtaining a calibrated TIADC output signal.
The digital zero-crossing detection module is simple and easy to operate in design, only a reasonable threshold range needs to be set, and the size of the threshold is determined by the number of bits of the designed TIADC. The purpose of designing the zero-crossing detection module is to select sampling points near the zero value, because the sampling points near the zero value are almost consistent in slope, and mismatch errors can be reflected to the maximum extent.
The Timing skew error information can be extracted by simply calculating the difference and average of the output of each channel ADC, the operation is simple and convenient, the design and integration are easy, and the number of sampling points required in the speed estimation is small.
In order to verify that the invention can quickly estimate the error of the mismatch at the sampling time, a verification embodiment is described, and the working principle of the invention is described in detail below with reference to the TIADC system and the simulation result.
Example 1:
in this embodiment, taking a four-channel TIADC system model as an example, the method includes the following steps:
(1) First, the TIADC system of this embodiment will be described, and this embodiment takes a four-channel TIADC simulation system as an example, and the overall sampling rate of the system is 1GS/s, and the system is composed of four identical 10bit 250MS/s single-channel ADCs. The initial values of the sampling instant mismatches for channels 1, 2, 3, 4 are set to-10 ps, 20ps, -30ps, respectively. The input signal to the TIADC is a 171MHz sinusoidal signal with an amplitude of 1Vpp.
(2) In the sampling process of the TIADC, the output of each channel ADC is subjected to zero-crossing detection in the digital domain, and for the 10-bit TIADC of this embodiment, the lower limit of the detection threshold is set to 500, and the upper limit is set to 524.
(3) Respectively calculating the absolute value of the difference between the sampling point and the sampling point of the ADC of the front and back adjacent channels aiming at the sampling point screened out by the zero-crossing detection in the last step, counting the absolute value of the difference for N =4096 times in total, and solving the average value E i1 And E i2 。
(4) Comparing the two average values obtained in the previous step, if E i1 <E i2 If the channel is in the ideal sampling time position, the actual sampling time position of the channel lags behind the ideal sampling time position, namely the Timing skew is a negative value; if E is i1 >E i2 Then the actual sample time position of the channel is advanced from the ideal sample time position, i.e. Timing skew is positive.
(5) According to the comparison result in the last step, if the Timing skew is judged to be a negative value, the delay time of the numerical control adjustable delay line is increased; and if the Timing skew is judged to be a positive value, reducing the delay time of the numerical control adjustable delay line. Finally, the Timing skew of each channel is consistent, and the purpose of eliminating mismatch errors of sampling moments is achieved.
FIGS. 5 and 6 are graphs of the output spectrum of the 10bit 1GS/s TIADC before and after calibration by the estimation method of the present invention. Before calibration, due to the influence of mismatch of sampling time, a plurality of error spurious spectral lines exist in an output spectrum, and the SNDR and the SFDR of the TIADC are seriously deteriorated, wherein the SNDR =33.7dB and the SFDR =37.3dB, and the design requirement of the 10-bit TIADC is far not met. After the estimation method provided by the invention is combined with numerical control adjustable delay line compensation, the amplitude of an error stray spectral line is obviously reduced, the SNDR and the SFDR are respectively improved to 60.8dB and 74.1dB, the dynamic performance is obviously improved, and the design requirement of a 10-bit TIADC is completely met.
Fig. 7 shows the convergence process of the estimation curve of each channel mismatch parameter in the error estimation process according to the method of the present invention. It can be seen that the estimated value of Timing skew mismatch parameter for each channel is completely consistent with the set initial value, indicating that the accuracy of error estimation is very high. Meanwhile, the estimation curve of each channel tends to be stable after 10 iterations, and a convergence state is reached, which indicates that for the 1GS/s TIADC in the embodiment, the estimation of the Timing skew error can be completed only in about 40us, and fully indicates that the speed of the estimation method is high.
In conclusion, the sampling time mismatch error estimation method of the TIADC system based on the difference equalization, which is provided by the invention, can accurately estimate the sampling time mismatch value between channels in the TIADC system, obviously improve the SNDR, SFDR and other system performances of the TIADC, has the advantages of high estimation speed, easy realization, no limitation of the number of channels and interference of process, voltage and temperature changes, and good effectiveness, universality and practicability.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (7)
1. A TIADC system sampling moment mismatch error estimation method based on difference equalization is characterized by comprising the following steps:
step 1, screening an output value y of the ith channel ADC near a zero value through a digital zero-crossing detection module for a TIADC system with sampling time mismatch i ；
Step 2, if y i Within the preset zero-crossing area, y is calculated respectively i The absolute value of the difference between the ADC output values of the front and the rear adjacent channels; namely:
D i ＝|y i+1 -y i |
D i-1 ＝|y i -y i-1 |；
wherein the content of the first and second substances,
y i+1 representing the output value, y, of the (i + 1) th channel ADC i-1 Represents the output value of the i-1 th channel ADC,
D i output value and adjacent y representing zero crossing region of ith channel ADC i+1 The absolute value of the difference of (a),
D i output value and adjacent y representing zero crossing region of ith channel ADC i-1 The absolute value of the difference of (a);
step 3, repeating the operation of the step 2 until N D are counted i And D i-1 The average value after N times of statistics is obtained, namely:
wherein D is i (k) Representing the calculated kth D i The numerical values are calculated for N times to obtain N D i Value of (D) i-1 (k) Representing the calculated kth D i-1 The total number of times of calculating N times to obtain N numbers of D i-1 The value of (a) is set to (b),
E i1 denotes N numbers of D i The average of the values is calculated as the average of the values,
E i2 denotes N numbers of D i-1 The average of the values;
step 4, comparing the two average values obtained in step 3, if E i1 <E i2 Then the actual sampling instant position of the channel lags behind the ideal sampling instant position; such asFruit E i1 >E i2 If the actual sampling time position of the channel is ahead of the ideal sampling time position; the ideal sampling moment position refers to a correct sampling moment position without any mismatch;
and 5, compensating and correcting the mismatched sampling time according to the information judged in the step 4, and finally obtaining the calibrated TIADC output signal.
2. The method for estimating the sampling time mismatch error of the TIADC system based on the difference equalization as claimed in claim 1, wherein the digital zero-crossing detection module only needs to set a threshold range, and the size of the threshold is determined by the number of bits of the designed TIADC; and the digital zero-crossing detection module is used for selecting sampling points near zero values.
3. The method of claim 1, wherein if E in step 4 is equal, the method for estimating the mismatch error of the TIADC system based on the difference equalization i1 <E i2 If the channel is in the ideal sampling time position, the actual sampling time position of the channel lags behind the ideal sampling time position, namely the sampling time is a negative value; if E is i1 >E i2 Then the actual sampling instant position of the channel is advanced from the ideal sampling instant position, i.e. the sampling instant is positive.
4. The method for estimating the sampling time mismatch error of the TIADC system based on the difference equalization as claimed in claim 1, wherein in step 5, an error compensation module is adopted to compensate and correct the sampling time mismatch, and finally a calibrated TIADC output signal is obtained.
5. The method of claim 4, wherein the error compensation module is a digitally controlled adjustable delay line or an adjustable fractional delay filter.
6. The method for estimating sampling time mismatch error of TIADC system based on difference equalization as claimed in claim 1, wherein the vicinity of zero is zero-crossing region of ten LSBs above and below zero.
7. The method for sampling time mismatch error estimation in a TIADC system based on difference equalization of claim 1, wherein N is 4096.
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| CN109274372A (en) * | 2018-09-05 | 2019-01-25 | 东南大学 | Sampling instant mismatch error extracting method between a kind of TIADC system channel |
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| CN109274372A (en) * | 2018-09-05 | 2019-01-25 | 东南大学 | Sampling instant mismatch error extracting method between a kind of TIADC system channel |
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