CN116931658A - Multi-board synchronous clock architecture and method based on digital-to-analog converter - Google Patents

Abstract

The application discloses a multi-plate synchronous clock architecture and a method based on a digital-to-analog converter, which relate to the technical field of clock synchronization and comprise a multi-stage clock tree frame and an FPGA clock synchronization system based on the digital-to-analog converter, wherein the multi-stage clock tree frame is used for carrying out adjustment processing of multi-stage clock synthesis on a reference clock signal, then generating multiple paths of sampling clock signals and data clock signals which are input into the FPGA clock synchronization system, and respectively input into a sampling clock port of the digital-to-analog converter, a first data clock port of the digital-to-analog converter and a second data clock port of an FPGA chip in output modes of the sampling clock signals, the first data clock signals and the second data clock signals; the application can ensure that the data clock signals input by the multi-disc digital-to-analog converter and the frequency division clock signals output by the multi-disc digital-to-analog converter have consistent phases through the two-stage clock generator synchronization mechanism, and avoid the problem that the prior signal synchronization device is easy to cause random phase differences.

Description

Multi-board synchronous clock architecture and method based on digital-to-analog converter

Technical Field

The application relates to the technical field of clock synchronization, in particular to a multi-plate synchronous clock architecture and method based on a digital-to-analog converter.

Background

Along with the development of requirements and technologies, in the field of quantum computation, to realize accurate control over a plurality of quantum bits, multiple synchronous arbitrary waveform pulses are required. The bandwidth of the output signal, the number of channels, and the timing accuracy between the channels are important indicators of the arbitrary wave pulse generator. At present, LTC2000 is selected as a waveform generator in the market, but the synchronous implementation scheme basically depends on a synchronous mechanism of a DAC, and the common clock scheme of the conventional waveform generator is generally sampling clock synchronization, and the clock source mainly is external filling value, so that a data clock is generated during frequency division.

In the existing working scheme for realizing the synchronization between channels by adopting a digital-to-analog converter, the contents mainly comprise: square wave signals generated by a voltage-controlled oscillator in the digital-to-analog converter are used as data clocks of the FPGA to be input; and the data associated clock signal generated by the FPGA is used as a data clock signal of the digital-to-analog converter and is directly input into the digital-to-analog converter. The synchronous mechanism of the scheme needs to read back sampling clocks of a plurality of digital-analog converters and phase discriminator results of the data clocks in real time, the process is that the PH value output by each phase discriminator is sequenced in an upper computer or a system MCU, the maximum value and the minimum value are calculated to obtain the maximum difference value, and finally the difference value is compared with a threshold value, and a channel larger than the threshold value needs to set delay of one sampling clock through MCU signaling to ensure the output synchronization. When the system is provided with multiple boards or multiple chassis, the synchronization mechanism has a problem of being too complex, and misjudgment or instant interference is easy to generate in the operation of the system, so that output has cycle jump. In addition, in the prior art, channel data synchronization is realized by setting an external reference clock, but because the signal frequency of the external reference clock is higher, high-frequency interference is easily caused by an internal wiring, so that the normal operation of other devices is influenced; meanwhile, in the external clock scheme, the connector and the clock wiring have larger insertion loss, so that the clock quality of a plurality of boards is poor, meanwhile, the data clock obtained by frequency division of the reference clock is assumed to be m frequency division, and the frequency division can cause the characteristic of uncertain phase, so that m different phase relations exist in different boards or cabinets, and the final output has random phase difference.

Disclosure of Invention

The application provides a multi-plate synchronous clock architecture and a method based on a digital-to-analog converter, which are used for designing a simple and efficient synchronous clock architecture under the condition that index conditions are met, and can avoid the problems that the existing data clock is derived from a clock synthesizer in the digital-to-analog converter, so that the synchronous mechanism has complex calibration and random phase difference is caused by clock frequency division.

The application is realized by the following technical scheme:

the multi-plate synchronous clock architecture based on the digital-to-analog converter comprises a multi-stage clock tree frame based on a voltage-controlled oscillator and an FPGA clock synchronous system based on the digital-to-analog converter, wherein the multi-stage clock tree frame is used for carrying out adjustment processing of multi-stage clock synthesis on a reference clock signal, then generating multiple paths of sampling clock signals and data clock signals which are input into the FPGA clock synchronous system, and respectively input into a sampling clock port of the digital-to-analog converter, a first data clock port of the digital-to-analog converter and a second data clock port of an FPGA chip in the output form of the sampling clock signals, the first data clock signals and the second data clock signals; the FPGA clock synchronization system comprises a plurality of digital-to-analog converters and an FPGA chip, and is used for inputting sampling clock signals and first data clock signals output by a multi-stage clock tree frame to the digital-to-analog converters, inputting second data clock signals to the FPGA chip, respectively comparing phases of the first data clock signals and the four-divided 0-degree and 90-degree clocks of the sampling clock signals through the digital-to-analog converters, adjusting output delay of the digital-to-analog converters according to the results, finally accessing analog signals output by the digital-to-analog converters to an oscilloscope, and observing synchronization results of a plurality of channels. In the prior art, a square wave signal generated by a voltage-controlled oscillator in a digital-to-analog converter is used as a data clock input of an FPGA; and taking the data associated clock signal generated by the FPGA as a data clock input signal of the digital-to-analog converter. The synchronization mechanism of the scheme needs to read back the sampling clock of a plurality of digital-analog converters and the phase discriminator result of the data clock in real time, and is too complex, so that misjudgment or instant interference is easy to generate in the operation of the system. On the other hand, in the common external reference clock synchronization technology, the signal frequency of the reference clock is higher, and the internal wiring is easy to cause high-frequency interference so as to influence the normal operation of other devices; meanwhile, in the external clock scheme, the data clock obtained by frequency division of the reference clock is assumed to be m frequency division, and because the frequency division can cause the characteristic of uncertain phase, m different phase relations exist in different boards or cabinets, so that random phase differences exist in final output. Based on the above, the application provides a multi-board synchronous clock architecture and a method based on a digital-to-analog converter, which aim to design a simple and efficient synchronous clock architecture under the condition of meeting index conditions, so that the problems of complex calibration and random phase difference caused by clock frequency division in the existing digital-to-analog converter synchronization mechanism can be avoided.

Further, the multi-stage clock tree framework comprises a clock source, a first-order clock generator and a second-order clock generator which are sequentially connected in a signal mode, and the clock source provides a reference clock signal for the first-order clock generator; the reference clock signal output by the clock source is output to the clock input port of the first-order clock generator.

Further, the first-order clock generator outputs a first-order clock signal and a synchronous signal to the input end of the second-order clock generator through signal output; the second-order clock generator inputs the sampling clock signal, the first data clock signal and the second data clock signal to a sampling clock port of the digital-to-analog converter, a first data clock port of the digital-to-analog converter and a second data clock port of the FPGA chip respectively through signal output.

Further, in the FPGA clock synchronization system, each of the FPGA chips can form a set of data units with at least one digital-to-analog converter, and the multi-stage clock tree framework maintains signal inputs of a sampling clock signal, a first data clock signal, and a second data clock signal for each set of data units.

Further, the clock generator includes:

and the acquisition selection module is used for: the synchronous signal acquisition device comprises a signal acquisition device and a synchronous selector, wherein the signal acquisition device is used for receiving an external synchronous signal and converting the external synchronous signal into a digital control signal, and the synchronous selector is used for selecting different clock sources to perform synchronous operation according to the state of the synchronous signal;

the synchronization generation module: the synchronous state machine is used for synchronizing an external reference clock signal with an internal data clock signal so as to realize synchronization and management of the clock signals;

and an output control module: including a retimer for delaying the signal and retiming the rising and falling edges of the signal and a clock gater for suspending or resuming the transmission of the clock signal when needed to reduce the overall power consumption of the chip.

Further, the digital-to-analog converter includes:

the frequency dividing module: the sampling clock signal is used for carrying out four frequency division on the received sampling clock signal, and the frequency-divided clock signals after frequency division are respectively named as clocks of 0 DEG, 90 DEG, 180 DEG and 270 DEG according to initial phases;

register module: the digital-to-analog converter is used for latching reference processing data input to the first data input port and the second data input port at the moment of rising edge or falling edge of the first data clock signal;

and the phase comparison module is used for: the phase difference value between each frequency division clock signal outputted after frequency division and the first data clock signal is calculated, and the time length from the rising edge of the first data clock signal to the rising edge of the sampling clock signal is calculated;

and a time delay module: and the delay module is used for delaying the frequency division data clock signals taken out from the register module, and the period interval length of the delay is equal to the phase difference value of each frequency division clock signal and the first data clock signal calculated by the phase comparison module.

A digital-to-analog converter based multi-board synchronization method, the method comprising:

step S1: inputting a reference clock signal into a multi-stage clock tree consisting of a plurality of clock generators, performing primary synchronization processing on the signals through two-stage clock generators in the multi-stage clock tree, detecting and converting the synchronization signals by using the clock generators, selecting corresponding clock sources according to different states of the synchronization signals, and synchronizing an external reference clock signal with an internal clock signal through a synchronization state machine;

step S2: synchronizing the synchronized data clock signals to confirm whether delay or retiming is needed, and outputting the synchronized data clock signals to a sampling clock port of a digital-to-analog converter, a first data clock port of the digital-to-analog converter and a second data clock port of an FPGA chip in the forms of a sampling clock signal, a first data clock signal and a second data clock signal on an FPGA clock synchronizing system after the synchronization is finished;

step S3: respectively inputting reference processing data related to a digital-to-analog converter in an FPGA chip to a first data input port and a second data input port of the digital-to-analog converter, and simultaneously sampling two paths of reference processing data of the first data input port and the second data input port through the digital-to-analog converter at the rising edge and the falling edge of a first data clock signal;

step S4: and then, respectively comparing the phases of the first data clock signal and the four-frequency-divided 0-degree clock and the four-frequency-divided 90-degree clock of the sampling clock signal through the digital-analog converter, adjusting the output delay of the digital-analog converter according to the result, and finally, accessing the analog signals output by the digital-analog converters into an oscilloscope to observe the synchronous result of a plurality of channels.

Further, the working method of the synchronous state machine comprises the following steps:

step A1: configuring parameters of each path of clocks of the first-order clock generator and the second-order clock generator, wherein the parameters comprise clock frequency, frequency division coefficient and delay period required by synchronization, entering a state waiting for starting a synchronous signal after the configuration is completed, performing parameter configuration correction after each configuration, and performing reconfiguration or parameter correction if normal transmission is not performed;

step A2: after receiving the start synchronizing signal, closing the clock channel capable of synchronizing so as to avoid the interference of the frequency divider of the enable synchronizing channel on the synchronizing signal, starting counting by the synchronizing counter, and waiting for the period counting of the synchronizing signal to be completed;

step A3: after the internal synchronous counter finishes counting, the clock channel and the pulse generator channel are started again, and pulse signals with different frequencies and phases are generated by the pulse generator according to the needs to finish synchronous pulses.

Compared with the prior art, the application directly inputs the data clock signals of the multiple digital-to-analog converters through the external clock generator and ensures that the data clock signals input by the multiple digital-to-analog converters and the frequency division clock signals output by the multiple digital-to-analog converters have completely consistent phases through the synchronization mechanism of the two-stage clock generator, thereby avoiding the problem that the synchronization mechanism in the prior signal synchronization device easily causes random phase differences, and having the following advantages and beneficial effects.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

FIG. 1 is a schematic diagram of a connection structure of a multi-stage clock tree framework and an FPGA clock synchronization system of the present application;

FIG. 2 is a schematic diagram of a multi-stage clock tree framework;

FIG. 3 is a schematic diagram of the internal structure of a clock generator;

FIG. 4 is a schematic diagram of the internal structure of the digital-to-analog converter;

FIG. 5 is a schematic workflow diagram of a synchronous state machine;

FIG. 6 is a timing diagram of synchronization of multiple digital-to-analog converters;

FIG. 7 is a diagram showing a comparison of the delay relationship between the first data clock signal and the divided clock signal;

FIG. 8 is a data flow chart for a digital-to-analog converter synchronization signal;

FIG. 9 is a graph showing the connection relationship of digital-to-analog converter signal processing in the conventional art;

FIG. 10 is a timing diagram of a digital to analog converter;

fig. 11 is a flow chart of the present application.

Detailed Description

For the purpose of making apparent the objects, technical solutions and advantages of the present application, the present application will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present application and the descriptions thereof are for illustrating the present application only and are not to be construed as limiting the present application.

Example 1

As shown in fig. 1-3, the application is a digital-to-analog converter based multi-board synchronous clock architecture, which comprises a voltage-controlled oscillator based multi-stage clock tree framework and a digital-to-analog converter based FPGA clock synchronization system; the multi-stage clock tree framework is used for carrying out multi-stage clock synthesis adjustment processing on the reference clock signals, generating multiple paths of sampling clock signals and data clock signals, inputting the multiple paths of sampling clock signals and the data clock signals into the FPGA clock synchronous system, and respectively inputting the multiple paths of sampling clock signals, first data clock signals and second data clock signals into a sampling clock port of the digital-to-analog converter, a first data clock port of the digital-to-analog converter and a second data clock port of the FPGA chip in output modes of the sampling clock signals, the first data clock signals and the second data clock signals; the FPGA clock synchronization system comprises a plurality of digital-to-analog converters and an FPGA chip, and is used for inputting sampling clock signals and first data clock signals output by a multi-stage clock tree frame to the digital-to-analog converters, inputting second data clock signals to the FPGA chip, respectively comparing phases of the first data clock signals and the four-divided 0-degree and 90-degree clocks of the sampling clock signals through the digital-to-analog converters, adjusting output delay of the digital-to-analog converters according to the results, finally accessing analog signals output by the digital-to-analog converters to an oscilloscope, and observing synchronization results of a plurality of channels.

Further, the multi-stage clock tree framework comprises a clock source, a first-order clock generator and a second-order clock generator which are sequentially connected through signals, wherein the clock source provides a reference clock signal for the first-order clock generator; the reference clock signal output by the clock source is output to the clock input port of the first-order clock generator. The first-order clock generator outputs a further-order clock signal and a synchronous signal to the input end of the second-order clock generator through signal output; the second-order clock generator inputs the sampling clock signal, the first data clock signal and the second data clock signal to a sampling clock port of the digital-to-analog converter, a first data clock port of the digital-to-analog converter and a second data clock port of the FPGA chip respectively through signal output. In a specific application of the embodiment, the clock generator adopts an HMC7044 chip, the digital-to-analog converter adopts an LTC2000 chip, the FPGA chip is not specifically limited, and in a specific implementation, the clock generator can be selected from various types of chips, for example, virtex chips, artix chips, etc. can be used for clock signal transmission operation of the embodiment.

The clock generator is arranged in a multi-stage signal transmission mode, so that the step-by-step adjustment and calibration of clock signals can be realized, and higher synchronization precision can be achieved; by cascading multiple clock generators together, the effects of noise and errors of a single clock generator on the synchronization effect can be reduced. In the synchronization process, the parameters of each clock generator can be independently set and adjusted according to specific application requirements. For example, parameters of each clock generator can be configured according to different clock frequencies, phase requirements and data transmission rates of the data clock signal or the sampling clock signal, or the frequency division or frequency multiplication proportion of the clock signal can be adjusted by adjusting the number of clock generators of a certain order so as to meet the requirements of different situations. The existing data clock signal is derived from a clock synthesizer in the digital-to-analog converter, the method can cause phase ambiguity in internal four-frequency division, various signal noises are introduced, the clock synchronization quality is obviously deteriorated, and the clock signal synchronization is very difficult to realize by the existing method.

Further, in the FPGA clock synchronization system, each of the FPGA chips can form a set of data units with at least one digital-to-analog converter, and the multi-stage clock tree framework maintains signal inputs of a sampling clock signal, a first data clock signal, and a second data clock signal for each set of data units. Wherein the clock generator comprises:

and the acquisition selection module is used for: the synchronous signal acquisition device comprises a signal acquisition device and a synchronous selector, wherein the signal acquisition device is used for receiving an external synchronous signal and converting the external synchronous signal into a digital control signal, and the synchronous selector is used for selecting different clock sources to perform synchronous operation according to the state of the synchronous signal. The signal collector is responsible for receiving the data clock signals from the external device and passing them to the synchronous selector. Signal collectors typically have high-speed data receiving capabilities that enable capturing and preliminary processing of high-speed data clock signals. The synchronous selector receives a plurality of data clock signals from the signal collector and selects one of the data clock signals as a synchronous clock signal according to a preset synchronous criterion. The synchronous selector can select the most suitable synchronous clock signal according to the conditions of the phase relation, the frequency and the like of the data clock signal, and ensures the stability and the accuracy of the data clock signal transmission.

The synchronization generation module: including a synchronous state machine, whose operation is shown in fig. 5. The synchronous state machine is used for synchronizing an external reference clock signal with an internal data clock signal so as to realize synchronization and management of the clock signals. The synchronous state machine is responsible for realizing synchronous state transfer and logic control, sampling and timing adjustment are carried out on data according to a received data clock signal, stability and accuracy of the data clock signal in a transmission process are ensured, and meanwhile, the synchronous state machine is also responsible for generating a control signal required by an output control module and coordinating and communicating with the output control module.

And an output control module: including a retimer for delaying the signal and retiming the rising and falling edges of the signal and a clock gater for suspending or resuming the transmission of the clock signal when needed to reduce the overall power consumption of the chip. The retimer is responsible for retiming the data clock signals to ensure that they remain consistent within the synchronous state machine; the clock gating is used for controlling the on-off of the data clock signal so as to realize the on-off control and the beat control of the data clock signal. It may suspend or resume the transmission of clock signals as needed to achieve delay or timing control of the data.

The reference processing data mainly comprises configuration parameter data related to the digital-to-analog converter, including parameters such as sampling rate, sampling precision, gain and the like, and also relates to data processing parameters such as preprocessing or calculation content related to the sampled data, and can also comprise partial control instructions, other communication data and the like. After the reference processing data enter the digital-to-analog converter, the digital-to-analog converter converts LVDS signals in the reference processing data into single-ended signals and then gives the single-ended signals to subsequent operations. The specific relation between the reference processing data and the first data clock signal is that the reference processing data values input in the first data input port and the second data input port are respectively latched into a register through the rising edge and the falling edge of the first data clock signal in the digital-analog converter, the signals subjected to four frequency division by the frequency division clock signal beat reg 1-4 to obtain reg_MUX1-4 in a cross-clock domain manner, the frequency division clock signal takes out the data through the rising edge of each clock period of the shift register, and finally the data is delayed for n periods and output to a DAC module in the digital-analog converter for signal conversion. The data is delayed for n periods, and the value of n is derived from the phase difference value of the frequency division clock signal and the first data clock signal.

Further, as shown in fig. 4, the digital-to-analog converter includes:

the frequency dividing module: the clock signal processing circuit is used for dividing the received sampling clock signal by four times, and the divided clock signals after frequency division are respectively named as 0 DEG, 90 DEG, 180 DEG and 270 DEG clocks according to initial phases. Since a sine wave is a periodically varying signal, its period is 360 °. In one period of the sine wave, it can be divided into four phase angles of 0 °,90 °,180 ° and 270 °, respectively. The four phase angles represent different phases of the sine wave, wherein 0 ° represents a start point of the sine wave, 90 ° represents a positive peak point of the sine wave, 180 ° represents an inversion point of the sine wave, 270 ° represents a negative peak point of the sine wave, and when the data clock signal is divided by four in the LTC2000, a rising edge or a falling edge of the data clock signal corresponds to the phase angle of the sine wave according to a phase relationship of the sine wave. Particularly, random four frequency division results exist in different LTC2000 digital-analog converters, the phase of the frequency division clock signal after frequency division is directly delayed by 0-3 clock cycles when data are collected, the specific delay period length can be calculated through the phase discrimination result in synchronous phase discrimination, and delay output can be automatically carried out at the later stage to ensure synchronization. This phase uncertainty is the main factor that leads to the dyssynchrony. In this divide-by-four manner, LTC2000 may ensure that the rising and falling edges of the data clock signal are synchronized with the input reference signal at the correct phase. This phase relationship is very important for achieving high-precision data synchronization because it can ensure stability and accuracy of data transmission, and thus the present embodiment performs frequency division setting of signals according to these four angles.

Register module: for latching reference process data input to the first data input port and the second data input port at the digital-to-analog converter at the time of a rising edge or a falling edge of the first data clock signal. The function is to ensure that at a particular clock edge instant, the value of the input clock signal is fixed for subsequent data processing and computation. The accurate sampling and synchronization of the input data can be achieved by latching the clock signal values by the latches, since any minor error can lead to inaccurate processing of the signal data synchronization and erroneous operation results.

And the phase comparison module is used for: and the phase difference value between each frequency division clock signal output after frequency division and the first data clock signal is calculated, and the time length from the rising edge of the first data clock signal to the rising edge of the sampling clock signal is calculated. The phase relation between the first data clock signal and the frequency division clock signal can be obtained through the phase discrimination work of the phase comparison module, the principle is that the first two clocks of the four clocks after frequency division, namely the 0 DEG and 90 DEG clocks generated by frequency division are respectively exclusive-ored with the first data clock signal to obtain the high level length of the result, which corresponds to the high 4 bits and the low 4 bits of the phase deviation result respectively, the phase discrimination function firstly calculates the time length from the rising edge of the first data clock signal to the rising edge of the frequency division clock signal, and secondly calculates the number of cycles of the frequency division clock signal, which is the number of cycles of the frequency division clock signal, in order to obtain the phase difference value, namely the number of cycles of which data output needs to delay.

And a time delay module: and the delay module is used for delaying the frequency division data clock signals taken out from the register module, and the period interval length of the delay is equal to the phase difference value of each frequency division clock signal and the first data clock signal calculated by the phase comparison module. In the system of the digital-to-analog converters, the frequency division results of each digital-to-analog converter are different, the clock generator ensures that the phase relation between the first data clock signal and the frequency division clock signal of each digital-to-analog converter is completely aligned, the phase condition of the four frequency divisions of the frequency division clock signal is calculated through the phase discriminator, the phase offset of the digital-to-analog converters and the default value of the phase difference value in the phase difference value relation table are compared, and the cycle value of each phase offset needing to be delayed can be determined, so that the aim of clock signal synchronization can be achieved.

Example 2

As shown in fig. 11, a digital-to-analog converter based multi-board synchronization method includes:

step S1: the method comprises the steps of inputting a reference clock signal into a multi-stage clock tree consisting of a plurality of clock generators, carrying out primary synchronization processing on the signal through two-stage clock generators in the multi-stage clock tree, detecting and converting the synchronization signal by using the clock generators, selecting corresponding clock sources according to different states of the synchronization signal, and synchronizing an external reference clock signal with an internal clock signal through a synchronization state machine. The first order HMC7044 clock generator is configured to perform a synchronization event in response to an externally or internally generated RFSYNC synchronization signal and to generate a 4-way single pulse RFSYNC synchronization signal to the second order HMC7044 clock generator. The second order HMC7044 clock generator is configured to respond to pulses of the external RFSYNC synchronization signal and to perform a synchronization event pattern. After the two-stage HMC7044 clock generator passes the synchronization event, the phase relationship of all output clock signals of the second stage is precisely synchronized with the external RFSYNC synchronization signal.

Step S2: and synchronously judging the synchronized data clock signals to confirm whether delay or retiming is needed, and outputting the synchronous data clock signals to a sampling clock port of a digital-to-analog converter, a first data clock port of the digital-to-analog converter and a second data clock port of an FPGA chip in the forms of a sampling clock signal, a first data clock signal and a second data clock signal on the FPGA clock synchronous system after judging. The 2.4G sampling clock signal and DCKI data clock of the LTC2000 digital-analog converter are from the HMC7044 clock generator on the design framework, and the clock for generating data of the FPGA is also from the input of the HMC7044 clock generator. When the configuration of the LTC2000 digital-analog converter and the clock synchronization are completed, the phase offset is read out but not compared, and the relevant phase difference value is directly written in according to the corresponding relation table.

Step S3: the reference processing data of the related digital-to-analog converter in the FPGA chip are respectively input into a first data input port and a second data input port of the digital-to-analog converter, and at the rising edge and the falling edge of a first data clock signal, two paths of reference processing data of the first data input port and the second data input port are sampled through the digital-to-analog converter. After the reference processing data is input in two ways from the first data input port and the second data input port, the digital-to-analog converter uses the rising edge and the falling edge of the first data clock signal to sample the two ways of data simultaneously.

Step S4: and then, respectively comparing the phases of the first data clock signal and the four-frequency-divided 0-degree clock and the four-frequency-divided 90-degree clock of the sampling clock signal through the digital-analog converter, adjusting the output delay of the digital-analog converter according to the result, and finally, accessing the analog signals output by the digital-analog converters into an oscilloscope to observe the synchronous result of a plurality of channels. The value of the delay period number N can be set by programming the phase difference value, and finally, the digital signal is converted into an analog signal to be output. After sampling is completed, 4 data are given to 4 in the digital-to-analog converter: 1MUX data area swap speed module. The module combines 4 data through a clock frequency division by CK4, and then uses 2.4G to beat N for output, wherein the sampling frequency is 2.4G/4/N, and the sampled data is transmitted and output through the clock frequency of 2.4G; and "N" represents the number of data bits output in a clock cycle of 2.4G. By this way of output, the module can transmit data at a higher rate while maintaining a lower clock frequency, thereby reducing the complexity of hardware design and control.

Further, the working method of the synchronous state machine comprises the following steps:

step A1: configuring parameters of each path of clocks of the first-order clock generator and the second-order clock generator, wherein the parameters comprise clock frequency, frequency division coefficient and delay period required by synchronization, entering a state waiting for starting a synchronous signal after the configuration is completed, performing parameter configuration correction after each configuration, and performing reconfiguration or parameter correction if normal transmission is not performed;

step A2: after receiving the start synchronizing signal, closing the clock channel capable of synchronizing so as to avoid the interference of the frequency divider of the enable synchronizing channel on the synchronizing signal, starting counting by the synchronizing counter, and waiting for the period counting of the synchronizing signal to be completed;

step A3: after the internal synchronous counter finishes counting, the clock channel and the pulse generator channel are started again, and pulse signals with different frequencies and phases are generated by the pulse generator according to the needs to finish synchronous pulses.

The main factors affecting the phase difference result are two: after the 2.4G sampling clock signal received by the single-chip LTC2000 digital-to-analog converter enters, 4 clock signals with different phases are generated after 4 frequency division, and each phase corresponds to the N value of different delay period numbers; the phase offset of the multiple LTC2000 digital-to-analog converters may cause the output signals of one digital-to-analog converter to differ by one period due to the difference in the input phase of the first data clock signal of each of the multiple LTC2000 digital-to-analog converters.

In specific operation, as shown in fig. 1-8, as a specific implementation manner, the first DATA clock signal is set to be DCKI, each divided clock signal is collectively referred to as CK, the first DATA input port and the second DATA input port are respectively set to be DA and DB ports, the reference processing DATA received by the DA and DB ports are respectively set to be DATA1 and DATA2, the phase offset is represented by PH value, the phase difference is represented by PS value, and two digital-to-analog converters ltc2000_x and ltc2000_y are set in the FPGA clock synchronization system. In particular implementations, as shown in fig. 6-7, assuming a 50ps error between the first data clock signals dcki_x and dcki_y input to two LTCs 2000, when the rising edge of the CK signal falls well between these 50ps, because the data and DCKI are perfectly aligned, it is known that the X chip must be output one beat later relative to the data in the Y chip 4:1mux, resulting in a difference in the final waveform of one 2.4G clock period. This fall of the CK signal rising edge just between 50ps can be reflected by the PH value, which is the result of comparing the delay ranges of DCKI and CK rising edges in LTC2000 chips, with DCKI being perfectly aligned by default in XY chips, DCKI being allowed a delay difference of 0.4 x 2.4ghz, and DCKI and edges of data being perfectly aligned. The synchronization mechanism of the LTC2000 needs to meet the three preconditions, and the synchronization mechanism of the chip is meaningful.

As shown in fig. 6-8, when the FPGA chip transmits reference processing data to the LTC2000 digital-to-analog converter, the data transmission is mainly performed by using 16 LVDS low voltage differential signaling channels, and the reference processing data, after entering the LTC2000 digital-to-analog converter, converts the 16 LVDS signals into single-ended signals and then sends the single-ended signals to a subsequent operation. The 16-way channel represents 16 lines, i.e. representing a 16-bit binary number, each line having a high or a low signal. When the system collects the rising edge of the data clock signal, according to the high level or low level signal collected on each line, recording '1' or '0' on each line, recording data by binary number, namely locking the level state of the digital-to-analog converter at the current moment by using the rising edge of DCKI by using the latch principle, and storing the data into Reg. D0 data of the DA port are collected at the rising edge of the DCKI, D1 data of the DB port are collected at the same time, D2 data of the DA port are collected at the falling edge of the DCKI, D3 data of the DB port are collected, and at the moment, the four data are output to a DAC module in a digital-to-analog converter through N beats of 2.4G and are output in an analog signal.

The principle of obtaining a 600M clock signal after the CK is divided by 4 times by a frequency division module in an LTC2000 digital-analog converter and the 2.4G sampling clock signal is that each rising edge of the 2.4G is counted, and the starting point of the counting is indeterminate when the power-on is started every time, so that 4 kinds of initial phase possibilities of 0 degree, 90 degree, 180 degree and 270 degree exist in the 600M. In the system of the multi-chip LTC2000 digital-to-analog converter, the frequency division results of each chip LTC2000 digital-to-analog converter are different, the DCKI and CK phase relation of each chip LTC2000 digital-to-analog converter is guaranteed to be completely aligned through each step hmc7044 clock generator, the phase condition of CK four frequency division is calculated through a phase discriminator, PS default values in the PH and PS relation tables of the multi-chip LTC2000 are directly taken out to be used for determining n values needing delay of each chip LTC2000, and the aim of synchronization can be achieved.

The first column represents the resulting PH value of the phase comparator output, and the 4 ranges of 0x03-0x25,0x35-0x53,0x52-0x30,0x20-0x02 represent the 4 phase relationships of the 2.4G sample clock signal divided by 4. The second column indicates the rising edge time interval of DCKI to CK, e.g., 0 to 0.2 indicates that the time delay range of DCKI to CK is one period of 0×ck to one period of 0.2×ck. The third column shows the default PS parameters that should be set for different phases after divide-by-4, without taking into account the multi-slice calibration. The fourth column shows the PS values that need to be adjusted after the comparison of the PH values of the plurality of sheets. As shown in fig. 9 and 10, there are a connection diagram of the digital-to-analog converter in the conventional means and a timing diagram in the special case, respectively. In the conventional practice, dcki_x and dcki_y are derived from the respective LTCs 2000, and no alignment can be guaranteed, but the phase difference between dcki_x and dcki_y can be guaranteed to be smaller than 0.4×ck through the constraint of the FPGA, now assuming that an error of 50ps exists between the input dcki_x and dcki_y of the two LTCs 2000, the PH values of the two LTCs 2000 are calculated by comparing the PH values after phase discrimination in practical terms, and the absolute value of the subtraction of the two values is larger than 0.4, which indicates that the rising edge of the CK signal falls between 50 ps. At this time, the PS value of the previous channel is reduced by one period according to the recommended PS value setting to complete synchronization, and the PH values of the LTCs 2000 are read out to the MCU to perform unified comparison calculation in the multi-chip system, which is very complex.

For this complex output manner through PS and PH calibration, in this embodiment, the DCKI input signal of the multiple LTCs 2000 is input through the external HMC7044, and by using the synchronization mechanism of the two-stage HMC7044, it is ensured that the DCKI and CK of the multiple LTCs 2000 are completely phase-aligned, the data DA and DB of the FPGA to the LTCs 2000 and the external DCKI are not completely aligned (because the data associated with the FPAG is not output to the LTCs 2000 together with the data, but is derived from the HMC 7044), and under this condition, the precondition of the synchronization mechanism of the DAC is no longer satisfied, so that this embodiment does not need to perform the PH value comparison of multiple slices or multiple boxes, and sets the PS value. In this embodiment, four frequency division of the 2.4G sampling clock signal in the LTC2000 generates clocks with 4 phases, and in this case, the PH value of each LTC2000 is read out, and the default PS parameters are written into the corresponding table according to the delay relationship between CK and DCKI, so that the problem of different frequency division phases of 4 phases can be solved.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the application, and is not meant to limit the scope of the application, but to limit the application to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the application are intended to be included within the scope of the application.

Claims (8)

1. A digital-to-analog converter based multi-board synchronous clock architecture, the clock architecture comprising:

multistage clock tree framework based on voltage controlled oscillators: the digital-to-analog converter comprises a digital-to-analog converter, a first data clock port, a second data clock port, a first clock signal and a second clock signal, wherein the first data clock port is used for carrying out multi-stage clock synthesis adjustment processing on a reference clock signal, and then generating multiple sampling clock signals and multiple data clock signals which are input into an FPGA clock synchronization system;

FPGA clock synchronization system based on digital-to-analog converter: the digital-to-analog converter comprises a plurality of digital-to-analog converters and an FPGA chip, wherein the digital-to-analog converters are used for inputting sampling clock signals and first data clock signals output by a multi-stage clock tree frame into the digital-to-analog converters, simultaneously inputting second data clock signals into the FPGA chip, respectively comparing phases of the first data clock signals and the four-divided 0-degree and 90-degree clocks of the sampling clock signals through the digital-to-analog converters, adjusting output delay of the digital-to-analog converters according to the results, finally accessing analog signals output by the digital-to-analog converters into an oscilloscope, and observing synchronous results of a plurality of channels.

2. The digital-to-analog converter based multi-board synchronous clock architecture of claim 1, wherein the multi-stage clock tree framework comprises a clock source, a first-order clock generator and a second-order clock generator connected in sequence, the clock source providing a reference clock signal for the first-order clock generator; the reference clock signal output by the clock source is output to the clock input port of the first-order clock generator.

3. The digital-to-analog converter based multi-plate synchronous clock architecture of claim 2, wherein the first-order clock generator outputs the advanced clock signal and the synchronous signal to the input terminal of the second-order clock generator through signal output; the second-order clock generator inputs the sampling clock signal, the first data clock signal and the second data clock signal to a sampling clock port of the digital-to-analog converter, a first data clock port of the digital-to-analog converter and a second data clock port of the FPGA chip respectively through signal output.

4. A digital to analog converter based multi-board synchronous clock architecture as claimed in claim 1, wherein in said FPGA clock synchronization system, each of said FPGA chips is capable of forming a set of data cells with at least one digital to analog converter, said multi-stage clock tree framework maintaining signal inputs of a sampling clock signal, a first data clock signal and a second data clock signal for each set of data cells.

5. The digital-to-analog converter based multi-plate synchronous clock architecture of claim 1, wherein the clock generator comprises:

and the acquisition selection module is used for: the synchronous signal acquisition device comprises a signal acquisition device and a synchronous selector, wherein the signal acquisition device is used for receiving an external synchronous signal and converting the external synchronous signal into a digital control signal, and the synchronous selector is used for selecting different clock sources to perform synchronous operation according to the state of the synchronous signal;

the synchronization generation module: the synchronous state machine is used for synchronizing an external reference clock signal with an internal data clock signal so as to realize synchronization and management of the clock signals;

and an output control module: including a retimer for delaying the signal and retiming the rising and falling edges of the signal and a clock gater for suspending or resuming the transmission of the clock signal when needed to reduce the overall power consumption of the chip.

6. The digital-to-analog converter based multi-plate synchronous clock architecture of claim 1, wherein the digital-to-analog converter comprises:

the frequency dividing module: the sampling clock signal is used for carrying out four frequency division on the received sampling clock signal, and the frequency-divided clock signals after frequency division are respectively named as clocks of 0 DEG, 90 DEG, 180 DEG and 270 DEG according to initial phases;

register module: the digital-to-analog converter is used for latching reference processing data input to the first data input port and the second data input port at the moment of rising edge or falling edge of the first data clock signal;

and the phase comparison module is used for: the method comprises the steps of calculating the phase difference value between each frequency-divided clock signal outputted after frequency division and a first data clock signal, and calculating the time length from the rising edge of the first data clock signal to the rising edge of a sampling clock signal;

and a time delay module: and the delay module is used for delaying the frequency division data clock signals taken out from the register module, and the period interval length of the delay is equal to the phase difference value of each frequency division clock signal and the first data clock signal calculated by the phase comparison module.

7. A digital-to-analog converter based multi-board synchronization method, comprising:

step S1: inputting a reference clock signal into a multi-stage clock tree consisting of a plurality of clock generators, performing primary synchronization processing on the signals through two-stage clock generators in the multi-stage clock tree, detecting and converting the synchronization signals by using the clock generators, selecting corresponding clock sources according to different states of the synchronization signals, and synchronizing an external reference clock signal with an internal clock signal through a synchronization state machine;

step S2: synchronizing the synchronized data clock signals to confirm whether delay or retiming is needed, and outputting the synchronized data clock signals to a sampling clock port of a digital-to-analog converter, a first data clock port of the digital-to-analog converter and a second data clock port of an FPGA chip in the forms of a sampling clock signal, a first data clock signal and a second data clock signal on an FPGA clock synchronizing system after the synchronization is finished;

step S3: respectively inputting reference processing data related to a digital-to-analog converter in an FPGA chip to a first data input port and a second data input port of the digital-to-analog converter, and simultaneously sampling two paths of reference processing data of the first data input port and the second data input port through the digital-to-analog converter at the rising edge and the falling edge of a first data clock signal;

step S4: and then, respectively comparing the phases of the first data clock signal and the four-frequency-divided 0-degree clock and the four-frequency-divided 90-degree clock of the sampling clock signal through the digital-analog converter, adjusting the output delay of the digital-analog converter according to the result, and finally, accessing the analog signals output by the digital-analog converters into an oscilloscope to observe the synchronous result of a plurality of channels.

8. The digital-to-analog converter based multi-plate synchronization method of claim 7, wherein said synchronization state machine operating method comprises:

step A1: configuring parameters of each path of clocks of the first-order clock generator and the second-order clock generator, wherein the parameters comprise clock frequency, frequency division coefficient and delay period required by synchronization, entering a state waiting for starting a synchronous signal after the configuration is completed, performing parameter configuration correction after each configuration, and performing reconfiguration or parameter correction if normal transmission is not performed;

step A2: after receiving the start synchronizing signal, closing the clock channel capable of synchronizing so as to avoid the interference of the frequency divider of the enable synchronizing channel on the synchronizing signal, starting counting by the synchronizing counter, and waiting for the period counting of the synchronizing signal to be completed;

step A3: after the internal synchronous counter finishes counting, the clock channel and the pulse generator channel are started again, and pulse signals with different frequencies and phases are generated by the pulse generator according to the needs to finish synchronous pulses.