CN108233906B - Starting-up deterministic delay system and method based on ADC - Google Patents
Starting-up deterministic delay system and method based on ADC Download PDFInfo
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- CN108233906B CN108233906B CN201810123329.5A CN201810123329A CN108233906B CN 108233906 B CN108233906 B CN 108233906B CN 201810123329 A CN201810123329 A CN 201810123329A CN 108233906 B CN108233906 B CN 108233906B
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
Abstract
The invention discloses a starting deterministic delay system and method based on ADC, relating to the technical field of time calibration and comprising the following steps: the reference clock source is connected with the power divider, the power divider is connected with the frequency synthesizer and the analog switch, the frequency synthesizer is connected with the ADC and the coherent synchronous address generator, the analog switch is connected with the target signal input port and the ADC, the ADC is connected with the buffer, the buffer is connected with the factory calibration memory, the delay numerical value calculation module and the delay compensation module, the coherent synchronous address generator is connected with the factory calibration memory, the factory calibration memory is connected with the delay numerical value calculation module, and the delay numerical value calculation module is connected with the delay compensation module; the invention has the advantages that: the self-calibration is carried out after the system is started, so that the delay of a data link in the system is kept unchanged after each start, the ranging precision of the phased array system is ensured, and complicated hardware correction networks, equipment quantity and hardware cost are not required to be increased.
Description
Technical Field
The invention relates to the technical field of time calibration, in particular to a starting deterministic delay system and method based on an ADC (analog to digital converter).
Background
In a modern phased array receiving system for radar and communication, the number of antenna units is large, the instantaneous bandwidth of a signal is large, and a plurality of high-speed Analog-to-Digital Converter (ADC) chips are required to complete Analog-to-Digital conversion of a received signal, so that wave velocity formation, interference resistance and other processing are performed in a Digital domain. In a large phased array system, the number of ADC chips is thousands or even tens of thousands, which are distributed among different subarray units, subsets, cards or modules. For a large-scale array data acquisition system of a high-speed ADC (analog to digital converter), a series of channel inconsistency differences such as clock power division, cable transmission, sampling aperture delay, phase skew of a phase-locked loop exist, so that the fixed establishment and retention time relation between an ADC data time sequence and a signal processing clock is difficult to satisfy, the signal processing clock cannot be directly adopted to synchronize data, and only a data buffer (such as an FIFO (first in first out) or a dual-port RAM) is used for realizing clock-domain-crossing conversion of the ADC data. Due to the uncertain phase relationship between the ADC clock and the signal processing clock, there is uncertainty in data delay of 0 or 1 clock cycle when using the data buffer to synchronize data, i.e. the absolute delay of each on/off link is not fixed. Even if an ADC chip based on a deterministic delay protocol (e.g., JESD204B) is used, only the transmission delay determination at individual single board and chassis level can be realized, and it is difficult to realize the transmission delay determination of all chassis or extension sets, the fundamental reason is that it is difficult to ensure that the synchronization signals sent to each ADC of the whole system and the ADC sampling clock meet the requirements of setup and hold time at the same time.
The uncertainty of the startup data link delay seriously restricts the ranging accuracy of the phased array system, and the traditional method is based on an additional correction link, and a receiving and transmitting closed-loop correction method is adopted to measure a system self-closing loop delay value for reference when the phased array system is started every time. The disadvantage is that a complex hardware correction network is required to be added, the equipment amount and the hardware cost are increased, the influence on a large-scale system is particularly obvious, and some systems do not allow a receiving and transmitting closed-loop correction flow to be adopted by a receiver every time the receiver is started so as not to influence the normal execution of tasks.
Disclosure of Invention
The invention aims to solve the technical problem that the delay of a data link in a system is uncertain when the data link is started up each time.
The invention solves the technical problems through the following technical scheme, and the specific technical scheme is as follows:
a starting up deterministic delay system and method based on ADC includes: the device comprises a reference clock source (1), a target signal input port, a power divider (2), a frequency synthesizer (3), an analog switch (4), an ADC (5), a buffer (6), a coherent synchronous address generator (7), a factory calibration memory (8), a delay value calculation module (9) and a delay compensation module (10); the reference clock source (1) is connected with the power divider (2), the power divider (2) is connected with the frequency synthesizer (3) and the analog switch (4), the frequency synthesizer (3) is connected with the ADC (5) and the coherent synchronous address generator (7), the analog switch (4) is connected with the target signal input port and the ADC (5), the ADC (5) is connected with the buffer (6), the buffer (6) is connected with the factory calibration memory (8), the delay numerical value calculation module (9) and the delay compensation module (10), the coherent synchronous address generator (7) is connected with the factory calibration memory (8), the factory calibration memory (8) is connected with the delay value calculation module (9), the delay numerical value calculation module (9) is connected with the delay compensation module (10).
Preferably, the working phase of the system comprises: a preparation stage, a delivery stage, a startup calibration stage and a working stage;
the preparation stage generates information of a memory read-write address of a frequency multiplication clock, a delay calibration reference signal and a reference clock source which are synchronous in phase;
the delivery stage acquires and stores the time delay calibration parameters at one time;
the starting calibration stage calibrates the time delay of the data link;
and the working stage adjusts the time delay of the data link according to the calibration result.
Preferably, the frequency synthesizer (3) outputs 2 paths of M-multiplied analog reference clock signals and 1 path of 1-multiplied analog reference clock signals, wherein the 1 path of M-multiplied analog reference clock signals is used as a sampling clock (b) of the ADC (5) and transmits the signals to the ADC (5), and the other 1 path of M-multiplied analog reference clock signals and 1 path of 1-multiplied analog reference clock signals are used as a system clock (c) and a reference clock (e) and transmit the 2 paths of signals to the coherent synchronous address generator (7).
Preferably, the buffer (6) switches the data (g) collected by the ADC (5) between a sampling clock domain and a system clock domain, and the write-in side clock of the buffer (6) is the data channel clock (h) of the ADC (5) and the read-out side clock is the system clock (c).
Preferably, the analog switch (4) selects a signal output by the power divider (2) as the ADC (5) input signal in a factory stage and a power-on calibration stage, and selects a signal output by the target signal input port as the ADC (5) input signal in an operating stage.
Preferably, the delay value calculation module (9) comprises a first register (9-1), a second register (9-2), a first error mean square value calculation module (9-3), a second error mean square value calculation module (9-4), a third error mean square value calculation module (9-5) and a delay value decision module (9-6); the buffer (6) is connected to the first register (9-1) and the first error mean square value calculation module (9-3), the factory calibration memory (8) is connected to the first error mean square value calculation module (9-3), the second error mean square value calculation module (9-4) and the third error mean square value calculation module (9-5), the first register (9-1) is connected to the second error mean square value calculation module (9-4) and the second register (9-2), the second register (9-2) is connected to the third error mean square value calculation module (9-5), and the first error mean square value calculation module (9-3), the second error mean square value calculation module (9-4) and the third error mean square value calculation module (9-5) are all connected to the delay value decision module (9-5) 9-6) connection.
Preferably, the delay compensation module (10) comprises a fourth register (10-1), a fifth register (10-2) and a data selector (10-3), the fourth register (10-1) is connected with the fifth register (10-2) and the data selector (10-3), and the fifth register (10-2) is connected with the data selector (10-3).
Preferably, the number of delay cycles used in each of the factory calibration memory (8), the delay value calculation module (9) and the delay compensation module (10) is determined based on the characteristic that each time the data is switched in the clock domain through the buffer (6) during startup, the delay uncertainty of one cycle is present.
A startup deterministic delay method based on ADC (analog to digital converter), the working phase of the system comprises: a preparation stage, a delivery stage, a startup calibration stage and a working stage; the working method of the system comprises the following steps:
s1, a preparation stage:
s1.1, dividing an analog reference clock signal (a) generated by a reference clock source (1) with the frequency of K into two paths of analog sinusoidal signals through a power divider (2);
s1.2, after the first path of analog sinusoidal signals generated in the step S1.1 passes through a frequency synthesizer (3), M times of frequency multiplication analog sinusoidal signals are output as a sampling clock (b) and a system clock (c) of an ADC (5), and 1 time of frequency multiplication analog sinusoidal signals are output as a reference clock (e) with the frequency of K; inputting the second path of analog sinusoidal signal into an analog switch (4) as a delay calibration reference signal (d);
s1.3, synchronizing the reference clock (e) with the frequency of K generated in the step S1.2 to a system clock domain to serve as a counter synchronization control signal, taking any rising edge of the reference clock (e) as a counter starting time, using a system clock to generate a cycle counter with the cycle of M, counting from 0 to M-1 in each cycle and stepping to 1, and taking the value (i) of the cycle counter as a read-write address of a factory calibration memory (8);
s2, entering a factory leaving stage:
using an analog switch (4) to select and input the delay calibration reference signal (d) generated in the step S1.2 into an ADC (5) for collection, and inputting collected data (g) into a buffer (6) for clock domain conversion, so that the data is converted from a sampling clock domain to a system clock domain; storing data (p) output by M continuous buffers into a factory calibration memory (8) at one time after delaying for one clock period to serve as a delay calibration parameter (q), and taking a cycle counter value (i) in the step S1.3 as a write address when the parameter is written into the factory calibration memory (8);
s3, entering a starting calibration stage:
s3.1, after restarting, using an analog switch (4) to input the delay calibration reference signal (d) generated in the step S1.2 into an ADC (5) for collection, and inputting collected data (g) into a buffer (6) for clock domain conversion, so that the data is converted from a sampling clock domain to a system clock domain;
s3.2, dividing data (p) output by the buffer (6) into three paths, wherein when the delay calibration parameters are read from the factory calibration memory (8) in each clock period, the value (i) of the cycle counter in the step S1.3 is used as a read address; the delay numerical value calculation module (9) calculates a delay index value N and gives the delay index value N according to the calculated data, namely 0,1 and 2; the delay compensation module (10) carries out delay compensation on the data output by the buffer (6) according to the delay index value N and outputs deterministic delay data;
s4, entering a working stage:
s4.1, selecting a target signal (f) output by a target signal input port by using an analog switch (4), inputting the target signal (f) into an ADC (5) for collection, inputting collected data (g) into a buffer (6) for clock domain conversion, and converting the data from a sampling clock domain to a system clock domain;
and S4.2, delaying the data (p) output by the buffer (6) by N system clock cycles according to the delay index value N determined in the step S3.3, and then outputting the data (k).
Preferably, the working process of the delay value calculation module includes:
delaying data (p) output by the buffer (6) by 0 clock cycle, delaying by 1 clock cycle of the register (9-1) and delaying by 2 clock cycles of the registers (9-1) and (9-2);
respectively calculating error mean square values of 0 period delay, one period delay and two period delays and a delay calibration parameter (q) through an error mean square value calculation module (9-3), an error mean square value calculation module (9-4) and an error mean square value calculation module (9-5);
and a delay index value N, namely 0,1,2 and 3 is given out through a delay value judgment module (9-6) according to the minimum value of the three error mean square values, and meanwhile, the analog switch (4) is informed to switch the input signal of the ADC (5) into a target signal (f) input by a target signal input port.
Compared with the prior art, the invention has the following advantages:
(1) in the factory stage and the startup calibration stage, because the delay calibration parameter signal is coherent with the value of the coherent synchronous address generator and is in periodic synchronization, the minimum mean square error value means that the delay of the data link passing through the delay calibration stage is the same as the delay of the data link in the factory stage, so that the delay of the data link passing through the delay calibration after each startup is the same as the factory time, namely the data link has deterministic delay.
(2) The system of the invention does not need to increase complex hardware correction network, equipment amount and hardware cost, can be widely applied to large-scale systems, and does not influence the normal execution of tasks.
Drawings
Fig. 1 is a block diagram of a configuration of a startup deterministic latency system based on an ADC according to an embodiment of the present invention.
Fig. 2 is a block diagram of a delay value calculation module in the ADC-based boot deterministic delay system according to an embodiment of the present invention.
Fig. 3 is a block diagram of a delay compensation module in the ADC-based boot deterministic delay system according to an embodiment of the present invention.
Fig. 4 is a flowchart illustrating the operation of the ADC-based boot deterministic latency system according to an embodiment of the present invention.
Detailed Description
The following examples are given for the detailed implementation and specific operation of the present invention, but the scope of the present invention is not limited to the following examples.
As shown in fig. 1, an ADC-based boot deterministic delay apparatus includes a reference clock source 1, a target signal input port, a power divider 2, a frequency synthesizer 3, an analog switch 4, an ADC5, a buffer 6, a coherent synchronous address generator 7, a factory calibration memory 8, a delay value calculation module 9, and a delay compensation module 10; the reference clock source 1 is connected with the power divider 2, the power divider 2 is connected with the frequency synthesizer 3 and the analog switch 4, the frequency synthesizer 3 is connected with the ADC5 and the coherent synchronous address generator 7, the analog switch 4 is connected with the target signal input port and the ADC5, the ADC5 is connected with the buffer 6, the buffer 6 is connected with the factory calibration memory 8, the delay value calculation module 9 and the delay compensation module 10, the coherent synchronous address generator 7 is connected with the factory calibration memory 8, the factory calibration memory 8 is connected with the delay value calculation module 9, and the delay value calculation module 9 is connected with the delay compensation module 10.
The reference clock source 1 is used for generating an analog reference clock signal a with a frequency of K, a typical value range of K is 10 MHz-25 MHz, and generally comprises an oscillator with low phase noise and high frequency stability, wherein K is 10MHz in the embodiment; the analog reference clock signal a is used for a finally generated system clock c, a sampling clock b of the ADC, a delay calibration reference signal d and a reference clock e; the target signal f to be collected by the ADC5 in the system is input from a target signal input port;
the power divider 2 is used for dividing the analog reference clock signal a generated by the reference clock source 1 into two paths, the first path is used for generating a sampling clock b, a system clock c and a reference clock e of the ADC5, and the second path is used as a delay calibration reference signal d;
the frequency synthesizer 3 generates three paths of output clock signals based on an analog reference clock signal a, wherein M times of frequency of the analog reference clock signal a is used as a sampling clock b and a system clock c of the ADC5, 1 time of frequency of the analog reference clock signal a is used as a reference clock e, a typical value range of M is an integer between 2 and 30, and M is 24 in the embodiment; the 1 path of M-multiplied analog reference clock signal is used as a sampling clock b of the ADC5 and transmitted to the ADC5, and the other 1 path of M-multiplied analog reference clock signal and the 1 path of 1-multiplied analog reference clock signal are used as a system clock c and a reference clock e, and transmit the 2 paths of signals to the coherent synchronous address generator 7.
The analog switch 4 is used for selecting the signal input of the ADC5, selecting the delay calibration reference signal d as the input signal of the ADC5 in the factory stage and the power-on calibration stage, and selecting the target signal f as the input signal of the ADC5 in the working stage.
The ADC5 is used to perform analog-to-digital conversion of the input signal, in this embodiment at a sampling rate of 240MSps, LVDS data bus interface.
The buffer 6 is used for converting the data g acquired by the ADC5 between a sampling clock domain and a system clock domain, the write-in side clock of the buffer 6 is the data channel clock h of the ADC5, and the read-out side clock is the system clock c; the buffer 6 is generally composed of a dual port RAM or FIFO, which is a dual port RAM in this embodiment. The data p output by the buffer 6 is divided into 3 paths, the first path of data p is transmitted to the factory calibration memory 8, the second path of data p is transmitted to the delay value calculation module 9, and the third path of data p is transmitted to the delay compensation module.
The coherent synchronous address generator 7 is configured to synchronize a reference clock generated by the frequency synthesizer 3 to a system clock domain to serve as a counter synchronization control signal, use any rising edge of the reference clock e as a counting start time, use the system clock to generate a cyclic counter with a count value of 0 to 23, and use the counter value as a read-write address of the factory calibration memory 8; according to the structure, the cyclic counter is coherent and synchronous in period with the delay calibration reference signal d output by the power divider 6, the count value of the cyclic counter is used as the read-write address of the factory calibration memory 8, and the address is coherent and synchronous in period with the delay calibration reference signal d.
The factory calibration memory 8 is used for storing data output by the continuous M buffers at one time as a delay calibration parameter in a factory stage, a clock period is needed for delay registration before the parameter is written into the factory calibration memory 8, and a counter value of the coherent synchronous address generator is used as a write address when the parameter is written into the factory calibration memory 8; in the startup calibration stage, the method is used for reading out continuous M stored values as delay calibration parameters of the delay value calculation module 9 at one time by taking the counter value of the coherent synchronous address generator 7 as a read address; in this embodiment, 24 delay calibration parameter values are stored in the factory calibration memory 8, and the factory calibration memory 8 outputs data q.
The delay value calculation module 9 is configured to calculate a delay index value N according to the data output by the buffer 6 and the delay calibration parameter in the startup calibration stage; as shown in fig. 2, the delay value calculation module 9 includes a register 9-1, a register 9-2, an error mean square value calculation module 9-3, an error mean square value calculation module 9-4, an error mean square value calculation module 9-5, and a delay value decision module 9-6; the buffer 6 is connected with a register 9-1 and an error mean square value calculation module 9-3, the factory calibration memory 8 is connected with the error mean square value calculation module 9-3, the error mean square value calculation module 9-4 and the error mean square value calculation module 9-5, the register 9-1 is connected with the error mean square value calculation module 9-4 and a register 9-2, the register 9-2 is connected with the error mean square value calculation module 9-5, and the error mean square value calculation module 9-3, the error mean square value calculation module 9-4 and the error mean square value calculation module 9-5 are all connected with the delay numerical value judgment module 9-6. The data p output by the buffer 6 is delayed by 0 clock cycle, delayed by 1 clock cycle of the register 9-1 and delayed by 2 clock cycles of the registers 9-1 and 9-2; respectively calculating error mean square values between 0 period delay, one period delay and two period delays and a delay calibration parameter q output by a factory calibration memory 8 through an error mean square value calculation module 9-3, an error mean square value calculation module 9-4 and an error mean square value calculation module 9-5; the delay value decision module 9-6 gives a delay index value N, i.e. 0,1,2, according to the minimum value of the three error mean square values, and simultaneously informs the analog switch 4 to switch the input signal of the ADC5 to the target signal f, so that the operating state of the system is switched from the factory stage or the power-on calibration stage to the operating stage.
The delay compensation module 10 is configured to perform delay compensation on the data p output by the buffer 6 according to the delay index value N in a working stage, and output data with deterministic delay; as shown in fig. 3, the delay compensation module 10 includes a register 10-1, a register 10-2, and a data selector 10-3, the register 10-1 is connected to the register 10-2 and the data selector 10-3, and the register 10-2 is connected to the data selector 10-3. The register 10-1 and the register 10-2 are used for delaying the data p output by the buffer 6 by one or two clock cycles, and the data selector 10-3 selects three data, which are not delayed and delayed by one or two clock cycles, as the output data k according to the data j of the delay index value N.
The working state of the system is divided into a preparation stage, a delivery stage, a startup calibration stage and a working stage; generating signals such as a frequency doubling clock, a delay calibration reference signal and a memory read-write address synchronous with the phase of the reference clock source in a preparation stage, obtaining and storing delay calibration parameters at one time in a factory stage, calibrating the delay of a data link in a startup calibration stage, and adjusting the delay of the data link according to a calibration result in a working stage.
As can be seen from the system structure, in the factory stage and the startup calibration stage, since the delay calibration reference signal d is coherent with the value of the coherent synchronization address generator 7 and is periodically synchronized, the minimum mean square error value means that the data link passed through by the data in the delay calibration stage is the same as the data link delay in the factory stage, and therefore the data link delay after the delay calibration after each startup is the same as the factory time, that is, the data link has deterministic delay. The working clocks of the data reading side of the buffer 6, the factory calibration memory 8, the delay value calculation module 9 and the delay compensation module 10 are not shown, and the working clocks are system clocks.
It should be noted that the number of delay cycles used in the factory calibration memory 8, the delay value calculation module 9, and the delay compensation module 10 is determined based on the characteristic that the delay uncertainty of one cycle is present when the data is converted into the clock domain through the buffer 6 at each time of starting. Besides analog or analog-digital mixed modules such as a reference clock source 1, an analog switch 4, an ADC5 and the like, other functional modules in the system are easy to realize in a programmable logic device, and the system can also be realized in other modes such as an application-specific integrated circuit, a discrete device circuit and the like.
As shown in fig. 4, in the startup deterministic delay method based on ADC of the present invention, the working phase of the system includes: a preparation stage, a delivery stage, a startup calibration stage and a working stage; the working method of the system comprises the following steps:
s1, a preparation stage:
s1.1, dividing an analog reference clock signal a generated by a reference clock source 1 with the frequency of K into two paths of analog sinusoidal signals through a power divider 2;
s1.2, after the first path of analog sinusoidal signals generated in the step S1.1 passes through a frequency synthesizer 3, M times of frequency multiplication analog sinusoidal signals are output as a sampling clock b and a system clock c of the ADC5, and 1 time of frequency multiplication analog sinusoidal signals are output as a reference clock e with the frequency of K; inputting the second path of analog sinusoidal signal into the analog switch 4 as a delay calibration reference signal d;
s1.3, synchronizing the reference clock e with the frequency of K generated in the step S1.2 to a system clock domain to serve as a counter synchronization control signal, taking any rising edge of the reference clock e as the starting time of a counter, using a cycle counter with the system clock generation period of M, counting from 0 to M-1 per period and stepping to 1, and taking the value i of the cycle counter as the read-write address of a factory calibration memory 8;
s2, entering a factory leaving stage:
using an analog switch 4 to select to input the delay calibration reference signal d generated in the step S1.2 into an ADC5 for collection, and inputting collected data g into a buffer 6 for clock domain conversion, so that the data is converted from a sampling clock domain to a system clock domain; the data p output by the M continuous buffers is stored into the factory calibration memory 8 once after the delay of one clock period as a delay calibration parameter q, and when the parameter is written into the factory calibration memory 8, the value i of the cycle counter in the step S1.3 is used as a write address;
s3, entering a starting calibration stage:
s3.1, after restarting, the analog switch 4 is still used for selecting to input the delay calibration reference signal d generated in the step S1.2 into the ADC5 for collection, and input the collected data g into the buffer 6 for clock domain conversion, so that the data is converted from a sampling clock domain to a system clock domain;
s3.2, dividing data p output by the M continuous buffers into three paths, wherein when the delay calibration parameters are read from the factory calibration memory 8 in each clock period, the value i of the cycle counter in the step S1.3 is used as a read address; the delay numerical value calculation module 9 calculates a delay index value N and gives the delay index value N, i.e., 0,1,2, according to the calculated data; the delay compensation module 10 performs delay compensation on the data output by the buffer 6 according to the delay index value N, and outputs deterministic delay data;
s4, entering a working stage:
s4.1, selecting a target signal f output by a target signal input port by using an analog switch 4, inputting the target signal f into an ADC5 for collection, inputting collected data g into a buffer 6 for clock domain conversion, and converting the data from a sampling clock domain to a system clock domain;
and S4.2, delaying the data p output by the buffer 6 by N system clock cycles according to the delay index value N determined in the step S3.3, and then outputting data k.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. An ADC-based boot deterministic latency system, comprising: the device comprises a reference clock source (1), a target signal input port, a power divider (2), a frequency synthesizer (3), an analog switch (4), an ADC (5), a buffer (6), a coherent synchronous address generator (7), a factory calibration memory (8), a delay value calculation module (9) and a delay compensation module (10);
the reference clock source (1) is connected with the power divider (2), and the reference clock source (1) outputs an analog reference clock signal to the power divider (2);
the power divider (2) is connected with the frequency synthesizer (3) and the analog switch (4), and the output of the power divider (2) is respectively sent to the frequency synthesizer (3) and the analog switch (4) as input signals;
the frequency synthesizer (3) is connected with the ADC (5) and the coherent synchronous address generator (7), and the frequency synthesizer (3) outputs a sampling clock to the ADC (5) and outputs a system clock and a reference clock to the coherent synchronous address generator (7);
the analog switch (4) is connected with the target signal input port and the ADC (5), a second path of input signal of the analog switch (4) comes from the target signal input port, and an output signal is sent to the ADC (5);
the ADC (5) is connected with the buffer (6), and the ADC (5) outputs acquired data and a data channel associated clock to the buffer (6);
the buffer (6) is connected with the factory calibration memory (8), the delay numerical value calculation module (9) and the delay compensation module (10), and the buffer (6) outputs data to the factory calibration memory (8), the delay numerical value calculation module (9) and the delay compensation module (10);
the coherent synchronous address generator (7) is connected with the factory calibration memory (8), and the coherent synchronous address generator (7) outputs a cycle counter value to the factory calibration memory (8);
the factory calibration memory (8) is connected with the delay value calculation module (9), and the factory calibration memory (8) outputs the delay calibration parameters to the delay value calculation module (9);
the delay numerical value calculation module (9) is connected with the delay compensation module (10), and the delay numerical value calculation module (9) outputs a delay index value to the delay compensation module (10).
2. The ADC-based boot deterministic latency system of claim 1, wherein the operational phase of the system comprises: a preparation stage, a delivery stage, a startup calibration stage and a working stage;
the preparation stage generates information of a memory read-write address of a frequency multiplication clock, a delay calibration reference signal and a reference clock source which are synchronous in phase;
the delivery stage acquires and stores the time delay calibration parameters at one time;
the starting calibration stage calibrates the time delay of the data link;
and the working stage adjusts the time delay of the data link according to the calibration result.
3. The ADC-based boot deterministic delay system of claim 1 wherein the frequency synthesizer (3) outputs 2M-times multiplied analog reference clock signals and 1-times multiplied analog reference clock signal, wherein the 1M-times multiplied analog reference clock signal is used as the sampling clock (b) of the ADC (5) and transmits the signal to the ADC (5), and the other 1M-times multiplied analog reference clock signal and 1-times 1 analog reference clock signal are used as the system clock (c) and the reference clock (e) and transmit 2 signals to the coherent synchronous address generator (7).
4. The ADC-based boot deterministic latency system of claim 1, wherein the buffer (6) switches the data (g) collected by the ADC (5) between a sampling clock domain and a system clock domain, wherein the buffer (6) writes the data associated clock (h) of the ADC (5) and reads the system clock (c).
5. The ADC-based boot deterministic delay system of claim 2 wherein the analog switch (4) selects the signal output from the power divider (2) as the ADC (5) input signal during the factory-shipping phase and the boot calibration phase, and selects the signal output from the target signal input port as the ADC (5) input signal during the working phase.
6. The ADC-based boot deterministic delay system of claim 1 wherein the delay value calculation module (9) comprises a first register (9-1), a second register (9-2), a first error mean square value calculation module (9-3), a second error mean square value calculation module (9-4), a third error mean square value calculation module (9-5) and a delay value decision module (9-6); the buffer (6) is connected to the first register (9-1) and the first error mean square value calculation module (9-3), the factory calibration memory (8) is connected to the first error mean square value calculation module (9-3), the second error mean square value calculation module (9-4) and the third error mean square value calculation module (9-5), the first register (9-1) is connected to the second error mean square value calculation module (9-4) and the second register (9-2), the second register (9-2) is connected to the third error mean square value calculation module (9-5), and the first error mean square value calculation module (9-3), the second error mean square value calculation module (9-4) and the third error mean square value calculation module (9-5) are all connected to the delay value decision module (9-5) 9-6) connection.
7. An ADC-based boot deterministic latency system according to claim 1, characterized in that the latency compensation module (10) comprises a fourth register (10-1), a fifth register (10-2) and a data selector (10-3), the fourth register (10-1) is connected with the fifth register (10-2) and the data selector (10-3), and the fifth register (10-2) is connected with the data selector (10-3).
8. The ADC-based boot deterministic delay system of claim 1 wherein the number of delay cycles used in each of the factory calibration memory (8), the delay value calculation module (9) and the delay compensation module (10) is determined based on the one cycle delay uncertainty per clock domain conversion of the boot data by the buffer (6).
9. An ADC-based boot deterministic delay method using the system of any of claims 1 to 8, wherein the system is operated by: a preparation stage, a delivery stage, a startup calibration stage and a working stage; the working method of the system comprises the following steps:
s1, a preparation stage:
s1.1, dividing an analog reference clock signal (a) generated by a reference clock source (1) with the frequency of K into two paths of analog sinusoidal signals through a power divider (2);
s1.2, after the first path of analog sinusoidal signals generated in the step S1.1 passes through a frequency synthesizer (3), M times of frequency multiplication analog sinusoidal signals are output as a sampling clock (b) and a system clock (c) of an ADC (5), and 1 time of frequency multiplication analog sinusoidal signals are output as a reference clock (e) with the frequency of K; inputting the second path of analog sinusoidal signal into an analog switch (4) as a delay calibration reference signal (d);
s1.3, synchronizing the reference clock (e) with the frequency of K generated in the step S1.2 to a system clock domain to serve as a counter synchronization control signal, taking any rising edge of the reference clock (e) as a counter starting time, using a system clock to generate a cycle counter with the cycle of M, counting from 0 to M-1 in each cycle and stepping to 1, and taking the value (i) of the cycle counter as a read-write address of a factory calibration memory (8);
s2, entering a factory leaving stage:
using an analog switch (4) to select and input the delay calibration reference signal (d) generated in the step S1.2 into an ADC (5) for collection, and inputting collected data (g) into a buffer (6) for clock domain conversion, so that the data is converted from a sampling clock domain to a system clock domain; storing data (p) output by M continuous buffers into a factory calibration memory (8) at one time after delaying for one clock period to serve as a delay calibration parameter (q), and taking a cycle counter value (i) in the step S1.3 as a write address when the parameter is written into the factory calibration memory (8);
s3, entering a starting calibration stage:
s3.1, after restarting, using an analog switch (4) to input the delay calibration reference signal (d) generated in the step S1.2 into an ADC (5) for collection, and inputting collected data (g) into a buffer (6) for clock domain conversion, so that the data is converted from a sampling clock domain to a system clock domain;
s3.2, dividing data (p) output by the buffer (6) into three paths, wherein when the delay calibration parameters are read from the factory calibration memory (8) in each clock period, the value (i) of the cycle counter in the step S1.3 is used as a read address; the delay numerical value calculation module (9) calculates a delay index value N and gives the delay index value N according to the calculated data, namely 0,1 and 2; the delay compensation module (10) carries out delay compensation on the data output by the buffer (6) according to the delay index value N and outputs deterministic delay data;
s4, entering a working stage:
s4.1, selecting a target signal (f) output by a target signal input port by using an analog switch (4), inputting the target signal (f) into an ADC (5) for collection, inputting collected data (g) into a buffer (6) for clock domain conversion, and converting the data from a sampling clock domain to a system clock domain;
and S4.2, delaying the data (p) output by the buffer (6) by N system clock cycles according to the delay index value N determined in the step S3.3, and then outputting the data (k).
10. The ADC-based boot deterministic delay method of claim 9, wherein the operation of the delay value calculating module comprises:
delaying data (p) output by the buffer (6) by 0 clock cycle, delaying by 1 clock cycle of the register (9-1) and delaying by 2 clock cycles of the registers (9-1) and (9-2);
respectively calculating error mean square values of 0 period delay, one period delay and two period delays and a delay calibration parameter (q) through an error mean square value calculation module (9-3), an error mean square value calculation module (9-4) and an error mean square value calculation module (9-5);
and a delay index value N, namely 0,1,2 and 3 is given out through a delay value judgment module (9-6) according to the minimum value of the three error mean square values, and meanwhile, the analog switch (4) is informed to switch the input signal of the ADC (5) into a target signal (f) input by a target signal input port.
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