CN109032498B - Waveform quantization synchronization method of multi-FPGA multi-channel acquisition system - Google Patents

Waveform quantization synchronization method of multi-FPGA multi-channel acquisition system Download PDF

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CN109032498B
CN109032498B CN201810826384.0A CN201810826384A CN109032498B CN 109032498 B CN109032498 B CN 109032498B CN 201810826384 A CN201810826384 A CN 201810826384A CN 109032498 B CN109032498 B CN 109032498B
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CN109032498A (en
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杨扩军
赵禹
叶芃
黄武煌
谭峰
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract

The invention discloses a waveform quantization synchronization method of a multi-FPGA multi-channel acquisition system, which comprises the steps of firstly generating a reset signal of a first ADC by a DSP and resetting hardware of the first ADC, then sequentially generating an asynchronous reset signal of a next ADC by the DSP, synchronizing the asynchronous reset signal of each ADC to a data synchronous clock domain of a previous ADC by a D trigger to generate a synchronous reset signal under the clock domain, then adjusting an input/output delay unit in the FPGA to enable the asynchronous reset signal not to be positioned in a metastable state interval under the data synchronous clock domain of the previous ADC, resetting the ADC by the synchronous reset signal, finally correcting a fixed phase difference among the ADCs, and completing waveform quantization synchronization.

Description

Waveform quantization synchronization method of multi-FPGA multi-channel acquisition system
Technical Field
The invention belongs to the technical field of data acquisition, and particularly relates to a waveform quantization synchronization method of a multi-FPGA multi-channel acquisition system.
Background
The multi-channel acquisition system is widely applied to various industrial and commercial fields, and particularly in the test field, the phase relation of signals among channels is often required to be acquired, so that the acquisition system not only has the capability of acquiring the signal information of the channels, but also can acquire the correlation information among the channels. This requires a synchronous processing of the acquisition system of multiple channels. In the acquisition system after synchronous processing, the phase difference does not exist between the acquired data after the same signal is input into the two channels.
The FPGA (Field-Programmable Gate Array) as a real-time processing device has the characteristics of high performance, high integration, high flexibility and low density, and provides strong support for a high-speed acquisition system. Along with the continuous development of electronic information technology, the requirements of various products and projects on the performance of a high-speed acquisition system are higher and higher, the index requirements of the high-speed acquisition system cannot be met by a traditional single ADC and a single FPGA, the sampling rate of a single ADC cannot meet the requirements of the acquisition system, the establishment of the high-speed acquisition system usually requires multiple ADCs to be established together to improve the sampling rate of the whole system, the use of the multiple ADCs causes the phenomenon that resources are insufficient inside one FPGA, and the acquisition system usually needs to use a system structure of multiple ADCs and multiple FPGAs due to the consideration of the current hardware manufacturing level and cost control, but the structure brings difficulty for the waveform quantization synchronization of the acquisition system.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a waveform quantization synchronization method of a multi-FPGA multi-channel acquisition system, which realizes the synchronization of the waveform quantization of the multi-channel acquisition system under a multi-ADC + multi-FPGA architecture, thereby ensuring that different ADCs have the same-phase quantization output when the same analog signal is quantized simultaneously.
In order to achieve the above object, the present invention provides a waveform quantization synchronization method for a multi-FPGA multi-channel acquisition system, comprising the following steps:
(1) DSP generates a first ADC1Reset signal SYNC of1DSP and will SYNC1The DSP is used as a hardware reset signal and sent to the first ADC1Resetting it to make the first ADC chip1Generating data synchronous clock signal DCLK1Connected to the FPGA through interconnection lines at the same time2An IO port of;
(2) ADC to be first chip1After reset is completed, DSP generates 2 nd ADC2Asynchronous reset signal SYNC2DSP sends to FPGA2And reuse of FPGA2The middle D trigger sends an asynchronous reset signal SYNC sent by the DSP2DSP synchronization to DCLK1Under the clock domain, DCLK is generated1Clock domain down ADC2Synchronous reset signal SYNC2；
(3) And judging the asynchronous reset signal SYNC2Whether DSP is in DCLK1Metastable state interval in clock domain, if it is, entering step(4) Otherwise, entering the step (5);
(4) adjusting the delay value of the delay module
Augmenting an FPGA2The delay value of the input/output delay unit is changed, thereby changing the FPGA2The delay of the input port enables the asynchronous reset signal SYNC sent by the DSP2DSP does not fall into ADC1Data synchronization clock DCLK1In the metastable state interval, returning to the step (3);
(5) ADC reset
Will FPGA2Synchronous reset signal SYNC generated by middle D flip-flop2As ADCs2By means of the FPGA2Is sent to the ADC2Resetting the reset port, and generating the ADC after the resetting is finished2Data synchronization clock DCLK2And is connected to the FPGA3And (3) returning to the step (2);
then analogize in turn, for ADC3Reset operation is carried out until all ADCsiResetting is completed, i is 1,2, …, and M is the number of ADCs;
(6) correcting fixed phase difference by software
The signal source signal is passed through a power divider, two coaxial lines with identical length are connected into two ADCs of an acquisition system, the number of lost points of a data receiving buffer area in software is regulated by using a first ADC as a reference, so that the output waveforms of the two ADCs are completely overlapped, namely, the fixed phase difference between the two ADCs is corrected, each ADC is sequentially calibrated, the fixed phase difference between the ADCs is eliminated one by one, and the waveform quantization synchronization of the whole system is completed.
The invention aims to realize the following steps:
the invention relates to a waveform quantization synchronization method of a multi-FPGA multi-channel acquisition system, which comprises the steps of firstly generating a reset signal of a first ADC by a DSP, resetting hardware of the first ADC, then sequentially generating an asynchronous reset signal of a next ADC by the DSP, synchronizing the asynchronous reset signal of each ADC to a data synchronous clock domain of a previous ADC by a D trigger to generate a synchronous reset signal under the clock domain, then adjusting an input/output delay unit in the FPGA to enable the asynchronous reset signal not to be positioned in a metastable state interval under the data synchronous clock domain of the previous ADC, resetting the ADC by the synchronous reset signal, finally correcting a fixed phase difference between the ADCs, and completing waveform quantization synchronization.
Meanwhile, the waveform quantization synchronization method of the multi-FPGA multi-channel acquisition system also has the following beneficial effects:
(1) when the first ADC is reset, whether the asynchronous reset signal is in the metastable state interval of the ADC1 or not does not need to be considered, and only the reset results of other ADCs and the first ADC need to be ensured to have the same phase.
(2) According to the invention, the quantization synchronization process of the ADC can be realized only by a DSP + FPGA structure without adding extra hardware, so that the research and development complexity is reduced, and the research and development cost is saved.
Drawings
FIG. 1 is an ADC reset timing diagram;
FIG. 2 is a simplified model diagram of an ADC synchronous reset;
FIG. 3 is a timing diagram of asynchronous reset of two ADC slices;
FIG. 4 is a schematic diagram of waveform quantization synchronization for a multi-FPGA multi-channel acquisition system;
FIG. 5 is a diagram of a metastable time window of a register;
FIG. 6 is a schematic diagram of a meta-stable affecting D flip-flop output signal;
fig. 7 is a three-chip ADC reset synchronization timing diagram.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
ADC quantization synchronization is a very important task in the design of acquisition systems, and it is a prerequisite for synchronization of the whole acquisition system, especially for time-parallel interleaved sampling (TIADC) systems. The TIADC technology is that the same signal is respectively sent into a plurality of ADCs for sampling, and sampling points are spliced at the digital rear end to restore the waveform, so as to improve the sampling rate of an acquisition system. Wherein, the sampling clocks of the multiple ADC have fixed phase difference. Therefore, for the TIADC system, the quantized output between the ADCs must have a fixed phase difference, otherwise the splicing of the backend data will be affected, and finally the original waveform cannot be restored.
The relationship between the quantized output of the ADC and the analog signal is shown in fig. 1, XIN is the analog input of the ADC, SCLK is the sampling clock of the ADC, SYNC is the reset signal of the ADC, and DATA and DCLK are the quantized DATA output and the DATA synchronization clock of the ADC, respectively. After the reset signal SYNC arrives, the DATA synchronization clock DCLK is forced to be pulled down, at this time, the output DATA does not change any more, the N point of the analog signal is synchronized to the DATA synchronization clock DCLK after the DATA preparation delay (TRDR), and finally, the synchronized DCLK and DATA are output after the DATA output delay (TDR) + the pipeline delay (pipeline delay). Wherein, TDR, pipeline delay and TRDR are all fixed delays and are determined by ADC device.
According to the above timing analysis of ADC reset, it can be seen that the timing of ADC reset directly affects the timing of ADC quantized output, and there is a fixed delay between the ADC reset signal and the collected and output data, so the phase relationship of the reset signal between different ADCs directly affects the quantized output phase relationship between ADCs, and because the sampled data and the DCLK clock are strictly synchronous, the analysis of the DCLK timing characteristics can analyze the synchronization problem of the ADC sampled data, thereby converting the ADC quantized synchronization problem into the ADC reset synchronization problem, and obtaining the simplified model shown in fig. 2.
Therefore, when multiple ADCs cannot respond to the same reset signal at the same time, the sampling output between the ADCs is asynchronous, and the timing diagram of the asynchronous ADC is shown in fig. 3.
As shown in fig. 3, taking the two-chip ADC reset as an example, the reset signals SYNC1 and SYNC2 of the two-chip ADC are different by one SCLK clock, which results in the data synchronization clocks DCLK1 and DCLK2 outputted by the two-chip ADC being different by one SCLK clock period, and the data outputs of the two-chip ADC are different by one sampling point, which introduces a deviation.
The key of the ADC reset synchronization is to ensure that multiple ADCs respond to a reset signal at the same time, so it is necessary to ensure the homology of the multiple ADC signals and avoid the metastable state of the ADC reset signal response.
A waveform quantization synchronization schematic diagram of a multi-FPGA multi-channel acquisition system is shown in fig. 4. Wherein, the DSP is a back-end digital processing chip, which undertakes the calculation and control tasks of the whole system, and the PLL provides sampling clocks SCLK and DCLK for the ADCnIs an ADCnGenerated quantized data synchronization clock, SYNCnDSP is ADC reset signal, SYNC sent by DSPnIs the hardware reset signal that is ultimately sent to the ADC.
Referring to fig. 4, the waveform quantization synchronization method of the multi-channel acquisition system with multiple FPGAs according to the present invention is described in detail, and specifically includes the following steps:
s1, DSP generates first ADC1Reset signal SYNC of1DSP and will SYNC1The DSP is used as a hardware reset signal and sent to the first ADC1Resetting it to make the first ADC chip1Generating data synchronous clock signal DCLK1Connected to the FPGA through interconnection lines at the same time2An IO port of;
s2, wait for first piece ADC1After reset is completed, DSP generates 2 nd ADC2Asynchronous reset signal SYNC2DSP sends to FPGA2And reuse of FPGA2The middle D trigger sends an asynchronous reset signal SYNC sent by the DSP2DSP synchronization to DCLK1Under the clock domain, DCLK is generated1Clock domain down ADC2Synchronous reset signal SYNC2；
S3, judging asynchronous reset signal SYNC2Whether DSP is in DCLK1A metastable state interval in the clock domain, if so, the step S4 is carried out, otherwise, the step S5 is carried out;
metastability is a very common phenomenon in digital circuits and is also one of the important factors affecting the reset synchronization of ADCs. All digital devices have certain timing requirements for signal transmission, so that each D trigger is ensuredThe captured input signal can be accurately and correctly output. Usually some time before the clock edge of the D flip-flop clock signal arrives (setup time T of the D flip-flop)setup) Remains stable for a period of time after the clock edge arrives (hold time T of D flip-flop)hold) Again, a change occurs that would otherwise fail to correctly output the captured input signal, i.e., create a meta-stable state.
Twindows＝Tsetup+Thold
As shown in FIG. 5, taking the rising edge of the clock as an example, a time span T is formed near the rising edgewindowsThe time window, in which the input signal cannot change, will generate metastable state once it changes.
Once the meta-stable state occurs, the output of the D flip-flop will be in an unknown state between the high level 1 and the low level 0, and after a period of time, the output will be at the low level 0 or at the high level 1, and the stable time after the device meta-stable state occurs will depend on the device process. As shown IN FIG. 6, CLK is the D-flip-flop clock, SIG _ IN is the D-flip-flop input signal, and SIG _ IN transitions within the meta-stable time window, creating a meta-stable condition. SIG _ OUT1 and SIG _ OUT2 are outputs that a D flip-flop may produce when meta-stability occurs, respectively. It can be seen that in fig. 6, due to the meta-stability, the D flip-flop randomly generates two outputs, and the two outputs differ by one CLK clock cycle. The generation of metastability introduces random errors into the signal reception.
In a synchronous system, the input signal strictly meets the requirement of a time window, and the metastable state phenomenon cannot occur, and usually occurs on the asynchronous signal transmission crossing clock domains. Reset signal SYNC from DSP to which the present invention relatesnDSP, which is an asynchronous signal for the sampling clock SCLK of the ADC, and the data synchronous clock DCLKnIs divided by SCLK, and therefore DCLKnThe sampling clock SCLK of the ADC is a signal in the same clock domain.
Therefore, the asynchronous reset signal can be sent by the DSP for multiple times, the phase relation of the acquired waveforms of the front and rear groups of ADCs after reset is observed, if the phase relation of the acquired waveforms of the front and rear groups of ADCs changes in the multiple reset process, the asynchronous reset signal is indicated to be located in a metastable state interval under a clock domain of the front ADC, otherwise, the asynchronous signal avoids the metastable state interval under the clock domain, and can be stably synchronized under the clock domain.
Based on the above analysis, the time window T can be reduced to avoid the metastable state caused by the reset of ADCwindowsReducing the interval of occurrence of the metastable state, reducing the probability of the occurrence of the metastable state, or preventing the signal from falling into the time window by delaying the asynchronous reset signal. However, the setup time T of the registersetupAnd a holding time TholdUsually determined by the device process and cannot be changed once the device type is selected. Although higher process devices may be selected, this approach will certainly increase the cost of the system. Therefore, the ADC reset can be prevented from generating a metastable state by a delay method.
S4, adjusting delay value of input/output delay unit
The input/output delay unit IODELAY is a programmable delay unit built in the FPGA, has 32 delay beats (tap), and can be used for a combined input path, a register input path, a combined output path or a register output path. Different delays can be achieved by configuring the tap number. tap resolution depends on the reference clock frequency input to the IODELAY module, with higher frequency, higher resolution of delayed beats.
Augmenting an FPGA2The delay value of the input/output delay unit is changed, thereby changing the FPGA2The delay of the input port enables the asynchronous reset signal SYNC sent by the DSP2DSP does not fall into ADC1Data synchronization clock DCLK1Within the metastable state interval, returning to the step S3;
s5, resetting ADC
Will FPGA2Synchronous reset signal SYNC generated by middle D flip-flop2As ADCs2By means of the FPGA2Is sent to the ADC2Resetting the reset port, and generating the ADC after the resetting is finished2Data synchronous clock ofDCLK2And is connected to the FPGA3The IO port of (3), and then returns to step S2;
then analogize in turn, for ADC3Reset operation is carried out until all ADCsiResetting is completed, i is 1,2, …, and M is the number of ADCs;
s6, correcting and fixing phase difference through software
The signal source signal is passed through a power divider, two coaxial lines with identical length are connected into two ADCs of an acquisition system, the number of lost points of a data receiving buffer area in software is regulated by using a first ADC as a reference, so that the output waveforms of the two ADCs are completely overlapped, namely, the fixed phase difference between the two ADCs is corrected, each ADC is sequentially calibrated, the fixed phase difference between the ADCs is eliminated one by one, and the waveform quantization synchronization of the whole system is completed.
Taking the reset of three ADC chips as an example, the timing of the reset signal synchronization is shown in fig. 7. In fig. 7, SCLK is the sampling clock of the multiple ADCs, SYNCn _ DSP is the ADC reset clock transmitted by the DSP, DCLKn is the data synchronization clock of ADCn, SYNCn _ DSP _ AFT _ IODELAY is the ADC reset signal after passing through the IODELAY module, (n is 1,2,3), and the block represents the metastable time window of the clock.
According to the above analysis, in fig. 7, after the DSP sends SYNC1_ DSP, the ADC1 is reset, the data synchronization clock DCLK1 is generated after the reset, and the SYNC2_ DSP is synchronized by using DCLK1, while the SYNC2_ DSP signal falls within the metastable time window of DCLK1, so that the delay is adjusted by the IODELAY module, so that the reset signal avoids the metastable time window of DCLK1, so as to eliminate the problem of random reset caused by metastable, and the adjusted signal SYNC2_ DSP _ AFT _ IODELAY obviously avoids the metastable interval of the clock, so that the ADC2 is reset by using the signal and the data synchronization clock DCLK2 is generated. The SYNC3_ DSP signal does not fall within the metastable time window of DCLK2, and therefore the delay value of IODELAY is set to 0, and the output of IODELAY, SYNC3_ DSP _ AFT _ IODELAY, is used as the hardware reset signal of ADC 3. Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.

Claims (2)

1. A waveform quantization synchronization method of a multi-FPGA multi-channel acquisition system is characterized by comprising the following steps:
(1) DSP generates a first ADC1Reset signal SYNC of1DSP and will SYNC1The DSP is used as a hardware reset signal and sent to the first ADC1Resetting it to make the first ADC chip1Generating data synchronous clock signal DCLK1Connected to the FPGA through interconnection lines at the same time2An IO port of;
(2) ADC to be first chip1After reset is completed, DSP generates 2 nd ADC2Asynchronous reset signal SYNC2DSP sends to FPGA2And reuse of FPGA2The middle D trigger sends an asynchronous reset signal SYNC sent by the DSP2DSP synchronization to DCLK1Under the clock domain, DCLK is generated1Clock domain down ADC2Synchronous reset signal SYNC2；
(3) And judging the asynchronous reset signal SYNC2Whether DSP is in DCLK1If the metastable state interval of the clock domain is in, entering the step (4), otherwise, entering the step (5);
(4) adjusting the delay value of the delay module
Augmenting an FPGA2The delay value of the input/output delay unit is changed, thereby changing the FPGA2The delay of the input port enables the asynchronous reset signal SYNC sent by the DSP2DSP does not fall into ADC1Data synchronization clock DCLK1In the metastable state interval, returning to the step (3);
(5) ADC reset
Will FPGA2Synchronous reset signal SYNC generated by middle D flip-flop2As ADCs2By means of the FPGA2Is sent to the ADC2Resetting the reset port, and generating the ADC after the resetting is finished2Data synchronization clock DCLK2And is connected to the FPGA3An IO port of;
then repeating the steps (2) - (5) by analogy in sequence, and carrying out ADC3Reset operation is carried out until all ADCsiResetting is completed, i is 1,2, …, and M is the number of ADCs;
(6) correcting fixed phase difference by software
The signal source signal is passed through a power divider, two coaxial lines with identical length are connected into two ADCs of an acquisition system, the number of lost points of a data receiving buffer area in software is regulated by using a first ADC as a reference, so that the output waveforms of the two ADCs are completely overlapped, namely, the fixed phase difference between the two ADCs is corrected, each ADC is sequentially calibrated, the fixed phase difference between the ADCs is eliminated one by one, and the waveform quantization synchronization of the whole system is completed.
2. The waveform quantization synchronization method for multi-channel acquisition system with multiple FPGAs (field programmable gate arrays) according to claim 1, wherein in the step (3), the asynchronous reset signal SYNC is judged2Whether DSP is in DCLK1The method of the metastable state interval under the clock domain comprises the following steps:
DSP repeatedly sends asynchronous reset signal SYNC2DSP, ADC after observation reset2And ADC1Collecting phase relationship of waveforms, ADC in the event of multiple resets1And ADC2The phase relation of the acquired waveform is changed, which indicates that the asynchronous reset signal SYNC is changed2DSP is located in DCLK1Otherwise, the asynchronous signal avoids DCLK1Can be stably synchronized to DCLK1Clock domain down.
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