CN109155798B

CN109155798B - Asynchronous FIFO circuit and time delay determination method

Info

Publication number: CN109155798B
Application number: CN201680086087.6A
Authority: CN
Inventors: 夏山春; 张志伟; 陈默
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-05-27
Filing date: 2016-05-27
Publication date: 2020-08-25
Anticipated expiration: 2036-05-27
Also published as: CN109155798A; WO2017201727A1

Abstract

The embodiment of the invention provides an asynchronous FIFO circuit and a time delay determination method, and relates to the field of wireless communication. The asynchronous FIFO circuit includes: the circuit comprises a write clock generating circuit, a read clock generating circuit, a write address generating circuit, a read address generating circuit, a random access memory, a delay line circuit, a synchronous logic circuit, an address comparison logic circuit and a processor; the second output end of the write address generating circuit is connected with the first input end of the delay line circuit, the second input end of the delay line circuit is connected with the first output end of the processor, the output end of the delay line circuit is connected with the first input end of the synchronous logic circuit, the output end of the synchronous logic circuit is connected with the first input end of the address comparison logic circuit, the output end of the read address generating circuit is connected with the third input end of the address comparison logic circuit, and the first output end of the address comparison logic circuit is connected with the input end of the processor. The invention can realize the accurate determination of the time delay of the asynchronous FIFO circuit.

Description

Asynchronous FIFO circuit and time delay determination method

Technical Field

The embodiment of the invention relates to the field of wireless communication, in particular to an asynchronous FIFO (First Input First output) circuit and a time delay determining method.

Background

In a wireless communication system, a plurality of communication devices are often included, the clock domains of the plurality of communication devices are all substantially independent, and the clock domains of a plurality of modules included in the same communication device are also substantially independent, so that data transmission between any two communication devices in the plurality of communication devices or data transmission between any two modules in the plurality of modules is substantially data transmission between different clock domains. For example, data transmission between Common Public Radio Interfaces (CPRI) of any two communication devices is data transmission in different clock domains, and data transmission between modules in a Digital Radio front end (DFE) in a Remote Radio Unit (RRU) in the same communication device is also data transmission in different clock domains. In order to ensure the integrity of data transmission between different clock domains, asynchronous FIFO circuits of communication devices are often used for data transmission. In addition, the normal operation of many services in a wireless communication system requires precise timing synchronization, while an asynchronous FIFO circuit often has a certain time delay, and the introduction of the time delay of the asynchronous FIFO circuit makes communication equipment unable to accurately determine the time for receiving and transmitting data, which affects the timing synchronization precision of the communication equipment.

Currently, an asynchronous FIFO circuit is provided, as shown in fig. 1, the asynchronous FIFO circuit comprising: a write clock generation circuit 1, a read clock generation circuit 2, a write address generation circuit 3, a read address generation circuit 4, a random access memory 5, a synchronization logic circuit 6, and an address comparison logic circuit 7. Referring to fig. 1, an output terminal 1a of the write clock generation circuit 1 is connected to an input terminal 3a of the write address generation circuit 3, a first output terminal 3b of the write address generation circuit 3 is connected to a first input terminal 5a of the random access memory 5, a second output terminal 3c of the write address generation circuit 3 is connected to a first input terminal 6a of the synchronization logic circuit 6, an output terminal 6b of the synchronization logic circuit 6 is connected to a first input terminal 7a of the address comparison logic circuit 7, and a second input terminal 6c of the synchronization logic circuit 6 and a second input terminal 7b of the address comparison logic circuit 7 are respectively connected to an output terminal 2a of the read clock generation circuit 2; the output terminal 2a of the read clock generating circuit 2 is further connected to the input terminal 4a of the read address generating circuit 4, the output terminal 4b of the read address generating circuit 4 is respectively connected to the second input terminal 5b of the random access memory 5 and the third input terminal 7c of the address comparison logic circuit 7, and the output terminal 7d of the address comparison logic circuit 7 is connected to the set terminal 4c of the read address generating circuit 4.

Taking data transmission between any two communication devices in different clock domains in the wireless communication processing system as an example, if a first communication device needs to transmit target data to be transmitted to a second communication device, at this time, the first communication device may perform write operation and read operation on a random access memory in an FIFO circuit included in the first communication device. When the first communication device performs a write operation on the random access memory, the write address generation circuit may generate a write address signal at a rising edge of a write clock signal generated by the write clock generation circuit, where the write address signal carries a write address, and the first communication device may write target data into a location in the random access memory corresponding to the write address. Meanwhile, when the first communication device performs a read operation on the random access memory, the read address generating circuit may generate a read address signal at a rising edge of the read clock signal generated by the read clock generating circuit, where the read address signal carries a read address, and the first communication device may read data stored at a position corresponding to the read address from the random access memory and transmit the read data to the second communication device. In the process of transmitting data by the first communication device and the second communication device, the first communication device may further determine a product of a specified read-write address difference and a clock cycle as a time delay of the asynchronous FIFO circuit, the specified read-write address difference is an address difference between a preset write address and a preset read address, the clock cycle is a read clock signal or a write clock signal, and the read clock signal and the write clock signal have the same cycle.

In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:

the real time delay of the asynchronous FIFO circuit comprises a decimal time delay and an integer time delay, wherein the decimal time delay is introduced by a phase difference between a read clock signal and a write clock signal, and the integer time delay is introduced by an address difference between a write address for performing write operation and a read address for performing read operation on the random access memory at the same moment. In the prior art, decimal time delay is not determined, only integer time delay is determined, and the integer time delay is directly determined as the time delay of an asynchronous FIFO circuit, so that the time delay determination result of the asynchronous FIFO circuit is inaccurate.

Disclosure of Invention

In order to solve the problems of the related art, the invention provides an asynchronous FIFO circuit and a time delay determination method. The technical scheme is as follows:

in a first aspect, a FIFO circuit is provided, the asynchronous FIFO circuit comprising: the circuit comprises a write clock generating circuit, a read clock generating circuit, a write address generating circuit, a read address generating circuit, a random access memory, a delay line circuit, a synchronous logic circuit, an address comparison logic circuit and a processor;

the output end of the write clock generating circuit is connected with the input end of the write address generating circuit, the first output end of the write address generating circuit is connected with the first input end of the random access memory, the second output end of the write address generating circuit is connected with the first input end of the delay line circuit, the second input end of the delay line circuit is connected with the first output end of the processor, the output end of the delay line circuit is connected with the first input end of the synchronous logic circuit, the output end of the synchronous logic circuit is connected with the first input end of the address comparison logic circuit, and the second input end of the synchronous logic circuit and the second input end of the address comparison logic circuit are respectively connected with the output end of the read clock generating circuit;

the output end of the read clock generating circuit is further connected with the input end of the read address generating circuit, the output end of the read address generating circuit is connected with the second input end of the random access memory, the output end of the read address generating circuit is further connected with the third input end of the address comparison logic circuit, and the first output end of the address comparison logic circuit is connected with the input end of the processor.

The write clock generating circuit is used for generating a write clock signal; the read clock generating circuit is used for generating a read clock signal; the write address generating circuit is used for generating a plurality of write address signals and write indicating signals, each write address signal carries a write address, the write indicating signals are generated based on at least two write addresses generated by the write address generating circuit, and the write indicating signals jump from a first logic level to a second logic level when the write address generating circuit generates a specified write address, wherein the write address generating circuit can send the generated write address signals to the random access memory through a first output end of the write address generating circuit and can send the generated write indicating signals to the delay line circuit through a second output end of the write address generating circuit; the read address generating circuit is used for generating a plurality of read address signals, each read address signal carries a read address, and the read address generating circuit can send the generated read address signals to the random access memory and the address comparison logic circuit through the output end of the read address generating circuit; the random access memory is used for storing data; the delay line circuit is used for delaying the write indication signal input into the delay line circuit and sending the delayed write indication signal to the synchronous logic circuit; the synchronous logic circuit is used for receiving the writing indication signal at the rising edge of the reading clock signal generated by the reading clock generation circuit and sending the received writing indication signal to the address comparison logic circuit; the address comparison logic circuit is used for determining a read-write address difference based on the write indication signal and the read address signal, wherein the read-write address difference is an address difference between a write address for performing write operation on the random access memory and a read address for performing read operation; the processor is used for determining decimal time delay based on the read-write address difference determined by the address comparison logic circuit, and determining the time delay of the asynchronous FIFO circuit based on the decimal time delay, wherein the decimal time delay is the time delay introduced by the phase difference between the read clock signal and the write clock signal.

It should be noted that the write clock generating circuit, the read clock generating circuit, the write address generating circuit, the read address generating circuit, the random access memory, the delay line circuit, and the synchronous logic circuit may be implemented in a hardware form in practical application, and the address comparison logic circuit and the processor may be implemented in a software form in practical application, which is not specifically limited in this embodiment of the present invention.

In an embodiment of the present invention, an asynchronous FIFO circuit includes a write clock generation circuit, a read clock generation circuit, a write address generation circuit, a read address generation circuit, a random access memory, a delay line circuit, a synchronous logic circuit, an address comparison logic circuit, and a processor. The processor can determine the decimal time delay based on the read-write address difference determined by the address comparison logic circuit and determine the time delay of the asynchronous FIFO circuit based on the decimal time delay, so that the time delay of the asynchronous FIFO circuit can be accurately determined.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the second output terminal of the address comparison logic circuit is connected to the set terminal of the read address generating circuit.

The address comparison logic circuit is used for resetting the read address currently generated by the read address generation circuit when the write indication signal is detected to jump from the first logic level to the second logic level.

In the embodiment of the invention, the address comparison logic circuit can reset the read address currently generated by the read address, so that the address difference between the write address for performing write operation on the random access memory and the read address for performing read operation at the same time is ensured to be a fixed read-write address difference, and the integer time delay of the asynchronous FIFO circuit is ensured to be fixed.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the second output terminal of the processor is connected to the reset terminal of the write address generating circuit, and the third output terminal of the processor is connected to the reset terminal of the read address generating circuit.

The processor is used for setting a power-on reset value of the write address to be a third address and setting a power-on reset value of the read address to be a fourth address when receiving a reset setting instruction, wherein the address difference between the third address and the fourth address is a specified read-write address difference, the power-on reset value of the write address is an initial write address generated by the write address generation circuit when the write address is powered on, and the power-on reset value of the read address is an initial read address generated by the read address generation circuit when the read address is powered on.

It should be noted that the reset setting instruction is used to set the write address power-on reset value and the read address power-on reset value.

In the embodiment of the present invention, the power-on reset value of the write address may be set as a third address, the power-on reset value of the read address may be set as a fourth address, and an address difference between the third address and the fourth address is a specified read-write address difference, so as to ensure that an address difference between a write address for performing a write operation on the random access memory and a read address for performing a read operation is a specified read-write address difference when the asynchronous FIFO circuit is powered on and starts to operate, thereby ensuring that time delays of the asynchronous FIFO circuit in the whole operation process are the same.

With reference to any one of the first aspect to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the delay line circuit includes: n-1 delay sections and N taps, wherein N is a natural number greater than 1;

the N-1 delay sections are connected in series, one end of the ith delay section in the N-1 delay sections is connected with the ith tap in the N taps, the other end of the ith delay section in the N-1 delay sections is connected with the (i + 1) th tap in the N taps, and i is greater than or equal to 1 and less than or equal to N-1.

It should be noted that each of the N-1 delay sections is used to delay the write indication signal input to the delay section.

In addition, since the number of delay sections between each of the N taps and the write address generation circuit is fixed, and each delay section can delay the write indication signal input to the delay section for a fixed time, the N taps correspond to N preset time delays one to one. Therefore, for each of the N taps, when the delay line circuit detects the write indication signal, the write indication signal may be delayed by a preset time delay corresponding to the tap and then sent to the synchronization logic circuit through the tap.

And the delay line circuit is also used for delaying the write indication signal by a second time delay and then sending the write indication signal to the synchronous logic circuit. Wherein the second time delay is a time delay capable of eliminating a metastable state of the synchronous logic circuit. The delay line circuit delays the write indication signal by a second time delay and then sends the write indication signal to the synchronous logic circuit, so that the synchronous logic circuit can be prevented from generating a metastable state, and the synchronous logic circuit can be ensured to receive the stable write indication signal.

In the embodiment of the invention, N taps in the delay line circuit correspond to N preset time delays one by one, the delay line circuit can sequentially pass through the N taps, and the writing indication signal is sequentially delayed by N preset time delays and then sent to the address comparison logic circuit through the synchronous logic circuit, so that the address comparison logic circuit can sequentially determine N reading and writing address differences corresponding to the N preset delays one by one, and further a subsequent processor can be ensured to accurately determine the decimal time delay based on the N reading and writing address differences.

With reference to any one of the first to the third possible implementation manners of the first aspect, in a fourth possible implementation manner of the first aspect, the synchronous logic circuit includes a plurality of serially connected flip-flops, and each flip-flop in the plurality of serially connected flip-flops is configured to receive the write indication signal at a rising edge of the read clock signal generated by the read clock generation circuit.

The synchronous logic circuit comprises a plurality of flip-flops, wherein a first stage flip-flop in the plurality of flip-flops receives a write indication signal at a rising edge of a read clock signal and sends the write indication signal to a second stage flip-flop, the second stage flip-flop receives the write indication signal at the rising edge of the read clock signal and sends the write indication signal to a third stage flip-flop, and therefore, the write indication signal is sent to an m-th stage flip-flop in the synchronous logic circuit, the m-th stage flip-flop receives the write indication signal at the rising edge of the read clock signal and sends the write indication signal to an address comparison logic circuit, m is a natural number, and m is larger than or equal to 2.

It should be noted that the first-stage flip-flop to the mth-stage flip-flop in the plurality of flip-flops are determined according to a serial sequence of the plurality of flip-flops, that is, the flip-flop connected to the delay line circuit may be determined as a first-stage flip-flop, and the flip-flops subsequent to the first-stage flip-flop are sequentially determined as a second-stage flip-flop and a third-stage flip-flop.

In the embodiment of the present invention, the synchronous logic circuit may send the write indication signal to the synchronous logic circuit through the plurality of flip-flops, and each flip-flop in the plurality of serially connected flip-flops receives and sends the write indication signal at a rising edge of the read clock signal generated by the read clock generation circuit, so that signal synchronization between the write indication signal and the read address signal may be achieved, and further, it is convenient for the subsequent address comparison logic circuit to determine the read-write address difference based on the write indication signal and the read address signal.

With reference to the third possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the read address generating circuit is configured to send the generated multiple read address signals to the address comparison logic circuit;

the write address generating circuit is used for sending a generated write indicating signal to the delay line circuit, the write indicating signal is generated based on at least two write addresses generated by the write address generating circuit, and the write indicating signal jumps from a first logic level to a second logic level when the write address generating circuit generates a specified write address;

the processor is configured to obtain, through the read address generating circuit, the delay line circuit, the synchronous logic circuit, and the address comparison logic circuit, N read-write address differences based on the write indication signal, the plurality of read address signals, and the read clock signal generated by the read clock generating circuit, where the N read-write address differences correspond to N preset time delays in the delay line circuit one to one;

the processor is further configured to determine a fractional time delay based on the N read-write address differences and a wiring time delay, and determine a time delay of the asynchronous FIFO circuit based on the fractional time delay, where the wiring time delay is a time delay introduced by wiring between the write address generation circuit and the synchronous logic circuit, and the fractional time delay is a time delay introduced by a phase difference between the read clock signal and the write clock signal generated by the write clock generation circuit.

In the embodiment of the invention, the processor can obtain N read-write address differences based on the write indication signal, the plurality of read address signals and the read clock signal generated by the read clock generation circuit through the read address generation circuit, the delay line circuit, the synchronous logic circuit and the address comparison logic circuit, determine the decimal time delay based on the N read-write address differences and the wiring time delay, further determine the time delay of the asynchronous FIFO circuit based on the decimal time delay, and realize the accurate determination of the asynchronous FIFO circuit.

With reference to the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the delay line circuit is configured to, when the write indication signal is detected, delay the write indication signal by a preset delay corresponding to an ith tap of the N taps and send the delay to the address comparison logic circuit through the synchronization logic circuit, where the N taps correspond to the N preset delays one to one;

the address comparison logic circuit is configured to, when it is detected that the write indication signal jumps from the first logic level to the second logic level at a rising edge of the read clock signal, acquire a read address carried in a currently received read address signal, determine, based on the specified write address and the acquired read address, a read-write address difference corresponding to the i-th tap, and send the read-write address difference corresponding to the i-th tap to the processor;

and the processor is configured to, when receiving a read-write address difference corresponding to the ith tap, make i equal to i +1, delay the write indication signal by the delay line circuit again by a preset delay corresponding to the ith tap of the N taps, and then send the write indication signal to the address comparison logic circuit by the synchronization logic circuit.

It should be noted that the processor may set the currently used tap of the delay line circuit, that is, the processor may set the currently used preset delay of the delay line circuit, so as to ensure that the delay line circuit may sequentially traverse the N taps, so as to sequentially delay the write indication signal by the N preset delays.

In the embodiment of the invention, a cycle operation can be executed through the cooperation of the delay line circuit, the synchronous logic circuit, the address comparison logic circuit and the processor, so that the read-write address difference corresponding to each of the N taps can be obtained, that is, the read-write address difference corresponding to each of the N preset time delays can be obtained, and the accuracy of determining the decimal time delay based on the N read-write address differences by a subsequent processor can be further ensured.

In a second aspect, a method for determining a time delay is provided, where the method is applied to an asynchronous FIFO circuit described in any one of the foregoing first aspect to the sixth possible implementation manner of the first aspect, and the method includes:

during the read operation and the write operation of the random access memory, the read address generating circuit sends a plurality of generated read address signals to the address comparison logic circuit, the write address generating circuit sends a generated write indication signal to the delay line circuit, the write indication signal is generated based on at least two write addresses generated by the write address generating circuit, and the write indication signal jumps from a first logic level to a second logic level when the write address generating circuit generates a specified write address;

the processor obtains N read-write address differences based on the write indication signal, the plurality of read address signals and the read clock signal generated by the read clock generation circuit through the read address generation circuit, the delay line circuit, the synchronous logic circuit and the address comparison logic circuit, wherein the N read-write address differences correspond to N preset time delays in the delay line circuit in a one-to-one mode, and N is a natural number greater than 1;

the processor determines a decimal time delay based on the N read-write address differences and a wiring time delay, wherein the wiring time delay is a time delay introduced by wiring between the write address generating circuit and the synchronous logic circuit, and the decimal time delay is a time delay introduced by a phase difference between the read clock signal and the write clock signal generated by the write clock generating circuit;

the processor determines a time delay of the asynchronous FIFO circuit based on the fractional time delay.

In the process of performing a read operation on the random access memory, each time the read address generating circuit detects a rising edge of the read clock signal, a read address signal is generated, and the read address signal carries a read address, that is, the read address generating circuit can generate a read address signal in each cycle of the read clock signal. Meanwhile, in the process of writing the random access memory, the write address generating circuit may generate a write indication signal and a plurality of write address signals, each of which carries a write address, and may jump the write indication signal from the first logic level to the second logic level when the write address generating circuit detects that the generated write address is the designated write address.

In addition, the state of the first logic level is opposite to the state of the second logic level, such as when the first logic level is 0, the second logic level may be 1; when the first logic level is 1, the second logic level may be 0, which is not specifically limited in the embodiment of the present invention.

Furthermore, the write address generating circuit may further jump the write indication signal from the second logic level to the first logic level when detecting that the generated write address is any write address other than the designated write address, which is not specifically limited in the embodiment of the present invention.

With reference to the second aspect, in a first possible implementation manner of the second aspect, the delay line circuit includes N-1 delay sections and N taps, where the N taps are in one-to-one correspondence with the N preset delays;

the processor obtains N read-write address differences based on the write indication signal, the plurality of read address signals, and the read clock signal generated by the read clock generation circuit through the read address generation circuit, the delay line circuit, the synchronization logic circuit, and the address comparison logic circuit, and includes:

when the write indication signal is detected by the delay line circuit, the write indication signal is delayed by a preset delay corresponding to the ith tap in the N taps and then is sent to the address comparison logic circuit through the synchronous logic circuit, wherein i is greater than or equal to 1 and less than or equal to N-1;

when the address comparison logic circuit detects that the write indication signal jumps from the first logic level to the second logic level on the rising edge of the read clock signal, acquiring a read address carried in a currently received read address signal, determining a read-write address difference corresponding to the ith tap based on the specified write address and the acquired read address, and sending the read-write address difference corresponding to the ith tap to the processor;

and when the processor receives the read-write address difference corresponding to the ith tap, enabling i to be i +1, and returning to the step of delaying the write indication signal by a preset time delay corresponding to the ith tap in the N taps and then sending the delayed write indication signal to the address comparison logic circuit through the synchronous logic circuit.

In addition, since the number of delay sections between each of the N taps and the write address generation circuit is fixed, and each delay section can delay the write indication signal input to the delay section for a fixed time, the N taps correspond to N preset time delays one to one.

Furthermore, the processor may set a tap currently used by the delay line circuit, that is, the processor may set a preset time delay currently used by the delay line circuit, so as to ensure that the delay line circuit may sequentially traverse the N taps, so as to sequentially delay the write indication signal by the N preset time delays.

With reference to the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the determining, by the address comparison logic circuit, a read-write address difference corresponding to the i-th tap based on a specified write address and an obtained read address includes:

the address comparison logic circuit determines an address difference between the specified write address and the retrieved read address;

the address comparison logic circuit subtracts 1 from the number of the triggers included in the synchronous logic circuit to obtain a first numerical value;

and the address comparison logic circuit adds the determined address difference and the first numerical value to obtain a read-write address difference corresponding to the ith tap.

In the embodiment of the invention, because the write indication signal is jumped from the first logic level to the second logic level when the write address generation circuit generates the specified write address, and the write indication signal is sent to the address comparison logic circuit after being delayed by the synchronous logic circuit for a first number of clock cycles, when the address comparison logic circuit detects that the write indication signal is jumped from the first logic level to the second logic level, the write address generation circuit generates the first number of write addresses after generating the specified write address, and therefore, the address difference between the write address currently performing the write operation on the random access memory and the specified write address is the first number. And the address comparison logic circuit is used for determining the address difference between a write address for performing write operation on the random access memory and a read address for performing read operation at the same time, and a read address signal currently received by the address comparison logic circuit is directly sent to the address comparison logic circuit without delay, so that when the address comparison logic circuit determines the read-write address difference corresponding to the ith tap based on the specified write address and the acquired read address, the determined address difference and the first value can be added to obtain the read-write address difference corresponding to the ith tap, and the accurate determination of the read-write address difference corresponding to the ith tap is realized.

With reference to any one of the second aspect to the second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the determining, by the processor, before the decimal time delay based on the N read-write address differences and the wiring time delay, further includes:

the processor acquires the maximum time delay and the minimum time delay introduced by the wiring between the write address generating circuit and the synchronous logic circuit from a stored back-end wiring report, wherein the back-end wiring report is used for recording the time delay introduced by all the wirings included in the asynchronous FIFO circuit;

and the processor determines the average value of the maximum time delay and the minimum time delay as the wiring time delay.

In the embodiment of the present invention, since the positions of the write address generating circuit and the synchronous logic circuit may affect the routing delay, when the asynchronous FIFO circuit is routed, the positions of the write address generating circuit and the synchronous logic circuit may be constrained to be as close as possible, so that the variation of the maximum delay and the minimum delay introduced by the routing between the write address generating circuit and the synchronous logic circuit is minimized, so that the routing delay determined based on the maximum delay and the minimum delay is as small and stable as possible, thereby ensuring the accuracy of the processor in determining the fractional delay based on the routing delay.

With reference to any one of the second aspect to the third possible implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, the determining, by the processor, a decimal delay based on the N read-write address differences and the wiring delay includes:

the processor determines a first time delay from the N preset time delays based on the N read-write address differences;

and the processor determines the sum of the first time delay and the wiring time delay as the fractional time delay.

In the embodiment of the invention, the processor can determine the first time delay from the N preset time delays based on the N read-write address differences, and determine the sum of the first time delay and the wiring time delay as the decimal time delay, thereby realizing the accurate determination of the decimal time delay.

With reference to the fourth possible implementation manner of the second aspect, in a fifth possible implementation manner of the second aspect, the determining, by the processor, a first delay from the N preset delays based on the N read/write address differences includes:

the processor sequences the N read-write address differences based on the N preset time delays to obtain the sequence of the N read-write address differences;

the processor acquires a first read-write address difference from the N read-write address differences based on the sequence of the N read-write address differences, wherein the first read-write address difference is determined based on a read-write address difference jumping in the N read-write address differences, and the jumping read-write address difference is a read-write address difference different from a previous read-write address difference;

and the processor determines the preset time delay corresponding to the first read-write address difference as the first time delay.

Optionally, when the processor ranks the N read/write address differences based on the N preset time delays, the N read/write address differences may be ranked according to a sequence from small to large of the N preset time delays, and of course, the N read/write address differences may also be ranked according to a sequence from large to small of the N preset time delays.

Optionally, the processor may obtain, based on the order of the N read-write address differences, a first read-write address difference from the N read-write address differences by: when the sequence of the N read-write address differences is obtained by sequencing according to the sequence of the N preset time delays from small to large, the processor obtains a first jumping read-write address difference from the N read-write address differences, and determines the obtained read-write address difference as a first read-write address difference; and when the sequence of the N read-write address differences is obtained by sequencing according to the sequence of the N preset time delays from large to small, the processor determines the read-write address difference of the last jump from the N read-write address differences, and determines the read-write address difference of the previous bit of the read-write address difference of the last jump as the first read-write address difference.

With reference to the fourth possible implementation manner of the second aspect or the fifth possible implementation manner of the second aspect, in a sixth possible implementation manner of the second aspect, after the determining, by the processor, a decimal time delay based on the N read-write address differences and the wiring time delay, the method further includes:

the processor determines a second time delay based on the first time delay, wherein the second time delay is a time delay capable of eliminating the metastable state of the synchronous logic circuit;

the processor resets the read address generated by the read address generation circuit through the address comparison logic circuit based on the first delay and the second delay.

In the embodiment of the present invention, since the second time delay is a time delay capable of eliminating a metastable state of the synchronous logic circuit, in the process that the processor resets the read address generated by the read address generating circuit through the address comparison logic circuit based on the first time delay and the second time delay, the metastable state of the synchronous logic circuit can be avoided, so that the synchronous logic circuit can receive a stable write indication signal, the accuracy of the read-write address difference determined by the address comparison logic circuit is ensured, and the correct reset of the read address generated by the read address generating circuit by the address comparison logic circuit is ensured.

With reference to the sixth possible implementation manner of the second aspect, in a seventh possible implementation manner of the second aspect, the determining, by the processor, the second time delay based on the first time delay includes:

when the first time delay is less than or equal to a signal stabilization time, the processor determines a sum of the first time delay and a first preset time delay as the second time delay, the first preset time delay is greater than the signal stabilization time and less than a third time delay, the signal stabilization time is a sum of an establishment time and a holding time of a first stage flip-flop, the first stage flip-flop is a flip-flop connected with the delay line circuit among a plurality of flip-flops included in the synchronous logic circuit, the third time delay is a difference between a clock cycle and the signal stabilization time, the clock cycle is a cycle of the read clock signal or the write clock signal, the cycles of the read clock signal and the write clock signal are equal, and the signal stabilization time is less than the third time delay; alternatively, the first and second electrodes may be,

when the first time delay is greater than the signal stabilization time and less than the third time delay, the processor subtracts a second preset time delay from the first time delay to obtain a second time delay, wherein the second preset time delay is greater than the signal stabilization time and less than or equal to the decimal time delay; alternatively, the first and second electrodes may be,

and when the first time delay is greater than or equal to the third time delay, the processor subtracts the first preset time delay from the first time delay to obtain the second time delay.

It should be noted that, both the first preset time delay and the second preset time delay may be preset, and the first preset time delay may be any time delay within a range greater than the signal stabilization time and less than the third time delay, and the second preset time delay may be any time delay within a range greater than the signal stabilization time and less than or equal to the fractional time delay, which is not specifically limited in the embodiment of the present invention.

In addition, in the embodiment of the present invention, the setup time and the hold time of the first stage flip-flop may be obtained from the back-end wiring report, and a sum of the setup time and the hold time may be determined as the signal stabilization time.

In the embodiment of the present invention, when the delay line circuit delays the write indication signal by the first delay and then transmits the write indication signal to the synchronous logic circuit, the rising edge of the read clock signal is located right at the transition point of the write indication signal, so that, in order to eliminate the metastable state of the synchronous logic circuit and ensure that the write indication signal received by the synchronous logic circuit is relatively stable, the second delay may be determined based on the first delay, and then the delay line circuit may delay the write indication signal by the second delay and then transmit the write indication signal to the synchronous logic circuit, so as to ensure that the rising edge of the read clock signal is located at the stable point of the write indication signal, and further ensure that the synchronous logic circuit can receive the stable write indication signal at the rising edge of the read clock signal.

With reference to the sixth possible implementation manner of the second aspect or the seventh possible implementation manner of the second aspect, in an eighth possible implementation manner of the second aspect, the resetting, by the processor, the read address generated by the read address generation circuit through the address comparison logic circuit based on the first latency and the second latency includes:

the processor sends the first time delay to the address comparison logic circuit;

the processor sets the delay of the delay line circuit to the second delay;

when the write indication signal is detected by the delay line circuit, sending the write indication signal to the address comparison logic circuit through the synchronous logic circuit;

when the address comparison logic circuit detects that the write indication signal jumps from the first logic level to the second logic level on the rising edge of a read clock signal, acquiring a read address carried in a currently received read address signal, and determining a second read-write address difference based on the specified write address and the acquired read address, wherein the second read-write address difference is a read-write address difference corresponding to the second time delay;

when the address comparison logic circuit receives the first time delay, the read address currently generated by the read address generation circuit is reset based on the specified write address, the first time delay, the second read-write address difference and the specified read-write address difference.

It should be noted that, when the N preset delays do not include the second delay, the N read/write address differences do not include the read/write address difference corresponding to the second delay, and therefore, the read/write address difference corresponding to the second delay needs to be determined; and when the N preset time delays include a second time delay, in order to ensure the accuracy of the determined second read/write address difference, the read/write address difference corresponding to the second time delay may be determined again. Therefore, no matter whether the N preset time delays include the second time delay, after the processor sets the time delay of the delay line circuit to the second time delay, the address comparison logic circuit may determine the read-write address difference corresponding to the second time delay, that is, determine the second read-write address difference, through the delay line circuit, the synchronous logic circuit, and the read-address generation circuit.

In an embodiment of the invention, after the processor sets the delay line circuit to the second delay, when the delay line circuit detects the write indication signal, the write indication signal may be sent to the address comparison logic circuit with the second delay. The second time delay is time delay capable of eliminating a metastable state of the synchronous logic circuit, so that the synchronous logic circuit can receive a stable writing indication signal and send the writing indication signal to the address comparison logic circuit, accuracy of a second reading and writing address difference determined by the address comparison logic circuit based on the writing indication signal is guaranteed, and correct resetting of a reading address generated by the reading address generation circuit by the address comparison logic circuit based on the second reading and writing address difference is guaranteed.

With reference to the sixth possible implementation manner of the second aspect or the seventh possible implementation manner of the second aspect, in a ninth possible implementation manner of the second aspect, the resetting, by the processor, the read address generated by the read address generation circuit through the address comparison logic circuit based on the first latency and the second latency includes:

when the N preset time delays comprise the second time delay, the processor acquires a second read-write address difference from the N read-write address differences, wherein the second read-write address difference is a read-write address difference corresponding to the second time delay;

the processor sends the first delay and the second read-write address difference to the address comparison logic circuit;

the processor sets the delay of the delay line circuit to the second delay;

when the address comparison logic circuit detects that the writing indication signal jumps from the first logic level to the second logic level at the rising edge of the reading clock signal and receives the first time delay and the second reading and writing address difference, the address comparison logic circuit resets the reading address currently generated by the reading address generation circuit based on the specified writing address, the first time delay, the second reading and writing address difference and the specified reading and writing address difference.

In the embodiment of the present invention, when the N preset delays include a second delay, at this time, the N read/write address differences include a read/write address difference corresponding to the second delay, so that the processor can directly obtain the read/write address difference corresponding to the second delay from the N read/write address differences, and send the read/write address difference corresponding to the second delay to the address comparison logic circuit, and at this time, the address comparison logic circuit does not need to determine the read/write address difference corresponding to the second delay again through the delay line circuit, the synchronous logic circuit, and the read address generation circuit, thereby saving the processing resources in the asynchronous FIFO circuit.

With reference to the eighth possible implementation manner of the second aspect or the ninth possible implementation manner of the second aspect, in a tenth possible implementation manner of the second aspect, the resetting, by the address comparison logic circuit, the read address currently generated by the read address generation circuit based on the specified write address, the first time delay, the second read/write address difference, and the specified read/write address difference includes:

when the first time delay is less than or equal to the signal stabilization time and the address difference obtained by adding 1 to the second read-write address difference is not equal to the specified read-write address difference, the address comparison logic circuit determines a first address based on the specified write address and the number of flip-flops included in the synchronous logic circuit, and sets the read address currently generated by the read address generation circuit as the first address; alternatively, the first and second electrodes may be,

when the first time delay is longer than the signal stabilization time and the second read-write address difference is not equal to the specified read-write address difference, the address comparison logic circuit determines a second address based on the specified write address and the number of flip-flops included in the synchronous logic circuit, and sets the read address currently generated by the read address generation circuit as the second address.

In the embodiment of the present invention, the address comparison logic circuit may determine the first address or the second address based on different conditions of the first time delay and the second read/write address difference, and further reset the read address currently generated by the read address generation circuit based on the first address or the second address, thereby implementing correct reset of the read address currently generated by the read address generation circuit.

With reference to any one of the second aspect to the tenth possible implementation manner of the second aspect, in an eleventh possible implementation manner of the second aspect, the determining, by the processor, a delay of the asynchronous FIFO circuit based on the fractional delay includes:

the processor acquires an integer time delay, wherein the integer time delay is the time delay introduced by the address difference between a write address for performing write operation and a read address for performing read operation on the random access memory at the same time;

and the processor determines the sum of the decimal time delay and the integer time delay as the time delay of the asynchronous FIFO circuit.

Optionally, the processor obtains the integer time delay, and may determine the product of the specified read-write address difference and the clock cycle as the integer time delay.

In the embodiment of the invention, because the time delay of the asynchronous FIFO circuit comprises the integer time delay and the decimal time delay under the normal condition, the sum of the decimal time delay and the integer time delay can be determined as the time delay of the asynchronous FIFO circuit, thereby realizing the accurate determination of the time delay of the asynchronous FIFO circuit.

With reference to any one possible implementation manner of the second aspect to the eleventh possible implementation manner of the second aspect, in a twelfth possible implementation manner of the second aspect, the method further includes:

when the processor receives a reset setting instruction, a write address power-on reset value is set as a third address, a read address power-on reset value is set as a fourth address, the address difference between the third address and the fourth address is a specified read-write address difference, the write address power-on reset value is an initial write address generated by the write address generation circuit when the write address is powered on, and the read address power-on reset value is an initial read address generated by the read address generation circuit when the read address is powered on.

In the embodiment of the invention, the power-on reset value of the write address is set as the third address, the power-on reset value of the read address is set as the fourth address, and the address difference between the third address and the fourth address is the specified read-write address difference, so that the address difference between the write address for performing write operation on the random access memory and the read address for performing read operation on the random access memory can be ensured to be the specified read-write address difference when the asynchronous FIFO circuit starts to work after being powered on, thereby ensuring that the time delays of the asynchronous FIFO circuit in the whole working process are the same, and ensuring the accuracy of the determined time delay of the asynchronous FIFO circuit.

The technical scheme provided by the invention has the beneficial effects that: in an embodiment of the present invention, an asynchronous FIFO circuit includes a write clock generation circuit, a read clock generation circuit, a write address generation circuit, a read address generation circuit, a random access memory, a delay line circuit, a synchronous logic circuit, an address comparison logic circuit, and a processor. Wherein, the read address generating circuit can send a plurality of read address signals to the address comparison logic circuit, the write address generating circuit can send a write indication signal to the delay line circuit, because the delay line circuit comprises N preset time delays, the delay line circuit can delay the write indication signal by N preset delays in sequence and then send the delay signal to the address comparison logic circuit through the synchronous logic circuit, the address comparison logic circuit can determine N read-write address differences corresponding to the N preset delays one by one based on the write indication signal and the read address signal, and sends the N read and write address differences to the processor, which may then determine a fractional delay based on the N read and write address differences and the wiring delay, and determining the time delay of the asynchronous FIFO circuit based on the decimal time delay, thereby realizing the accurate determination of the time delay of the asynchronous FIFO circuit.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below.

Fig. 1 is a schematic structural diagram of an asynchronous FIFO circuit provided in the related art;

FIG. 2 is a schematic diagram of an asynchronous FIFO circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another asynchronous FIFO circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a structure of another asynchronous FIFO circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a delay line circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a synchronous logic circuit according to an embodiment of the present invention;

fig. 7 is a flowchart of a method for determining a delay according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a first write indication signal according to an embodiment of the present invention;

FIG. 9(a) is a diagram of a second write indication signal provided by an embodiment of the present invention;

FIG. 9(b) is a diagram of a third write indication signal provided by an embodiment of the present invention;

FIG. 10(a) is a diagram illustrating a fourth write indication signal provided by an embodiment of the present invention;

FIG. 10(b) is a diagram of a fifth write indication signal provided by an embodiment of the present invention;

fig. 10(c) is a schematic diagram of a sixth write indication signal provided by the embodiment of the present invention.

Reference numerals:

the related technology comprises the following steps:

1: a write clock generation circuit; 1 a: an output terminal of the write clock generation circuit;

2: a read clock generating circuit; 2 a: an output terminal of the read clock generating circuit;

3: a write address generating circuit; 3 a: an input terminal of a write address generating circuit; 3 b: a first output terminal of the write address generating circuit; 3 c: a second output terminal of the write address generating circuit;

4: a read address generating circuit; 4 a: an input terminal of the read address generating circuit; 4 b: an output terminal of the read address generating circuit; 4 c: reading a set end of the address generating circuit;

5: a random access memory; 5 a: a first input of a random access memory; 5 b: a second input of the random access memory;

6: a synchronous logic circuit; 6 a: a first input of the synchronization logic circuit; 6 b: an output of the synchronous logic circuit; 6 c: a second input of the synchronization logic circuit;

7: an address comparison logic circuit; 7 a: a first input of the address comparison logic circuit; 7 b: second input terminal of address comparison logic circuit, 7 c: a third input of the address comparison logic circuit; 7 d: an output of the address comparison logic circuit.

The embodiment of the invention comprises the following steps:

8: a write clock generation circuit; 8 a: an output terminal of the write clock generation circuit;

9: a read clock generating circuit; 9 a: an output terminal of the read clock generating circuit;

10: a write address generating circuit; 10 a: an input terminal of a write address generating circuit; 10 b: a first output terminal of the write address generating circuit; 10 c: a second output terminal of the write address generating circuit; 10 d: a reset terminal of the write address generating circuit;

11: a read address generating circuit; 11 a: an input terminal of the read address generating circuit; 11 b: an output terminal of the read address generating circuit; 11 c: reading a set end of the address generating circuit; 11 d: a reset terminal of the read address generating circuit;

12: a random access memory; 12 a: a first input of a random access memory; 12 b: a second input of the random access memory;

13: a delay line circuit; 13 a: a first input of a delay line circuit; 13 b: an output of the delay line circuit; 13 c: a second input of the delay line circuit;

14: a synchronous logic circuit; 14 a: a first input of the synchronization logic circuit; 14 b: an output of the synchronous logic circuit; 14 c: a second input of the synchronization logic circuit;

15: an address comparison logic circuit; 15 a: a first input of the address comparison logic circuit; 15 b: second input terminal of address comparison logic circuit, 15 c: a third input of the address comparison logic circuit; 15 d: a first output of the address compare logic circuit; 15 e: a second output of the address compare logic circuit;

16: a processor; 16 a: a first output of the processor; 16 b: an input of a processor; 16 c: a second output of the processor; 16 d: a third output of the processor 16;

d: a delay section; t: tapping; p: and a trigger.

Detailed Description

Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

Fig. 2 is a schematic structural diagram of an asynchronous FIFO circuit according to an embodiment of the present invention. Referring to fig. 2, the asynchronous FIFO circuit includes: a write clock generation circuit 8, a read clock generation circuit 9, a write address generation circuit 10, a read address generation circuit 11, a random access memory 12, a delay line circuit 13, a synchronization logic circuit 14, an address comparison logic circuit 15, and a processor 16;

an output end 8a of the write clock generation circuit 8 is connected to an input end 10a of the write address generation circuit 10, a first output end 10b of the write address generation circuit 10 is connected to a first input end 12a of the random access memory 12, a second output end 10c of the write address generation circuit 10 is connected to a first input end 13a of the delay line circuit 13, a second input end 13c of the delay line circuit 13 is connected to a first output end 16a of the processor 16, an output end 13b of the delay line circuit 13 is connected to a first input end 14a of the read logic circuit 14, an output end 14b of the read logic circuit 14 is connected to a first input end 15a of the address comparison logic circuit 15, and a second input end 14c of the read logic circuit 14 and a second input end 15b of the address comparison logic circuit 15 are respectively connected to an output end 9a of the write clock generation circuit 10; the output 9a of the read clock generating circuit 9 is further connected to an input 11a of a read address generating circuit 11, an output 11b of the read address generating circuit 11 is connected to a second input 12b of the random access memory 12, an output 11b of the read address generating circuit 11 is further connected to a third input 15c of the address comparison logic circuit 15, and a first output 15d of the address comparison logic circuit 15 is connected to an input 16b of the processor 16.

When the asynchronous FIFO circuit is used to write into the random access memory 12, the write clock generating circuit 8 may send the generated write clock signal to the write address generating circuit 10, the write address generating circuit 10 may generate a write address signal at a rising edge of the write clock signal, the write address signal carries a write address, and at this time, the communication device where the asynchronous FIFO circuit is located may write the data to be transmitted into the random access memory 12 at a position corresponding to the write address. Meanwhile, when the asynchronous FIFO circuit is used to read the random access memory 12, the read clock generating circuit 9 may send the generated read clock signal to the read address generating circuit 11, and the read address generating circuit 11 may generate a read address signal at a rising edge of the read clock signal, where the read address signal carries a read address, and at this time, the communication device where the asynchronous FIFO circuit is located may read data stored at a position corresponding to the read address from the random access memory 12.

Wherein, the write clock generating circuit 8 is used for generating a write clock signal; the read clock generating circuit 9 is used for generating a read clock signal; the write address generating circuit 10 is configured to generate a plurality of write address signals and a write indication signal, each write address signal carries a write address, the write indication signal is generated based on at least two write addresses generated by the write address generating circuit 10, and the write indication signal jumps from a first logic level to a second logic level when the write address generating circuit 10 generates a specified write address, wherein the write address generating circuit 10 may transmit the generated plurality of write address signals to the random access memory 12 through the first output terminal 10b and may transmit the generated write indication signal to the delay line circuit 13 through the second output terminal 10 c; the read address generating circuit 11 is configured to generate a plurality of read address signals, each of which carries a read address, wherein the read address generating circuit 11 may send the generated plurality of read address signals to the random access memory 12 and the address comparison logic circuit 15 through the output terminal 11 b; the random access memory 12 is used for storing data; the delay line circuit 13 is used for delaying the write indication signal input into the delay line circuit 13 and sending the delayed write indication signal to the synchronous logic circuit 14; the synchronization logic circuit 14 is configured to receive a write indication signal at a rising edge of the read clock signal generated by the read clock generation circuit 9, and send the received write indication signal to the address comparison logic circuit 15; the address comparison logic circuit 15 is configured to determine a read-write address difference based on the write indication signal and the read address signal, where the read-write address difference is an address difference between a write address currently performing a write operation on the random access memory 12 and a read address performing a read operation; the processor 16 is configured to obtain, through the read address generating circuit 11, the delay line circuit 13, the synchronous logic circuit 14, and the address comparison logic circuit 15, N read-write address differences based on the write indication signal, the multiple read address signals, and the read clock signal, where the N read-write address differences correspond to N preset time delays in the delay line circuit 13 one to one, and N is a natural number greater than 1; and the processor 16 is further configured to determine a fractional time delay based on the N read-write address differences and the wiring time delay, and determine a time delay of the asynchronous FIFO circuit based on the fractional time delay, where the wiring time delay is a time delay introduced by wiring between the write address generating circuit and the synchronous logic circuit, and the fractional time delay is a time delay introduced by a phase difference between the read clock signal and the write clock signal.

It should be noted that, both the specified write address and the N preset time delays may be preset, and this is not specifically limited in the embodiment of the present invention.

In addition, the state of the first logic level is opposite to the state of the second logic level, such as when the first logic level is 0, the second logic level is 1; when the first logic level is 1, the second logic level is 0, which is not specifically limited in this embodiment of the present invention.

Furthermore, the write address generating circuit 10 may further jump the write indication signal from the second logic level to the first logic level when detecting that the generated write address is any write address other than the designated write address, which is not specifically limited in the embodiment of the present invention.

It should be further noted that the write clock generation circuit 8, the read clock generation circuit 9, the write address generation circuit 10, the read address generation circuit 11, the random access memory 12, the delay line circuit 13, and the synchronization logic circuit 14 may be implemented in a hardware form or a software form in practical applications, for example, the write clock generation circuit 8 and the read clock generation circuit 9 are implemented by an oscillator, further, the oscillator may be implemented by combining a phase-locked loop, the write address generation circuit 10 and the read address generation circuit 11 may be implemented by hardware programming devices, for example, the synchronous logic circuit 14 may be implemented by a flip-flop, and the functions of the address comparison logic circuit 15 and the processor 16 may be implemented in a form of software or hardware in practical application, for example, by a hardware coding device, which is not specifically limited in this embodiment of the present invention. Alternatively, when the above circuits and processors are implemented by software, they may be integrated on one hardware entity, or may be distributed on multiple hardware entities separately or in a partial combination, which is not limited herein. For example, the function of the address comparison logic circuit 15 may be implemented by the processor 16, or the function of the processor 16 may be implemented by being embedded in the address comparison logic circuit 15, or the address comparison logic circuit 15 and the processor 16 may not be integrated, which is not limited herein.

Referring to fig. 3, in the asynchronous FIFO circuit, the second output terminal 15e of the address comparison logic circuit 15 is connected to the set terminal 11c of the read address generation circuit 11.

The address comparison logic circuit 15 is configured to reset the read address currently generated by the read address generation circuit 11 when detecting that the write indication signal transits from the first logic level to the second logic level.

Referring to fig. 4, in the asynchronous FIFO circuit, the second output terminal 16c of the processor 16 is connected to the reset terminal 10d of the write address generation circuit 10, and the third output terminal 16d of the processor 16 is connected to the reset terminal 11d of the read address generation circuit 11.

The processor 16 is configured to set a power-on reset value of the write address to a third address and a power-on reset value of the read address to a fourth address when receiving a reset setting instruction, where an address difference between the third address and the fourth address is a specified read-write address difference, the power-on reset value of the write address is an initial write address generated by the write address generation circuit 10 when the write address is powered on, and the power-on reset value of the read address is an initial read address generated by the read address generation circuit 11 when the read address is powered on.

In addition, the specified read/write address difference may be preset, and for example, the specified read/write address difference may be 7 or 8, and this is not specifically limited in this embodiment of the present invention.

Furthermore, in the embodiment of the present invention, the power-on reset value of the write address is set as the third address, the power-on reset value of the read address is set as the fourth address, and the address difference between the third address and the fourth address is the specified read-write address difference, so that it can be ensured that the address difference between the write address for performing the write operation and the read address for performing the read operation on the random access memory 12 is the specified read-write address difference when the asynchronous FIFO circuit starts to operate after being powered on, thereby ensuring that the time delays of the asynchronous FIFO circuit are the same in the whole operation process.

Referring to fig. 5, the delay line circuit 13 includes: n-1 delay sections D and N taps T, wherein N is a natural number greater than 1;

n-1 delay sections are connected in series, one end of the ith delay section in the N-1 delay sections is connected with the ith tap in the N taps, the other end of the ith delay section in the N-1 delay sections is connected with the (i + 1) th tap in the N taps, and i is greater than or equal to 1 and less than or equal to N-1.

The delay line circuit 13 is configured to, when a write indication signal is detected, delay the write indication signal by a preset delay corresponding to an ith tap of the N taps and send the delay to the address comparison logic circuit 15 through the synchronous logic circuit 14, where the N taps correspond to the N preset delays one to one; the address comparison logic circuit 15 is configured to, when it is detected that the write indication signal jumps from the first logic level to the second logic level at a rising edge of the read clock signal, acquire a read address carried in a currently received read address signal, determine a read-write address difference corresponding to the i-th tap based on the specified write address and the acquired read address, and send the read-write address difference corresponding to the i-th tap to the processor 16; the processor 16 is configured to, when receiving the read-write address difference corresponding to the ith tap, make i equal to i +1, delay the write indication signal by the delay line circuit 13 again by a preset delay corresponding to the ith tap of the N taps, and then send the write indication signal to the address comparison logic circuit 15 by the synchronization logic circuit 14.

Furthermore, the processor 16 may set the currently used tap of the delay line circuit 13, that is, the processor 16 may set the currently used preset delay of the delay line circuit 13, so as to ensure that the delay line circuit 13 may sequentially traverse the N taps to sequentially delay the write indication signal by the N preset delays.

It should be further noted that, in the embodiment of the present invention, the above-mentioned loop operation may be executed through cooperation of the delay line circuit 13, the synchronous logic circuit 14, the address comparison logic circuit 15, and the processor 16, so as to ensure that the read-write address difference corresponding to each tap of the N taps can be obtained, that is, the read-write address difference corresponding to each preset delay of the N preset delays can be obtained, and further, the accuracy of determining the fractional delay by the subsequent processor 16 based on the N read-write address differences can be ensured.

Referring to fig. 6, the synchronization logic circuit 14 includes a plurality of flip-flops P connected in series, each of the plurality of flip-flops P connected in series for receiving the write indication signal at a rising edge of the read clock signal generated by the read clock generation circuit 9.

The first stage flip-flop among the plurality of flip-flops included in the synchronous logic circuit 14 receives a write indication signal at a rising edge of a read clock signal and transmits the write indication signal to the second stage flip-flop, the second stage flip-flop receives the write indication signal at the rising edge of the read clock signal and transmits the write indication signal to the third stage flip-flop, and thus, until the write indication signal is transmitted to the m-th stage flip-flop included in the synchronous logic circuit 14, the m-th stage flip-flop receives the write indication signal at the rising edge of the read clock signal and transmits the write indication signal to the address comparison logic circuit 15, m is a natural number, and m is greater than or equal to 2.

It should be noted that the first-stage flip-flop to the mth-stage flip-flop in the plurality of flip-flops are determined according to a serial sequence of the plurality of flip-flops, that is, the flip-flop connected to the delay line circuit 13 may be determined as a first-stage flip-flop, and the flip-flops subsequent to the first-stage flip-flop are sequentially determined as a second-stage flip-flop and a third-stage flip-flop.

In an embodiment of the present invention, an asynchronous FIFO circuit includes a write clock generation circuit, a read clock generation circuit, a write address generation circuit, a read address generation circuit, a random access memory, a delay line circuit, a synchronous logic circuit, an address comparison logic circuit, and a processor. Wherein, the read address generating circuit can send a plurality of read address signals to the address comparison logic circuit, the write address generating circuit can send a write indication signal to the delay line circuit, because the delay line circuit comprises N preset time delays, the delay line circuit can delay the write indication signal by N preset delays in sequence and then send the delay signal to the address comparison logic circuit through the synchronous logic circuit, the address comparison logic circuit can determine N read-write address differences corresponding to the N preset delays one by one based on the write indication signal and the read address signal, and sends the N read and write address differences to the processor, which may then determine a fractional delay based on the N read and write address differences and the wiring delay, and determining the time delay of the asynchronous FIFO circuit based on the decimal time delay, thereby realizing the accurate determination of the time delay of the asynchronous FIFO circuit.

Fig. 7 is a flowchart of a delay determination method according to an embodiment of the present invention, which may be applied to the asynchronous FIFO circuit shown in any one of fig. 2 to 6, and it can be understood that the method may also be applied to an asynchronous FIFO circuit different from any one of fig. 2 to 6, and when a portion or connection of the asynchronous FIFO circuit shown in any one of fig. 2 to 6, which has a smaller association with a key portion implemented by the method, is changed, the method may still be applied to the changed circuit, for example, when the setting function and connection of the address comparison logic circuit are implemented by another module, such as a processor. Referring to fig. 7, the method includes:

step 701: in the process of performing read operation and write operation on the random access memory, the read address generating circuit sends a plurality of generated read address signals to the address comparison logic circuit, the write address generating circuit sends a generated write indication signal to the delay line circuit, the write indication signal is generated based on at least two write addresses generated by the write address generating circuit, and the write indication signal jumps from a first logic level to a second logic level when the write address generating circuit generates a specified write address.

It should be noted that the designated write address may be preset, for example, the designated write address may be 7, 8, 9, and the like, which is not specifically limited in this embodiment of the present invention.

It should be noted that the random access memory is used for storing data; the read address generating circuit is used for generating a plurality of read address signals, and each read address signal carries a read address; the write address generating circuit is used for generating a plurality of write address signals and write indicating signals, each write address signal carries a write address, the write indicating signals are generated based on at least two write addresses generated by the write address generating circuit, and the write indicating signals jump from a first logic level to a second logic level when the write address generating circuit generates a specified write address; the address comparison logic circuit is used for determining a read-write address difference based on the write indication signal and the read address signal, wherein the read-write address difference is an address difference between a write address for performing write operation on the random access memory and a read address for performing read operation; the delay line circuit is used for delaying a write indication signal input into the delay line circuit.

Step 702: the processor obtains N read-write address differences based on the write indication signal, the plurality of read address signals and the read clock signal generated by the read clock generation circuit through a read address generation circuit, a delay line circuit, a synchronous logic circuit and an address comparison logic circuit, wherein the N read-write address differences correspond to N preset time delays in the delay line circuit one by one, and N is a natural number greater than 1.

It should be noted that N preset time delays may be preset, and this is not specifically limited in the embodiment of the present invention. In addition, preferably, the fractional delay is a delay introduced by a phase difference between the read clock signal and the write clock signal, and the fractional delay is smaller than one clock cycle, so as to ensure that the fractional delay can be determined subsequently based on the N preset delays, a minimum preset delay of the N preset delays may be 0, and a maximum preset delay of the N preset delays may be greater than or equal to one clock cycle. The clock period is the period of the read clock signal or the write clock signal, and the period of the read clock signal is equal to the period of the write clock signal.

Specifically, the operation of acquiring N read/write address differences by the processor through the read address generating circuit, the delay line circuit, the synchronization logic circuit, and the address comparison logic circuit based on the write indication signal, the read address signals, and the read clock signal generated by the read clock generating circuit may include the following steps (1) to (3):

(1) and when the delay line circuit detects the write indication signal, the write indication signal is delayed by a preset delay corresponding to the ith tap in the N taps and then is sent to the address comparison logic circuit through the synchronous logic circuit, wherein i is greater than or equal to 1 and less than or equal to N-1.

The operation of the delay line circuit delaying the write indication signal by a preset delay corresponding to the ith tap of the N taps and then sending the delayed write indication signal to the address comparison logic circuit through the synchronous logic circuit may be: the delay line circuit delays the write indication signal by the ith tap of the N taps by the preset time delay corresponding to the ith tap and then sends the write indication signal to the synchronous logic circuit; when the synchronous logic circuit receives the write indicating signal, the write indicating signal is sent to the address comparison logic circuit after delaying for a first number of clock cycles.

It should be noted that the first value is a value obtained by subtracting 1 from the number of flip-flops included in the synchronous logic circuit.

Since the number of delay sections between each of the N taps and the write address generation circuit is fixed, and each delay section can delay the write indication signal input to the delay section for a fixed time, the N taps correspond to the N preset delays one to one. Therefore, the delay line circuit can delay the write indication signal by the ith tap of the N taps by the preset time delay corresponding to the ith tap and then send the write indication signal to the synchronous logic circuit.

When the synchronous logic circuit receives the write indication signal, the operation of delaying the write indication signal by a first number of clock cycles and then sending the write indication signal to the address comparison logic circuit may be: the first stage flip-flop in the plurality of flip-flops included in the synchronous logic circuit receives the write indication signal at a rising edge of a read clock signal and transmits the write indication signal to the second stage flip-flop, the second stage flip-flop receives the write indication signal at a rising edge of a read clock signal and transmits the write indication signal to the third stage flip-flop, and so on until the write indication signal is transmitted to an m-th stage flip-flop included in the synchronous logic circuit, the m-th stage flip-flop receives the write indication signal at a rising edge of the read clock signal and transmits the write indication signal to the address comparison logic circuit, m is a natural number, and m is greater than or equal to 2.

It should be noted that the first-stage flip-flop to the mth-stage flip-flop in the plurality of flip-flops are determined according to a serial sequence of the plurality of flip-flops, that is, a flip-flop connected to the delay line circuit in the plurality of flip-flops may be determined as a first-stage flip-flop, and flip-flops subsequent to the first-stage flip-flop are sequentially determined as a second-stage flip-flop and a third-stage flip-flop.

Since each flip-flop of the plurality of flip-flops included in the synchronous logic circuit receives the write indication signal at the rising edge of the read clock signal and transmits the write indication signal to the next flip-flop, when the write indication signal is transmitted from one flip-flop to the next flip-flop and is transmitted again from the next flip-flop, the write indication signal is delayed by one clock cycle, and thus, the synchronous logic circuit may delay the write indication signal by the first number of clock cycles.

It should be noted that, when the synchronous logic circuit receives the write indication signal, the operation of delaying the write indication signal by the first number of clock cycles and then sending the delayed write indication signal to the address comparison logic circuit may refer to related technologies, which are not described in detail in this embodiment of the present invention.

(2) When the address comparison logic circuit detects that the write indication signal jumps from the first logic level to the second logic level when the rising edge of the read clock signal, the read address carried in the currently received read address signal is acquired, the read-write address difference corresponding to the ith tap is determined based on the specified write address and the acquired read address, and the read-write address difference corresponding to the ith tap is sent to the processor.

The operation of the address comparison logic circuit determining the read-write address difference corresponding to the ith tap based on the specified write address and the acquired read address may be: the address comparison logic circuit determines an address difference between the specified write address and the acquired read address; the address comparison logic circuit subtracts 1 from the number of the triggers included in the synchronous logic circuit to obtain a first numerical value; and the address comparison logic circuit adds the determined address difference and the first numerical value to obtain a read-write address difference corresponding to the ith tap.

Because the write indication signal is changed from the first logic level to the second logic level when the write address generating circuit generates the specified write address, and the write indication signal is sent to the address comparison logic circuit after being delayed by the synchronous logic circuit for a first number of clock cycles, when the address comparison logic circuit detects that the write indication signal is changed from the first logic level to the second logic level, the write address generating circuit generates the first number of write addresses after generating the specified write address, and therefore, the address difference between the write address currently writing the random access memory and the specified write address is the first number. And because the address comparison logic circuit is used for determining the address difference between the write address for performing the write operation on the random access memory and the read address for performing the read operation at the same time, and the read address signal currently received by the address comparison logic circuit is directly sent to the address comparison logic circuit without delay, when the address comparison logic circuit determines the read-write address difference corresponding to the ith tap based on the specified write address and the acquired read address, the address difference between the specified write address and the acquired read address needs to be added to the first value.

For example, the address comparison logic circuit determines that the address difference between the specified write address and the obtained read address is 6, and the number of the flip-flops included in the synchronous logic circuit is 3, then the number of the flip-flops included in the synchronous logic circuit is reduced by 1 to obtain a first value of 2, and the determined address difference 6 and the first value of 2 are added to obtain a read-write address difference corresponding to the i-th tap of 8.

Wherein the operation of the address comparison logic circuit to determine the address difference between the specified write address and the retrieved read address may be: when the appointed write address is larger than the acquired read address, subtracting the acquired read address from the appointed write address to obtain a second numerical value, and determining the second numerical value as the address difference between the appointed write address and the acquired read address; when the appointed write address is smaller than the acquired read address, subtracting the appointed write address from the acquired read address to obtain a third numerical value, subtracting the third numerical value from the total number of addresses included in the random access memory to obtain a fourth numerical value, and determining the fourth numerical value as the address difference between the appointed write address and the acquired read address; when the specified write address is equal to the acquired read address, if the number of times of writing of the specified write address is the same as the number of times of reading of the acquired read address, determining the address difference between the specified write address and the acquired read address to be 0, and if the number of times of writing of the specified write address is not the same as the number of times of reading of the acquired read address, determining the total number of addresses included in the random access memory to be the address difference between the specified write address and the acquired read address. The number of times of writing the specified write address is the number of times of writing data into the specified write address, and the number of times of reading the acquired read address is the number of times of reading data from the acquired read address.

Each address in the plurality of addresses included in the random access memory may be marked with a read time and a write time of the address, where the write time is a time when data is written to the address, and the read time is a time when data is read from the address.

For example, the designated write address is 8, the acquired read address is 7, and since 8 is greater than 7, the acquired read address 7 is subtracted from the designated write address 8 to obtain a second value of 1, and a second value of 1 is determined as the address difference between the designated write address and the acquired read address.

For another example, the specified write address is 2, the obtained read address is 7, since 2 is smaller than 7, the specified write address is subtracted from the obtained read address to obtain a third value of 5, assuming that the total number of addresses included in the random access memory is 10, the third value is subtracted from the total number of addresses 10 included in the random access memory to obtain a fourth value of 5, and the fourth value of 5 is determined as an address difference between the specified write address and the obtained read address.

For another example, the specified write address is 7, the obtained read address is 7, since the specified write address is equal to the obtained read address, the number of writes of the specified write address and the number of reads of the obtained read address may be determined, assuming that the number of writes of the specified write address is 2 and the number of reads of the obtained read address is 1, determining that the number of writes of the specified write address is different from the number of reads of the obtained read address, assuming that the total number of addresses included in the random access memory is 10, the total number of addresses included in the random access memory may be determined as an address difference between the specified write address and the obtained read address.

It should be noted that, the operation of the address comparison logic circuit to determine the address difference between the specified write address and the acquired read address may also refer to the related art, and this is not described in detail in this embodiment of the present invention.

(3) And when the processor receives the read-write address difference corresponding to the ith tap, enabling i to be i +1, returning to the step (1), delaying the write indication signal by a preset time delay corresponding to the ith tap in the N taps, and then sending the write indication signal to the address comparison logic circuit through the synchronous logic circuit.

It should be noted that, in the embodiment of the present invention, through a cycle operation, it may be ensured that a read-write address difference corresponding to each tap of the N taps is obtained, that is, it may be ensured that a read-write address difference corresponding to each preset delay of the N preset delays is obtained, so that accuracy of determining the decimal delay based on the N read-write address differences by the subsequent processor may be ensured.

Step 703: the processor determines decimal time delay based on the N read-write address differences and the wiring time delay, wherein the wiring time delay is time delay introduced by wiring between the write address generating circuit and the synchronous logic circuit, and the decimal time delay is time delay introduced by phase difference between the read clock signal and the write clock signal.

Further, before the processor determines the decimal time delay based on the N read-write address differences and the wiring time delay, the processor may further obtain a maximum time delay and a minimum time delay introduced by wiring between the write address generation circuit and the synchronous logic circuit from a stored back-end wiring report, and determine an average value of the maximum time delay and the minimum time delay as the wiring time delay, where the back-end wiring report is used to record time delays introduced by all wirings included in the asynchronous FIFO circuit.

For example, if the maximum delay introduced by the wiring between the write address generation circuit and the synchronous logic circuit, which is obtained from the back-end wiring report by the processor, is 0.6ns (nanosecond), and the minimum delay is 0.2ns, the processor may determine the average value of 0.4ns between the maximum delay 0.6ns and the minimum delay 0.2ns as the wiring delay.

It should be noted that, because the positions of the write address generating circuit and the synchronous logic circuit may affect the routing delay, the embodiments of the present invention may constrain the positions of the write address generating circuit and the synchronous logic circuit to be as close as possible when routing the asynchronous FIFO circuit, so as to minimize the variation of the maximum delay and the minimum delay introduced by the routing between the write address generating circuit and the synchronous logic circuit, so that the routing delay determined based on the maximum delay and the minimum delay is as small and stable as possible, thereby ensuring the accuracy of the processor determining the fractional delay based on the routing delay.

Specifically, the processor determines the fractional time delay based on the N read/write address differences and the wiring time delay, and the processor may determine a first time delay from the N preset time delays based on the N read/write address differences, and determine a sum of the first time delay and the wiring time delay as the fractional time delay.

Based on the N read-write address differences, the processor determines a first delay from the N preset delays by: the processor sequences the N read-write address differences based on the N preset time delays to obtain the sequence of the N read-write address differences; the processor acquires a first read-write address difference from the N read-write address differences based on the sequence of the N read-write address differences, wherein the first read-write address difference is determined based on a read-write address difference jumping in the N read-write address differences, and the jumping read-write address difference is a read-write address difference different from the previous read-write address difference; and the processor determines the preset time delay corresponding to the first read-write address difference as a first time delay.

It should be noted that, when the processor ranks the N read/write address differences based on the N preset time delays, the N read/write address differences may be ranked according to a sequence from small to large of the N preset time delays, and of course, the N read/write address differences may also be ranked according to a sequence from large to small of the N preset time delays, which is not specifically limited in this embodiment of the present invention.

For example, the N preset delays are 5ns, 1ns, 2ns, 4ns, and 3ns, and the N read/write address differences are 6, 7, 6, and 7, where the read/write address difference corresponding to 5ns is 6, the read/write address difference corresponding to 1ns is 7, the read/write address difference corresponding to 2ns is 7, the read/write address difference corresponding to 4ns is 6, and the read/write address difference corresponding to 3ns is 7, the processor may sort the N read/write address differences according to a sequence of the N preset delays from small to large, and obtain a sequence of the N read/write address differences of 7, 6, and 6.

For another example, the N preset time delays are 5ns, 1ns, 2ns, 4ns, and 3ns, and the N read-write address differences are 6, 7, 6, and 7, where the read-write address difference corresponding to 5ns is 6, the read-write address difference corresponding to 1ns is 7, the read-write address difference corresponding to 2ns is 7, the read-write address difference corresponding to 4ns is 6, and the read-write address difference corresponding to 3ns is 7, the processor may sort the N read-write address differences according to the sequence of the N preset time delays from large to small, and obtain the sequence of the N read-write address differences as 6, 7, and 7.

Based on the sequence of the N read-write address differences, the processor may obtain a first read-write address difference from the N read-write address differences by: when the sequence of the N read-write address differences is obtained by sequencing according to the sequence of the N preset time delays from small to large, the processor obtains a first jumping read-write address difference from the N read-write address differences, and determines the obtained read-write address difference as a first read-write address difference; and when the sequence of the N read-write address differences is obtained by sequencing according to the sequence of the N preset time delays from large to small, the processor determines the read-write address difference of the last jump from the N read-write address differences, and determines the read-write address difference of the previous bit of the read-write address difference of the last jump as the first read-write address difference.

For example, the sequence of the N read/write address differences is 7, 6, and the sequence of the N read/write address differences is obtained by sorting the N preset time delays from small to large, the processor may obtain a first jump read/write address difference of 6 from the N read/write address differences, and determine 6 as the first read/write address difference.

For another example, the sequence of the N read-write address differences is 6, 7, and the sequence of the N read-write address differences is obtained by sorting according to the N preset time delays from large to small, the processor may determine that the read-write address difference of the last jump is 7 from the N read-write address differences, and determine the read-write address difference 6 that is one bit before the read-write address difference of the last jump as the first read-write address difference.

Further, with reference to a specific example, a principle that the processor determines the first delay from N preset delays based on N read/write address differences, and determines the sum of the first delay and the wiring delay as the fractional delay is described:

fig. 8 is a schematic diagram of a delay line circuit for delaying a write indication signal according to an embodiment of the present invention. Referring to fig. 8, fractional delay is the delay introduced by the phase difference between the write clock signal and the read clock signal; the write address generating circuit generates a write indicating signal, and the write indicating signal jumps from a first logic level 0 to a second logic level 1 on a rising edge a of a write clock signal; n preset time delays in the delay line circuit are a preset time delay 1, a preset time delay 2.. the preset time delay f-1 and a preset time delay f.. the preset time delay N, and the preset time delay 1 is less than the preset time delay 2.. the preset time delay f-1 is less than the preset time delay f.. the preset time delay N is less than the preset time delay.

As shown in fig. 8, when the delay line circuit delays the write indication signal by a preset time delay 1 and a preset time delay 2.. the preset time delay f-1 and then sends the write indication signal to the synchronous logic circuit, the rising edge c of the read clock signal is at the second logic level 1 of the write indication signal. And when the delay line circuit delays the write indication signal by a preset time delay f and then sends the write indication signal to the synchronous logic circuit, the rising edge c of the read clock signal is just positioned at a transition point of the first logic level 0 to the second logic level 1 of the write indication signal.

Since the wiring delay is introduced by the wiring between the write address generating circuit and the synchronous logic circuit, when the rising edge c of the read clock signal is located at a transition point where the first logic level 0 of the write indication signal jumps to the second logic level 1, the write indication signal is delayed by the delay line circuit by the preset delay f, and is also delayed by the wiring delay between the write address generating circuit and the synchronous logic circuit. As can be seen from fig. 8, when the write indication signal is sent to the delay line circuit by the write address generation circuit, the transition point of the first logic level 0 of the write indication signal to the second logic level 1 is at the rising edge a of the write clock signal, and when the write indication signal is delayed by the preset delay f and the wiring delay, the transition point of the first logic level 0 of the write indication signal to the second logic level 1 is at the rising edge c of the read clock signal. Since the fractional delay is introduced by the phase difference between the write clock signal and the read clock signal, that is, the fractional delay is the delay between the rising edge a of the write clock signal and the rising edge c of the read clock signal in fig. 8, the sum of the preset delay f and the wiring delay can be determined as the fractional delay.

Since the rising edge c of the read clock signal is at the second logic level 1 of the write indication signal when the delay line circuit delays the write indication signal by the preset time delay 1 and the preset time delay 2.. the preset time delay f-1 and since the synchronous logic circuit receives the write indication signal only at the rising edge of the read clock signal, the synchronous logic circuit may detect that the write indication signal changes from the first logic level 0 to the second logic level 1 when the delay line circuit delays the write indication signal by the preset time delay 1 and the preset time delay 2.. the preset time delay f-1 and then transmits the write indication signal to the synchronous logic circuit, as shown in fig. 9 (a). Assuming that the synchronous logic circuit includes three flip-flops, that is, the synchronous logic circuit may delay the write indication signal by two clock cycles, at this time, the address comparison logic circuit may detect that the write indication signal jumps from the first logic level 0 to the second logic level 1 at the rising edge e of the read clock signal, and the read address acquired by the address comparison logic circuit is the read address received at the rising edge e of the read clock signal. Since the read-write address difference is determined by the address comparison logic circuit based on the specified write address and the read address obtained when the write indication signal is detected to jump from the first logic level to the second logic level, the read-write address differences corresponding to the preset time delay 1 and the preset time delay 2.

Since the rising edge c of the read clock signal is at the transition point when the write indication signal is delayed by the preset delay f and then sent to the synchronous logic circuit, the rising edge d after the rising edge c of the read clock signal is at the second logic level 1 of the write indication signal, and since the synchronous logic circuit receives the write indication signal only at the rising edge of the read clock signal, when the delay line circuit delays the write indication signal by the preset delay f and then sends the write indication signal to the synchronous logic circuit, as shown in fig. 9(b), the synchronous logic circuit may detect that the write indication signal is transitioned from the first logic level 0 to the second logic level 1 at the rising edge d of the read clock signal. Assuming that the synchronous logic circuit includes three flip-flops, that is, the synchronous logic circuit may delay the write indication signal by two clock cycles, at this time, the address comparison logic circuit may detect that the write indication signal jumps from the first logic level 0 to the second logic level 1 at a rising edge f after a rising edge e of the read clock signal, and the read address acquired by the address comparison logic circuit is the read address received at the rising edge f of the read clock signal. Since the address difference between the read address generated by the read address generating circuit at the rising edge f of the read clock signal and the read address generated at the rising edge E of the read clock signal is 1, the read/write address difference corresponding to the preset time delay f jumps to the address difference obtained by subtracting 1 from the address difference corresponding to any one of the preset time delays 1 and 2.

TABLE 1

In the embodiment of the present invention, only the correspondence between the preset delay and the read/write address difference shown in table 1 is taken as an example for description, and table 1 does not limit the embodiment of the present invention.

Therefore, when the sequence of the N read/write address differences is obtained by sequencing the N preset time delays from small to large, the preset time delay f is a preset time delay corresponding to the first jumping read/write address difference in the N read/write address differences, that is, the preset time delay f is the first time delay.

And when the sequence of the N read-write address differences is obtained by sequencing according to the sequence of the N preset time delays from large to small, the previous read-write address difference of the last jump read-write address difference in the N read-write address differences is the same as the read-write address difference of the first jump. Therefore, when the sequence of the N read-write address differences is obtained by sorting the N preset time delays from large to small, the preset time delay f is a preset time delay corresponding to a read-write address difference one bit before the last jump read-write address difference in the N read-write address differences, that is, the preset time delay f is the first time delay.

Therefore, the processor determines the fractional time delay based on the N read/write address differences and the wiring time delay, may determine the first time delay from the N preset time delays based on the N read/write address differences, and determine the sum of the first time delay and the wiring time delay as the fractional time delay.

Further, after the processor determines the fractional time delay based on the N read-write address differences and the wiring time delay, the processor may also determine a second time delay based on the first time delay, the second time delay being a time delay capable of eliminating a metastable state of the synchronous logic circuit; the processor resets the read address generated by the read address generation circuit through the address comparison logic circuit based on the first time delay and the second time delay.

Wherein, the processor, based on the first time delay, determining the second time delay may be: when the first time delay is smaller than or equal to the signal stabilization time, determining the sum of the first time delay and the first preset time delay as a second time delay, wherein the first preset time delay is larger than the signal stabilization time and smaller than a third time delay, the signal stabilization time is the sum of the setup time and the hold time of a first-stage trigger, the first-stage trigger is a trigger which is connected with a delay line circuit in a plurality of triggers included in a synchronous logic circuit, the third time delay is a difference value between a clock period and the signal stabilization time, and the signal stabilization time is smaller than the third time delay; or when the first time delay is greater than the signal stabilization time and less than the third time delay, subtracting a second preset time delay from the first time delay to obtain a second time delay, wherein the second preset time delay is greater than the signal stabilization time and less than or equal to the decimal time delay; or when the first time delay is greater than or equal to the third time delay, subtracting the first preset time delay from the first time delay to obtain a second time delay.

Since the first stage flip-flop in the synchronous logic circuit receives the write indication signal sent by the delay line circuit at the rising edge of the read clock signal, in order to ensure that the first stage flip-flop can receive a stable write indication signal at the rising edge of the read clock signal, the write indication signal should be stable and unchanged within a first specified time before the rising edge of the read clock signal arrives, and stable and unchanged within a second specified time after the rising edge of the read clock signal arrives, otherwise, the write indication signal received by the first stage flip-flop may be unstable, which may cause the synchronous logic circuit to generate a metastable state.

It should be noted that the first specified time may be greater than or equal to the setup time of the first stage flip-flop, and the second specified time may be greater than or equal to the hold time of the first stage flip-flop, which is not specifically limited in this embodiment of the present invention.

Because the rising edge of the read clock signal is located at the transition point of the write indication signal when the delay line circuit delays the write indication signal by the first delay and sends the write indication signal to the synchronous logic circuit, in order to eliminate the metastable state of the synchronous logic circuit and ensure that the write indication signal received by the synchronous logic circuit is relatively stable, the second delay can be determined based on the first delay, and then the delay line circuit can delay the write indication signal by the second delay and send the write indication signal to the synchronous logic circuit, so as to ensure that the rising edge of the read clock signal is located at the stable point of the write indication signal, and further ensure that the synchronous logic circuit can receive the stable write indication signal at the rising edge of the read clock signal.

As shown in fig. 10(a), the signal stabilization time is t, when the first delay is less than or equal to the signal stabilization time, the sum of the first delay and the first preset delay may be determined as the second delay, and at this time, when the delay line circuit delays the write indication signal by the second delay and sends the write indication signal to the synchronous logic circuit, the rising edge c of the read clock signal is located in the stabilization region a of the write indication signal, so that the synchronous logic circuit is ensured to receive the stable write indication signal at the rising edge of the read clock signal, and the occurrence of the metastable state is avoided.

As shown in fig. 10(B), the signal stabilization time is t, and when the first time delay is greater than the signal stabilization time and less than the third time delay, the second time delay may be obtained by subtracting the second preset time delay from the first time delay, and at this time, when the delay line circuit delays the write indication signal by the second time delay and sends the write indication signal to the synchronous logic circuit, the rising edge c of the read clock signal is exactly located in the stabilization region B of the write indication signal, so that the synchronous logic circuit is ensured to receive the stable write indication signal at the rising edge of the read clock signal, and the occurrence of the metastable state is avoided.

As shown in fig. 10(c), the signal stabilization time is t, and when the first time delay is greater than or equal to the third time delay, the first time delay may be subtracted by the first preset time delay to obtain a second time delay, and at this time, when the delay line circuit delays the write indication signal by the second time delay and then sends the write indication signal to the synchronous logic circuit, the rising edge c of the read clock signal is exactly located in the stabilization region B of the write indication signal, so that the synchronous logic circuit is ensured to receive the stable write indication signal at the rising edge of the read clock signal, and the occurrence of the metastable state is avoided.

The operation of the processor resetting the read address generated by the read address generation circuit through the address comparison logic circuit based on the first time delay and the second time delay may include the following two ways:

the first mode is as follows: the processor sends the first time delay to the address comparison logic circuit, and sets the time delay of the delay line circuit as a second time delay; when the delay line circuit detects a write indication signal, the write indication signal is sent to the address comparison logic circuit through the synchronous logic circuit; when the address comparison logic circuit detects that the write indication signal jumps from a first logic level to a second logic level on the rising edge of the read clock signal, acquiring a read address carried in a currently received read address signal, and determining a second read-write address difference based on the specified write address and the acquired read address, wherein the second read-write address difference is a read-write address difference corresponding to a second time delay; when the address comparison logic circuit receives the first time delay, the read address currently generated by the read address generation circuit is reset based on the specified write address, the first time delay, the second read-write address difference and the specified read-write address difference.

It should be noted that the specified read/write address difference may be preset, and for example, the specified read/write address difference may be 7, 8, and the like, which is not specifically limited in this embodiment of the present invention.

Because the time delay of the asynchronous FIFO circuit comprises integer time delay and decimal time delay, and the decimal time delay is the time delay introduced by the phase difference between the read clock signal and the write clock signal, the decimal time delay of the same asynchronous FIFO circuit is fixed. In order to ensure that the time delay of the asynchronous FIFO circuit is fixed, it is necessary to ensure that the address difference between the write address for performing write operation and the read address for performing read operation on the random access memory at the same time is the specified read-write address difference, thereby ensuring that the integer time delay of the same asynchronous FIFO circuit is fixed. However, due to the influence of some non-measurable factors, the read address generated by the read address generation circuit may be incorrect, and at this time, the address difference between the write address for performing the write operation on the random access memory and the read address for performing the read operation at the same time is not the specified read-write address difference, so that the time delay of the asynchronous FIFO circuit determined based on the specified read-write address difference is incorrect. Therefore, in the working process of the asynchronous FIFO circuit, the address difference between the write address for performing write operation on the random access memory and the read address for performing read operation can be determined in real time, and when the address difference is not detected to be the specified read-write address difference, the read address generated by the read address generating circuit is reset through the address comparison logic circuit, so that the address difference between the write address for performing write operation on the random access memory and the read address for performing read operation at the same time is ensured to be the specified read-write address difference, and the accuracy of the time delay of the asynchronous FIFO circuit determined based on the specified read-write address difference is ensured.

The address comparison logic circuit is used for determining the read-write address difference between the write address for performing write operation on the random access memory and the read address for performing read operation on the random access memory based on the write indication signal sent by the synchronous logic circuit and the read address signal sent by the read address generation circuit, and resetting the read address generated by the read address generation circuit when the read-write address difference is not equal to the specified read-write address difference. When the synchronous logic circuit is in a metastable state, the write indication signal received by the synchronous logic circuit may be inaccurate, thereby affecting the accuracy of the read-write address difference determined by the address comparison logic circuit, and further causing the address comparison logic circuit to have errors in resetting the read address generated by the read address generation circuit. And because the second time delay can eliminate the metastable state of the synchronous logic circuit, the processor can set the time delay of the delay line circuit as the second time delay, and the synchronous logic circuit can receive a stable write indication signal at the moment, so that the accuracy of the read-write address difference determined by the address comparison logic circuit can be ensured, and the address comparison logic circuit can be further ensured to correctly reset the read address generated by the read address generation circuit.

The purpose of resetting the read address generated by the read address generating circuit by the address comparison logic circuit is to make the address difference between the write address currently writing to the random access memory and the read address currently reading be the designated read-write address difference. Therefore, after the processor sets the delay line circuit to the second delay, when the delay line circuit detects a write indication signal, the write indication signal may be sent to the address comparison logic circuit by the synchronization logic circuit, so that the address comparison logic circuit may reset the read address currently generated by the read address generation circuit based on the specified write address, the first delay, the second read-write address difference, and the specified read-write address difference when detecting that the write indication signal jumps from the first logic level to the second logic level.

In addition, when the address comparison logic circuit detects that the write indication signal jumps from the first logic level to the second logic level when the rising edge of the read clock signal detects that the write indication signal jumps from the first logic level to the second logic level, the operation of obtaining the read address carried in the currently received read address signal and determining the second read/write address difference based on the specified write address and the obtained read address is similar to the operation of the step (2) in the step 702, which is not described in detail in the embodiment of the present invention.

The second mode is as follows: when the N preset time delays comprise a second time delay, the processor acquires a second read-write address difference from the N read-write address differences, wherein the second read-write address difference is a read-write address difference corresponding to the second time delay; the processor sends the first time delay and the second read-write address difference to the address comparison logic circuit, and sets the time delay of the delay line circuit as a second time delay; when the delay line circuit detects the write indication signal, the write indication signal is sent to the address comparison logic circuit through the synchronous logic circuit; when the address comparison logic circuit detects that the writing indication signal jumps from a first logic level to a second logic level and receives a first time delay and a second reading and writing address difference when the rising edge of the reading clock signal, the address comparison logic circuit resets the reading address currently generated by the reading address generation circuit based on the specified writing address, the first time delay, the second reading and writing address difference and the specified reading and writing address difference.

It should be noted that, when the N preset delays include a second delay, at this time, the N read/write address differences include a read/write address difference corresponding to the second delay, so that the processor may directly obtain the read/write address difference corresponding to the second delay from the N read/write address differences, and send the read/write address difference corresponding to the second delay to the address comparison logic circuit, and at this time, the address comparison logic circuit does not need to determine the read/write address difference corresponding to the second delay again through the delay line circuit, the synchronous logic circuit, and the read address generation circuit, thereby saving processing resources in the asynchronous FIFO circuit.

In the first and second manners, the operation of the address comparison logic circuit resetting the read address currently generated by the read address generation circuit based on the specified write address, the first time delay, the second read/write address difference, and the specified read/write address difference may include one of the following manners (1) and (2):

(1) and when the first time delay is less than or equal to the signal stabilization time and the address difference obtained by adding 1 to the second read-write address difference is not equal to the specified read-write address difference, the address comparison logic circuit determines the first address based on the specified write address and the number of the triggers included in the synchronous logic circuit, and sets the read address currently generated by the read address generation circuit as the first address.

When the first delay is less than or equal to the signal settling time, as shown in fig. 10(a), when the delay line circuit delays the write indication signal by the second delay and transmits the write indication signal to the synchronous logic circuit, the rising edge c of the read clock signal is located in the settling region a of the first logic level 0 of the write indication signal, and the rising edge d following the rising edge c of the read clock signal is located in the settling region B of the second logic level 1 of the write indication signal. Since the synchronous logic circuit receives the write indication signal only at the rising edge of the read clock signal, the synchronous logic circuit can detect that the write indication signal jumps from the first logic level 0 to the second logic level 1 at the rising edge d of the read clock signal. As shown in fig. 9(b), assuming that the synchronous logic circuit includes three flip-flops, the address comparison logic circuit may detect that the write indication signal jumps from the first logic level 0 to the second logic level 1 at a rising edge f after a rising edge e of the read clock signal, and the read address acquired by the address comparison logic circuit is the read address received at the rising edge f of the read clock signal.

When the address difference between the write address currently performing the write operation on the random access memory and the read address performing the read operation is the specified read-write address difference, the read-write address difference determined by the address comparison logic circuit based on the read address received at the rising edge e of the read clock signal should be the specified read-write address difference, and since the address difference between the read address generated by the read address generation circuit at the rising edge f of the read clock signal and the read address generated at the rising edge e of the read clock signal is 1, when the delay line circuit delays the write indication signal by the second time delay, the second read-write address difference determined by the address comparison logic circuit based on the read address received at the rising edge f of the read clock signal is smaller than the specified read-write address difference by 1. Therefore, when the first time delay is less than or equal to the signal stabilization time and the address difference obtained by adding 1 to the second read-write address difference is not equal to the specified read-write address difference, it can be determined that the address difference between the write address currently performing the write operation on the random access memory and the read address performing the read operation is not the specified read-write address difference. At this time, the address comparison logic circuit may determine the first address based on the designated write address and the number of flip-flops included in the synchronization logic circuit, and set the read address currently generated by the read address generation circuit as the first address.

The operation of the address comparison logic circuit determining the first address based on the specified write address and the number of flip-flops included in the synchronization logic circuit may be: the address comparison logic circuit determines a write address of the current write operation to the random access memory based on the specified write address and the number of triggers included in the synchronous logic circuit, and determines a first address based on the difference between the write address and the specified read-write address, wherein the address difference between the write address and the first address is the specified read-write address difference.

The operation of the address comparison logic circuit determining the current write address for performing the write operation on the random access memory based on the specified write address and the number of the flip-flops included in the synchronization logic circuit may be: the address comparison logic circuit subtracts 1 from the number of the triggers included in the synchronous logic circuit to obtain a first numerical value, adds 1 to the first numerical value to obtain a fifth numerical value, determines an address with the fifth numerical value as an address difference with the specified write address based on the specified write address and the fifth numerical value, and determines the determined address as the write address for performing write operation on the random access memory at present.

When the first delay is less than or equal to the signal settling time, as shown in fig. 9(b), the write indication signal generated by the write address generation circuit jumps from the first logic level 0 to the second logic level 1 at the rising edge a of the write clock signal, the delay line circuit delays the write indication signal by the second delay, and the synchronous logic circuit detects that the write indication signal jumps from the first logic level 0 to the second logic level 1 at the rising edge d of the read clock signal. Since the rising edge d of the read clock signal is after the rising edge b of the write clock signal and the rising edge b of the write clock is after the rising edge a of the write clock, the write address generation circuit may generate a write address at the rising edge b of the write clock signal during a period from when the write indication signal makes a transition at the rising edge a of the write clock signal to when the synchronization logic circuit detects the transition of the write indication signal at the rising edge d of the read clock signal. In the process that the synchronous logic circuit sends the writing indication signal to the address comparison logic circuit, the synchronous logic circuit delays the writing indication signal by a first number of clock cycles, so that the writing address generating circuit generates a first number of writing addresses in the process. That is, when the address comparison logic circuit detects that the write indication signal jumps from the first logic level 0 to the second logic level 1, the write address generation circuit generates the first value plus 1 write address after generating the specified write address, and the fifth value is determined by adding 1 to the first value, so that the address difference between the write address currently writing to the random access memory and the specified write address is the fifth value, and the address whose address difference with the specified write address is the fifth value can be determined as the write address currently writing to the random access memory.

The operation of determining the first address based on the difference between the write address currently performing the write operation on the random access memory and the specified read/write address may refer to related technologies, which are not described in detail in the embodiments of the present disclosure.

For example, if the specified read-write address difference is 8, the specified write address is 9, and the number of the flip-flops included in the synchronous logic circuit is 3, the number of the flip-flops included in the synchronous logic circuit is subtracted from 3 by 1 to obtain a first numerical value of 2, and the first numerical value is added by 1 to obtain a fifth numerical value of 3, then the write address currently performing the write operation on the random access memory is a write address 12 whose address difference from the specified write address 9 is 3. Since the specified read-write address difference is 8, the first address may be determined to be 4 based on the write address 12 and the specified read-write address difference 8, and thereafter, the address comparison logic circuit may set the read address currently generated by the read address generation circuit to the first address 4.

(2) And when the first time delay is longer than the signal stabilization time and the second read-write address difference is not equal to the specified read-write address difference, the address comparison logic circuit determines a second address based on the specified write address and the number of triggers included in the synchronous logic circuit, and sets the read address currently generated by the read address generation circuit as the second address.

When the first delay is longer than the signal settling time, as shown in fig. 10(B) or fig. 10(c), the delay line circuit delays the write indication signal by the second delay and then transmits the write indication signal to the synchronous logic circuit, and the rising edge c of the read clock signal is located in the settling region B of the second logic level 1 of the write indication signal. Since the synchronous logic circuit receives the write indication signal only at the rising edge of the read clock signal, the synchronous logic circuit can detect that the write indication signal jumps from the first logic level 0 to the second logic level 1 at the rising edge c of the read clock signal. As shown in fig. 9(a), assuming that the synchronous logic circuit includes three flip-flops, the address comparison logic circuit may detect that the write indication signal jumps from the first logic level 0 to the second logic level 1 at the rising edge e of the read clock signal, and the read address obtained by the address comparison logic circuit is the read address received at the rising edge e of the read clock signal.

When the address difference between the write address currently performing the write operation on the random access memory and the read address performing the read operation is the specified read-write address difference, the address comparison logic circuit determines that the read-write address difference determined based on the read address received at the rising edge e of the read clock signal should be the specified read-write address difference, and therefore, when the first time delay is greater than the signal stabilization time and the second read-write address difference is not equal to the specified read-write address difference, it can be determined that the address difference between the write address currently performing the write operation on the random access memory and the read address performing the read operation is not the specified read-write address difference. At this time, the address comparison logic circuit may determine the second address based on the designated write address and the number of flip-flops included in the synchronization logic circuit, and set the read address currently generated by the read address generation circuit as the second address.

The address comparison logic circuit may determine, based on the specified write address and the number of flip-flops included in the synchronization logic circuit, that the second address is to be operated as: the address comparison logic circuit determines a write address for performing write operation on the random access memory at present based on the specified write address and the number of triggers included in the synchronous logic circuit, and determines a second address based on the difference between the write address and the specified read-write address, wherein the address difference between the write address and the second address is the specified read-write address difference.

The operation of the address comparison logic circuit determining the current write address for performing the write operation on the random access memory based on the specified write address and the number of the flip-flops included in the synchronization logic circuit may be: the address comparison logic circuit subtracts 1 from the number of the flip-flops included in the synchronous logic circuit to obtain a first numerical value, determines an address with the first numerical value as an address difference with the designated write address based on the designated write address, and determines the determined address as the write address for performing write operation on the random access memory at present.

When the first delay is longer than the signal stabilization time, as shown in fig. 9(a), the write indication signal generated by the write address generation circuit jumps from the first logic level 0 to the second logic level 1 on the rising edge a of the write clock signal, and after the delay line circuit delays the write indication signal by the second delay, the synchronous logic circuit detects that the write indication signal jumps from the first logic level 0 to the second logic level 1 on the rising edge c of the read clock signal. Since the rising edge c of the read clock signal follows the rising edge a of the write clock signal, the write address generation circuit does not generate a write address during the time period from when the write indication signal makes a transition at the rising edge a of the write clock signal to when the synchronization logic circuit detects the transition of the write indication signal at the rising edge c of the read clock signal. In the process that the synchronous logic circuit sends the writing indication signal to the address comparison logic circuit, the synchronous logic circuit delays the writing indication signal by a first number of clock cycles, so that the writing address generating circuit generates a first number of writing addresses in the process. That is, when the address comparison logic circuit detects that the write indication signal jumps from the first logic level 0 to the second logic level 1, the write address generation circuit generates the first number of write addresses after generating the specified write address, so that the address difference between the write address currently performing the write operation to the random access memory and the specified write address is the first number, and therefore, the address whose address difference from the specified write address is the first number can be determined as the write address currently performing the write operation to the random access memory.

The operation of determining the second address based on the difference between the current write address for performing the write operation on the random access memory and the specified read/write address may refer to related technologies, which are not described in detail in the embodiments of the present disclosure.

For example, the specified read/write address difference is 8, the specified write address is 9, the number of flip-flops included in the synchronous logic circuit is 3, and the first numerical value is 2 by subtracting 1 from the number 3 of flip-flops included in the synchronous logic circuit, then the write address currently performing a write operation on the random access memory is the write address 11 having the address difference with the specified write address 9 being the first numerical value 2, and since the specified read/write address difference is 8, it may be determined that the second address is 3 based on the write address 11 and the specified read/write address difference 8, and then, the address comparison logic circuit may set the read address currently generated by the read address generation circuit to be the second address 3.

Step 704: the processor determines the time delay of the asynchronous FIFO circuit based on the fractional time delay.

Specifically, the processor obtains an integer time delay, and determines the sum of the fractional time delay and the integer time delay as the time delay of the asynchronous FIFO circuit, wherein the integer time delay is the time delay introduced by the address difference between a write address for performing write operation and a read address for performing read operation on the random access memory at the same time.

The processor obtains the integer time delay, and may determine the product of the specified read-write address difference and the clock cycle as the integer time delay.

For example, if the specified read/write address difference is 8 and the clock period is 10ns, the processor may multiply the specified read/write address difference 8 by the clock period of 10ns to obtain an integer time delay of 80ns,

further, when the processor receives a reset setting instruction, the power-on reset value of the write address is set as a third address, the power-on reset value of the read address is set as a fourth address, the address difference between the third address and the fourth address is a specified read-write address difference, the power-on reset value of the write address is an initial write address generated by the write address generation circuit when the write address is powered on, and the power-on reset value of the read address is an initial read address generated by the read address generation circuit when the read address is powered on.

In addition, in the embodiment of the present invention, the power-on reset value of the write address is set as the third address, the power-on reset value of the read address is set as the fourth address, and the address difference between the third address and the fourth address is the specified read-write address difference, so that it can be ensured that the address difference between the write address for performing the write operation and the read address for performing the read operation on the random access memory is the specified read-write address difference when the asynchronous FIFO circuit is powered on and starts to operate, thereby ensuring that the time delays of the asynchronous FIFO circuit in the whole operating process are the same, and ensuring the accuracy of the determined time delay of the asynchronous FIFO circuit.

It should be noted that, in the embodiment of the present invention, after determining the delay of the asynchronous FIFO circuit, the asynchronous FIFO circuit for determining the delay may be applied to a digital signal transceiver of a base station in a wireless communication system, for example, may be applied to a digital signal transceiver in a MIMO (Multi-Input Multi-Output) or a massive MIMO Multi-antenna system of the base station, so as to ensure that the receiving and transmitting timings of the antennas are synchronized with respect to an air interface signal, and improve the timing synchronization accuracy of the base station. Of course, the asynchronous FIFO circuit for determining time delay may also be applied to a synchronous transmission network, for example, an ethernet using IEEE-1588 protocol, so as to ensure accurate transmission of time stamps in IEEE-1588 protocol in the network and improve the clock synchronization precision between network nodes.

In the embodiment of the invention, in the process of performing read operation and write operation on the random access memory, the read address generating circuit sends a plurality of generated read address signals to the address comparison logic circuit, the write address generating circuit sends a generated write indication signal to the delay line circuit, the processor obtains N read-write address differences which are in one-to-one correspondence with N preset delays in the delay line circuit through the read address generating circuit, the delay line circuit, the synchronous logic circuit and the address comparison logic circuit on the basis of the write indication signal, the read address signals and a read clock signal generated by the read clock generating circuit, and then the processor determines the fractional delay on the basis of the N read-write address differences and the wiring delay and determines the delay of the asynchronous FIFO circuit on the basis of the fractional delay, so that the accurate determination of the delay of the asynchronous FIFO circuit is realized. In addition, in the embodiment of the present invention, the processor may further determine a second time delay based on the first time delay, and reset the read address generated by the read address generating circuit through the address comparison logic circuit based on the first time delay and the second time delay.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. An asynchronous FIFO circuit, comprising: the circuit comprises a write clock generating circuit, a read clock generating circuit, a write address generating circuit, a read address generating circuit, a random access memory, a delay line circuit, a synchronous logic circuit, an address comparison logic circuit and a processor;

the output end of the read clock generating circuit is further connected with the input end of the read address generating circuit, the output end of the read address generating circuit is connected with the second input end of the random access memory, the output end of the read address generating circuit is further connected with the third input end of the address comparison logic circuit, and the first output end of the address comparison logic circuit is connected with the input end of the processor;

the read address generating circuit is used for sending the generated read address signals to the address comparison logic circuit;

the processor is configured to obtain, through the read address generating circuit, the delay line circuit, the synchronous logic circuit, and the address comparison logic circuit, N read-write address differences based on the write indication signal, the multiple read address signals, and a read clock signal generated by the read clock generating circuit, where the N read-write address differences correspond to N preset delays in the delay line circuit one to one, and N is a natural number greater than 1;

2. The asynchronous FIFO circuit of claim 1 wherein,

and the second output end of the address comparison logic circuit is connected with the setting end of the read address generating circuit.

3. The asynchronous FIFO circuit of claim 1 or 2,

and the second output end of the processor is connected with the reset end of the write address generating circuit, and the third output end of the processor is connected with the reset end of the read address generating circuit.

4. The asynchronous FIFO circuit of any of claims 1-3, wherein the delay line circuit comprises: n-1 delay sections and N taps;

5. The asynchronous FIFO circuit of any one of claims 1-4, wherein the synchronous logic circuit comprises a plurality of serially connected flip-flops, each flip-flop of the plurality of serially connected flip-flops to receive the write indication signal on a rising edge of the read clock signal generated by the read clock generation circuit.

6. The asynchronous FIFO circuit of claim 4 wherein,

the delay line circuit is configured to, when the write indication signal is detected, delay the write indication signal by a preset delay corresponding to an ith tap of the N taps and then send the delay to the address comparison logic circuit through the synchronous logic circuit, where the N taps correspond to the N preset delays one to one;

7. A method for determining a delay applied to an asynchronous FIFO circuit according to any one of claims 1 to 6, the method comprising:

8. The method of claim 7, wherein said delay line circuit comprises N-1 delay sections and N taps, said N taps corresponding one-to-one to said N predetermined time delays;

9. The method of claim 8, wherein the address comparison logic circuit determines a read-write address difference corresponding to the i-th tap based on a specified write address and an obtained read address, comprising:

10. The method of any of claims 7-9, wherein the processor determines a fractional delay before based on the N read and write address differences and a routing delay, further comprising:

11. The method of any of claims 7-10, wherein the processor determines a fractional delay based on the N read and write address differences and a routing delay, comprising:

12. The method of claim 11, wherein the processor determining a first latency from the N preset latencies based on the N read and write address differences comprises:

13. The method of claim 11 or 12, wherein the processor determines a fractional delay based on the N read and write address differences and a routing delay, further comprising:

14. The method of claim 13, wherein the processor determines a second time delay based on the first time delay, comprising:

15. The method of claim 13 or 14, wherein the processor resetting the read address generated by the read address generation circuit based on the first latency and the second latency by the address comparison logic circuit, comprises:

the processor sets the delay of the delay line circuit to the second delay;

16. The method of claim 13 or 14, wherein the processor resetting the read address generated by the read address generation circuit based on the first latency and the second latency by an address comparison logic circuit, comprises:

the processor sets the delay of the delay line circuit to the second delay;

17. The method of claim 15 or 16, wherein the address comparison logic circuitry resets the read address currently generated by the read address generation circuitry based on the specified write address, the first latency, the second read-write address difference, and a specified read-write address difference, comprising:

18. The method of any of claims 7-17, wherein the processor determining the latency of the asynchronous FIFO circuit based on the fractional latency comprises:

19. The method of any one of claims 7-18, further comprising: