CN103677732A - Fifo device and method thereof - Google Patents
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- CN103677732A CN103677732A CN201210322132.7A CN201210322132A CN103677732A CN 103677732 A CN103677732 A CN 103677732A CN 201210322132 A CN201210322132 A CN 201210322132A CN 103677732 A CN103677732 A CN 103677732A
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Abstract
The invention relates to an asynchronous FIFO device. The asynchronous FIFO device comprises at least one of an asynchronous FIFO storage device, a first counter module which is capable of producing Gray codes and provided with a writing pointer, a second counter module which is capable of producing Gray codes and provided with a reading pointer, a first shifter which is capable of producing a virtual writing pointer by applying a first delay value to the writing pointer, and a second shifter which is capable of producing a virtual reading pointer by applying a second delay value to the reading pointer, and at least one of a first comparator and a second comparator, wherein the first comparator can output an 'occupied' referent according to the comparison between the writing pointer and the virtual reading pointer, and the second comparator can output an 'unoccupied' referent according to the comparison between the reading pointer and the virtual writing pointer. Therefore, the asynchronous FIFO device is improved.
Description
Technical field
The present invention relates generally to first-in first-out (First Input First Output, FIFO) device, more specifically, relates to asynchronous first-in first-out device.
Background technology
Knownly in data processing equipment, with asynchronous first-in/first-out memory, between the first and second clock zones, transmit data, data processing equipment is microchip designs/realization for example, and such means are typically under the asynchronous situation of the first clock zone and second clock territory (namely the clock frequency in the clock frequency of the first clock zone and second clock territory is asynchronous).
Conventionally, write operation in a clock zone (can be called and write clock zone) and read operation in another clock zone (can be called and read clock zone).In FIFO storer, the quantity of occupied storage unit is an important indicator of judgement sky/full state.Because calculate the quantity of occupied storage unit in FIFO storer, relate to read pointer and write pointer, thereby carry out continually the asynchronous-sampling to pointer.As known, Gray code, also referred to as reflected binary coding, is a kind of binary digital system, wherein between any two continuous codings, only has a bit to change.Reading and writing pointer is converted into Gray code conventionally to alleviate or to eliminate the mistake producing in asynchronous-sampling.
Because Gray code is non-weighted code, when relating to the numerical evaluation of Gray code, need to change Gray code into natural binary coding.Some bits in natural binary coding are that all bits of corresponding Gray code carry out the result of XOR one by one.Therefore, Gray code is realized and is related to a large amount of logic gates to the microchip of binary coding converter, and the bit bit wide of its processing delay and Gray code is proportionate.Therefore, Gray code to the practical application of binary coding converter is limited to shorter bit bit wide and lower frequency of operation.
Reach out of contior a kind of traditional means that enables/make of the read-write operation of FIFO storer is related to the comparison to the calculating of the use degree of depth of FIFO storer and the FIFO use degree of depth and a protection interval; this needs at least three totalizers, a comparer and a selector switch, and the Gray code of two pointers is to binary coding converter.The term here " degree of depth " refers to the quantity of storage unit, and " the use degree of depth " refers to the quantity of the storage unit of using in FIFO storer.In the situation that calculating is designed to flowing water pattern, processing delay will increase, and also be proportionate with the bit bit wide of pointer.
Summary of the invention
So one object of the present invention is to provide a kind of improved Asynchronous FIFO Design, it has alleviated above-mentioned problem.
According to one embodiment of present invention, a kind of device comprises having the asynchronous FIFO memory of write port and read port, first counter module of write pointer that can produce Gray code and second counter module that can produce the read pointer of Gray code.This device also comprises at least one in the first shift unit and the second shift unit, wherein the first shift unit can produce virtual write pointer by the write pointer of described Gray code is applied to the first length of delay, and the second shift unit can produce virtual read pointer by the read pointer of described Gray code is applied to the second length of delay.In addition, this device also comprises at least one in the first comparer and the second comparer, wherein the first comparer can be exported ' expiring ' indicant according to the comparison of the write pointer of described Gray code and described virtual read pointer, and the second comparer can be exported ' sky ' indicant according to the comparison of the read pointer of described Gray code and described virtual write pointer.
' expiring ' indicant can be used as the enable signal of write operation, and ' sky ' indicant can be as the enable signal of read operation.The first length of delay and the second length of delay are all adjustable, as the protection interval between write pointer and read pointer, so that avoid the loss of data inharmonious and that therefore cause between read operation and write operation.
Because the first and second shift units, the first and second comparers are used to replace Gray code to binary coding converter and for calculating the circuit of the use degree of depth of FIFO storer, asynchronous FIFO device is being improved aspect processing time delay, the logic gate quantity of using and power consumption.
According to another embodiment of the invention, the first shift unit in asynchronous FIFO device or the second shift unit are barrel shifter.
According to another embodiment of the invention, the first shift unit in asynchronous FIFO device or the second shift unit are for triggering (flip-flop) shift unit.
According to another embodiment of the invention, provide a kind of control to there is the method for the asynchronous FIFO memory of write port and read port.The method comprises the following steps: the write pointer that produces Gray code; Produce the read pointer of Gray code; By being applied to a length of delay, the read pointer of described Gray code produces virtual read pointer; According to the comparison of the write pointer of described Gray code and described virtual read pointer, export ' expiring ' indicant.
According to another embodiment of the invention, provide a kind of control to there is the method for the asynchronous FIFO memory of write port and read port.The method comprises the following steps: the write pointer that produces Gray code; Produce the read pointer of Gray code; By being applied to a length of delay, the write pointer of described Gray code produces virtual write pointer; According to the comparison of the read pointer of described Gray code and described virtual write pointer, export ' sky ' indicant.
Technical characterictic of the present invention and advantage have more than been summarized so that the detailed description below the present invention is easier to understand.Other features and advantages of the present invention will be described below, and it has formed the theme of claim of the present invention.Those skilled in the art will be understood that disclosed concept and embodiment can easily be used as revising or design other for realizing the basis of structure or the flow process of the object identical with the present invention.Those skilled in the art should also be understood that such equivalent constructions does not deviate from the spirit and scope of appended claims.
Accompanying drawing explanation
By reference to the accompanying drawings, the detailed description about the preferred embodiments of the present invention below will be easier to understand.The present invention is explained by way of example, is not limited to accompanying drawing, and in accompanying drawing, similarly Reference numeral is indicated similar element.
Fig. 1 is the block diagram of the logical organization of device according to an embodiment of the invention;
Fig. 2 is the process flow diagram of the method for control asynchronous FIFO memory according to an embodiment of the invention;
Fig. 3 is the process flow diagram of the method for control asynchronous FIFO memory according to another embodiment of the invention.
Embodiment
The detailed description of accompanying drawing is intended to the explanation as currently preferred embodiment of the present invention, but not is intended to represent that the present invention can be achieved only form.It should be understood that function identical or that be equal to can be completed by the different embodiment that are intended to be contained within the spirit and scope of the present invention.
Those skilled in the art will be understood that means described herein and function can realize by the software function in conjunction with program control microprocessor and multi-purpose computer, and/or use ASIC(Application Specific Integrated Circuit) (ASIC) to realize.What will also be understood that is, although the present invention mainly describes with the form of method and apparatus, the present invention also can be embodied as computer program and comprise computer processor and the system that is connected to the storer of processor, and wherein storer is encoded by a plurality of programs of work that can complete the function disclosing herein.
The term here " degree of depth " refers to the quantity of storage unit, and " the use degree of depth " refers to the quantity of the storage unit of using in FIFO storer.Write pointer or read pointer can be corresponding to arbitrary storage unit of FIFO storer.The total depth of FIFO storer is configured to the bit bit wide time power of 2 write pointer or read pointer conventionally.For example, the bit bit wide of write pointer or read pointer is 10, and FIFO storer is configured to have 1024 and storage unit.
Fig. 1 is the block diagram of the logical organization of device 10 according to an embodiment of the invention.Device 10 comprises asynchronous FIFO memory 100, the first counter module 110, the second counter module 120, the first shift unit 113, the second shift unit 124, the first comparer 115 and the second comparer 126.For easy, some other parts or function element is not shown in figure.In certain embodiments, device 10 can be by realizing (Field Programmable Gate Array, FPGA) with field programmable gate array.
FIFO storer 100 is for example a twoport FIFO storer, has a write port and a read port, and wherein the clock frequency of write port is different from the clock frequency of read port.All functional entitys of being controlled by same clock with write port can be called as writes clock zone.Similarly, the functional entitys that all and read port is controlled by same clock can be called as reads clock zone.
The first counter module 110 can produce the write pointer of Gray code, and the second counter module 120 can produce the read pointer of Gray code.More specifically, the first counter module 110 or the second counter module 120 can comprise that a counter for generation of binary-coded write pointer or read pointer and one are for being converted to binary-coded pointer the converter of the pointer of Gray code.
The first shift unit 113 can, by the write pointer of described Gray code is applied to the first length of delay, also referred to as the first skew, and produce virtual write pointer.The second shift unit 124 can, by the read pointer of described Gray code is applied to the second length of delay, also referred to as the second skew, and produce virtual read pointer.The first length of delay and the second length of delay are all adjustable, as the protection interval between write pointer and read pointer, so that avoid the loss of data inharmonious and that therefore cause between read operation and write operation.
The first comparer 115 and the first counter module 110 are all in writing clock zone, coupled to each other.The first comparer 115 can be exported ' expiring ' indicant according to the comparison of the write pointer of described Gray code and described virtual read pointer, and it can be as the enable signal of write operation.In the situation that the write pointer of described Gray code equals ' expiring ' indicant of the full state of described virtual read pointer output indication FIFO storer, so write operation is prohibited; Otherwise ' expiring ' indicant of the non-full state of output indication FIFO storer, so write operation is activated.' expiring ' indicant is 1-0 signal normally in practice.
Similarly, the second comparer 126 and the second counter module 120 are all in reading clock zone, coupled to each other.The second comparer 126 can be exported ' sky ' indicant according to the comparison of the read pointer of described Gray code and described virtual write pointer, and it can be as the enable signal of read operation.In the situation that the read pointer of described Gray code equals ' sky ' indicant of the dummy status of described virtual write pointer output indication FIFO storer, so read operation is prohibited; Otherwise ' sky ' indicant of the non-dummy status of output indication FIFO storer, so read operation is activated.' sky ' indicant is 1-0 signal normally in practice.
The second shift unit 126 and the first comparer 115 all relate to the control that enables of write operation.The first shift unit 113 and the second comparer 126 all relate to the control that enables of read operation.Two sampling thief (not shown) can be for asynchronous-sampling.The first skew (length of delay) and the second skew (length of delay) are all adjustable, are used as the protection interval between write pointer and read pointer, so that avoid causing inharmonious between the read operation of loss of data and write operation.Protection interval can be any integer value that is less than FIFO storer total depth, and it is less than FIFO storer total depth half conventionally.Preferably, protection interval is less than 1/4th of FIFO storer total depth, thereby can effectively utilize FIFO storer.
Distance between write pointer and read pointer is less than protection interval, needs to force to forbid write operation or read operation, so that avoid logic error and the loss of data causing thus or misread.
For example, when device 10 energising operation first or replacement, in FIFO storer, there is no valid data.Possible situation is that write pointer and the read pointer of FIFO storer 100 is mutually the same, and this may cause wrong ' sky ' indicant of the second comparer 126 outputs.In this case, need to force to forbid read operation until the distance between write pointer and read pointer is greater than protection interval.After this, device 10 starts normal work.
In this embodiment, the first shift unit 113 is in writing clock zone, and the second shift unit 124 is in reading clock zone.A sampling thief of reading in clock zone is configured to sample imaginary formulation pointer and the pointer of sampling is sent to the second comparer 126.Write a sampling thief in clock zone be configured to sample virtual read pointer the pointer of sampling is sent to the first comparer 115.
In certain embodiments, the first shift unit 113 can and be coupled in the sampling thief for the write pointer of the Gray code of sampling in reading clock zone.Write pointer after displacement, also referred to as virtual write pointer, is sent to the second comparer 126 from the first shift unit 113.
In some other embodiment, the second shift unit 124 can be in writing clock zone and being coupled in the sampling thief for the read pointer of the Gray code of sampling.Read pointer after displacement, also referred to as virtual read pointer, is sent to the first comparer 115 from the second shift unit 124.
Because the first and second shift units 113 and the 124, first and second comparers 115 and 126 are used to replace Gray code to binary coding converter and for calculating the circuit of the use degree of depth of FIFO storer, asynchronous FIFO device 10 is being improved processing aspect time delay, the logic gate quantity of using and power consumption.The first shift unit 113 or the second shift unit 124 advantageously trigger (flip-flop) shift unit by use and are achieved, more preferably by using barrel shifter to be achieved, because the logic gate quantity of processing delay and use is all less than Gray to binary coding converter, especially when the bit of pointer is for example wider than 8.In the situation that asynchronous FIFO device 10 is achieved by use Xilinx FPGA, the first and second shift units 113 and 124 can use LUT-SRL module wherein and be achieved.
Fig. 2 is the process flow diagram of the method 200 of control asynchronous FIFO memory according to an embodiment of the invention.As shown in the figure, method 200 comprises step 210,220,230 and 240.
In step 210, produce the write pointer of the Gray code of asynchronous FIFO memory.
In step 220, produce the read pointer of the Gray code of asynchronous FIFO memory.Then in step 230, by the read pointer of described Gray code being applied to a length of delay (skew), produce virtual read pointer.
In step 240, according to the comparison of the write pointer of described Gray code and described virtual read pointer, export ' expiring ' indicant, it can be as the enable signal of write operation.In the situation that the write pointer of Gray code equals virtual read pointer, ' expiring ' indicant of the full state of output indication FIFO storer, so the write operation of FIFO storer is prohibited.In the situation that the write pointer of Gray code is different from virtual read pointer, ' expiring ' indicant of the non-full state of output indication FIFO storer, so the write operation of FIFO storer is activated.' expiring ' indicant is 1-0 signal normally in practice.Skew between virtual read pointer and the read pointer of Gray code is adjustable, can be as the protection interval between write pointer and read pointer, so that avoid inharmonious between write operation and read operation.Distance between write pointer and read pointer is less than protection interval, needs to force to forbid that write operation or read operation are until the distance between write pointer and read pointer is greater than protection interval, so that avoid logic error and consequent loss of data or misread.
In certain embodiments, step 230 is carried out after reading clock zone relaying step 220.The step of asynchronous-sampling is carried out after step 230, thereby step 240 is relatively to carry out between the virtual read pointer of sampling and the write pointer of Gray code.
In some other embodiment, adopt step to carry out after step 220, step 230 is carried out after writing clock zone relaying sampling step, thus virtual read pointer is to produce by the read pointer of sampling is applied to skew.
Fig. 3 is the process flow diagram of the method 300 of control asynchronous FIFO memory according to another embodiment of the invention.As shown in the figure, method 300 comprises step 310,320,330 and 340.
In step 310, produce the write pointer of the Gray code of asynchronous FIFO memory.Then in step 320, by the write pointer of described Gray code being applied to a length of delay (skew), produce virtual write pointer.
In step 330, produce the read pointer of the Gray code of asynchronous FIFO memory.
In step 340, according to the comparison of the read pointer of described Gray code and described virtual write pointer, export ' sky ' indicant, it can be as the enable signal of read operation.In the situation that the read pointer of Gray code equals virtual write pointer, ' sky ' indicant of the dummy status of output indication FIFO storer, so the read operation of FIFO storer is prohibited.In the situation that the read pointer of Gray code is different from virtual write pointer, ' sky ' indicant of the non-dummy status of output indication FIFO storer, so the read operation of FIFO storer is activated.' sky ' indicant is 1-0 signal normally in practice.Skew between virtual write pointer and the write pointer of Gray code is adjustable, can be as the protection interval between write pointer and read pointer, so that avoid inharmonious between write operation and read operation.
Distance between write pointer and read pointer is less than protection interval, needs to force to forbid that write operation or read operation are until the distance between write pointer and read pointer is greater than protection interval, so that avoid logic error and consequent loss of data or misread.
For example, when FIFO storer is switched on operation or replacement first, in FIFO storer, there is no valid data.Possible situation is that write pointer and the read pointer of FIFO storer is mutually the same, and this may cause wrong ' sky ' indicant.In this case, need to force to forbid read operation until the distance between write pointer and read pointer is greater than protection interval.After this, method 300 starts normal operation.
In certain embodiments, step 320 is carried out after writing clock zone relaying step 310.Asynchronous-sampling step is carried out after step 320, thereby step 340 is relatively to carry out between the virtual write pointer of sampling and the read pointer of Gray code.
In some other embodiment, asynchronous-sampling step is carried out after step 310, and step 320 is carried out after reading clock zone relaying asynchronous-sampling step, thereby virtual write pointer is to produce by the write pointer of sampling is applied to skew.
Although illustrated and described different embodiments of the invention, the present invention is not limited to these embodiment.In the situation that not deviating from as the described the spirit and scope of the present invention of claims, many modifications, change, distortion, to substitute and be equal to be obvious to those skilled in the art.
Claims (12)
1. a device, comprising:
The asynchronous FIFO memory with write port and read port;
Can produce first counter module and second counter module that can produce the read pointer of Gray code of the write pointer of Gray code;
At least one in the first shift unit and the second shift unit, wherein the first shift unit can produce virtual write pointer by the write pointer of described Gray code is applied to the first length of delay, and the second shift unit can produce virtual read pointer by the read pointer of described Gray code is applied to the second length of delay;
At least one in the first comparer and the second comparer, wherein the first comparer can be exported ' expiring ' indicant according to the comparison of the write pointer of described Gray code and described virtual read pointer, and the second comparer can be exported ' sky ' indicant according to the comparison of the read pointer of described Gray code and described virtual write pointer.
2. device as claimed in claim 1, is characterized in that, described the first shift unit or the second shift unit are barrel shifter.
3. device as claimed in claim 1, is characterized in that, described the first shift unit or the second shift unit are for triggering shift unit.
4. device as claimed in claim 1, is characterized in that, described the first length of delay is different from described the second length of delay.
5. device as claimed in claim 1, is characterized in that, described the first counter module and described the first comparer are in same clock zone, and described the second counter module and the second comparer are in another clock zone.
6. device as claimed in claim 1, is characterized in that, described device is realized by FPGA.
7. control has a method for the asynchronous FIFO memory of write port and read port, comprises the following steps:
Produce the write pointer of Gray code;
Produce the read pointer of Gray code;
By being applied to a length of delay, the read pointer of described Gray code produces virtual read pointer;
According to the comparison of the write pointer of described Gray code and described virtual read pointer, export ' expiring ' indicant.
8. method as claimed in claim 7, is characterized in that, in the situation that the write pointer of described Gray code equals ' expiring ' indicant of the full state of described virtual read pointer output indication.
9. method as claimed in claim 7, is characterized in that, in the situation that the write pointer of described Gray code is different from ' expiring ' indicant of the non-full state of described virtual read pointer output indication.
10. control has a method for the asynchronous FIFO memory of write port and read port, comprises the following steps:
Produce the write pointer of Gray code;
Produce the read pointer of Gray code;
By being applied to a length of delay, the write pointer of described Gray code produces virtual write pointer;
According to the comparison of the read pointer of described Gray code and described virtual write pointer, export ' sky ' indicant.
11. methods as claimed in claim 10, is characterized in that, in the situation that the read pointer of described Gray code equals ' sky ' indicant of described virtual write pointer output indication dummy status.
12. methods as claimed in claim 10, is characterized in that, in the situation that the read pointer of described Gray code is different from ' sky ' indicant of the non-dummy status of described virtual write pointer output indication.
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| WO2016187781A1 (en) * | 2015-05-25 | 2016-12-01 | 华为技术有限公司 | Packet processing method and apparatus |
| CN106681687A (en) * | 2016-12-30 | 2017-05-17 | 周阳 | FIFO data balanced output method and output device thereof |
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| CN109155798A (en) * | 2016-05-27 | 2019-01-04 | 华为技术有限公司 | A kind of asynchronous FIFO circuit and time delay determine method |
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| CN106681687A (en) * | 2016-12-30 | 2017-05-17 | 周阳 | FIFO data balanced output method and output device thereof |
| CN107220023A (en) * | 2017-06-29 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | A kind of embedded configurable FIFO memory |
| CN115481079A (en) * | 2021-06-15 | 2022-12-16 | 珠海一微半导体股份有限公司 | Data scheduling system, reconfigurable processor and data scheduling method |
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