CN103853694A - Implementation method for reconfigurable state machine - Google Patents
Implementation method for reconfigurable state machine Download PDFInfo
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Abstract
The invention provides an implementation method and an implementation device for a reconfigurable state machine. The method includes the following steps: a central processing unit reconfigures a state transition table stored in a first dual-port RAM (random access memory) via a address-writing line and a data-writing line of the first dual-port RAM; the central processing unit reconfigures a signal output code table stored in a second dual-port RAM via a address-writing line and a data-writing line of the second dual-port RAM. By utilizing a central processor to reconfigure the state transition table and the signal output code table of the dual-port RAM memory-type state machine, the invention realizes the reconfigurability of the state machine, not only a Moore state machine but also a Mealy-type state machine can be implemented, the implementation structure is simple, the cost is lower, the complex state machine can be effectively and dynamically reconfigured in a programmable logic device, and the state machine is easy to maintain and can flexibly meet the requirement of an actual design.
Description
Technical field
The present invention relates to Digital Signals field, relate in particular to a kind of implementation method and device of restructural state machine.
Background technology
Most of digital display circuit all comprises control module and data cell, control module is made up of state machine conventionally, control module receives the status information of external signal and data cell generation, produces control signal, is to realize digital display circuit important channel reliable, that effectively control.
Finite state machine (Finite State Machine, FSM), claim again finite-state automata, be called for short state machine, to represent limited state and the mathematical model of the behavior such as transfer and action between these states, in the design of digital programmable logical device, finite state machine is the hardware time order circuit being made up of register group and combinational logic, its state in the clock hopping edge moment from another state of state shift, next state not only can depend on each input value, can also depend on current state, here, described state refers to limited the state being made up of 1 and 0 assembled state of register group, conventionally use binary number coded representation, meanwhile, state machine can be created in the clock hopping edge moment and carry out the complex control logic of switch, is the control core of mathematical logic.Further, whether relevant with input according to the output of state machine, state machine can be divided into two large classes: Moore type state machine and Mealy type state machine.The output of Moore type state machine is only relevant with current state; The output of Mealy type state machine is not only relevant with current state, and also relevant with input value.
A kind of register that customizes state by the state machine of classic method design, register is fixed, do not possess reconfigurable function, conventionally can only meet the demand of one group of control module, if need to realize many group control modules, just need to design multiple state machines meets, usual way is the new FPGA (Field Programmable Gate Array) version of compiling, reload version by central processing unit or single-chip microcomputer and carry out the switching of state machine, the loading of FPGA (Field Programmable Gate Array) and configuration enter the time that storer need to be longer, can not work in time, therefore, state machine can not be dynamically, be reconstructed rapidly, cause the inconvenience in use.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of implementation method and device of restructural state machine, can realize as required the reconstruct of state machine, reduces and realizes cost.
For achieving the above object, technical scheme of the present invention is achieved in that
An implementation method for restructural state machine, described method comprises:
CPU (central processing unit) is reconstructed the state-transition table being stored in described the first dual port RAM by write address line and the write data line of the first Double Port Random Memory RAM;
CPU (central processing unit) is reconstructed the signal output encoder table being stored in described the second dual port RAM by write address line and the write data line of the second dual port RAM.
The write address line of described CPU (central processing unit) by the first dual port RAM and write data line to be stored in state-transition table in described the first dual port RAM be reconstructed into:
CPU (central processing unit) is by write address line and the write data line of the first dual port RAM, state transitions condition using state machine is carried out addressing as address, write in the state-transition table being stored in described the first dual port RAM the next state of corresponding state machine as data.
State the write address line of CPU (central processing unit) by the second dual port RAM and write data line to be stored in signal output encoder table in described the second dual port RAM be reconstructed into:
CPU (central processing unit), by write address line and the write data line of the second dual port RAM, is carried out addressing using output transform condition as address, writes in the signal output encoder table being stored in described the second dual port RAM using corresponding control signal as data.
Described method also comprises:
Address calculation calculates first according to the current state of the state machine of the first dual port RAM output and the external input signal that receives and reads address and second and read address;
Described the first dual port RAM is read address according to described first and is read described state-transition table, carries out state transitions, and described the second dual port RAM is read address read signal output encoder table according to described second, output control signal.
Described address calculation calculates first according to the current state of the state machine of the first dual port RAM output and the external input signal that receives and reads address and second and read address and be:
Address calculation is to the current state the receiving processing of shifting left, current state after displacement and described external input signal are added, obtain first and read address, wherein, described first reads the current state of the high bit representation state machine of address, and described first reads the current initial conditions of low bit representation state machine of address; Or to the processing of shifting left of described external input signal, external input signal after described current state and displacement is added, obtain first and read address, wherein, described first reads the current initial conditions of high bit representation state machine of address, and described first reads the current state of the low bit representation state machine of address;
In the time that the state transitions of state machine is only relevant to the current state of state machine, current state is read to address as second and export, otherwise, read address using described first and read address as second and export.
Read address when address calculation using described first and read address while exporting as second, described method also comprises:
The state-transition table of the signal output encoder table of described the second dual port RAM storage and described the first dual port RAM storage is merged, obtain state transitions and signal output encoder table, and be stored in described the first dual port RAM or the second dual port RAM; Wherein, in described state transitions and signal output encoder table, store the next State-output of the high-order or low bit representation state machine of data, the control signal of the low level of described storage data or the output of high bit representation.
Described the first dual port RAM is read address according to described first and is read described state-transition table, carries out state transitions and is:
Described the first dual port RAM is read address according to described first, reads described first and reads storage content corresponding to address, exports as the current state of described state machine; Wherein, the current state before the described first high-order or low bit representation state machine state of reading address shifts, described first reads the low level of address or the current outside initial conditions of high bit representation state machine.
Described the second dual port RAM is read address read signal output encoder table according to described second, and output control signal is:
Described the second dual port RAM is read address according to described second, reads described second and reads storage content corresponding to address, and described storage content is exported as control signal; Wherein, the current state before the described second high-order or low bit representation state machine state of reading address shifts, described second reads the low level of address or the current initial conditions of high bit representation state machine.
Described CPU (central processing unit) is central processor CPU or single-chip microcomputer.
An implement device for restructural state machine, described device comprises: CPU (central processing unit), the first dual port RAM and the second dual port RAM; Wherein,
Described CPU (central processing unit), is reconstructed the state-transition table that is stored in described the first dual port RAM for the write address line by described the first dual port RAM and write data line; Also for the write address line by the second dual port RAM and write data line, the signal output encoder table that is stored in described the second dual port RAM is reconstructed.
Described CPU (central processing unit), specifically for passing through write address line and the write data line of the first dual port RAM, state transitions condition using state machine is carried out addressing as address, write in the state-transition table being stored in described the first dual port RAM the next state of corresponding state machine as data.
Described CPU (central processing unit), specifically for passing through write address line and the write data line of the second dual port RAM, carry out addressing using output transform condition as address, write corresponding control signal as data in the signal output encoder table being stored in described the second dual port RAM.
Described device also comprises: address calculation; Wherein,
Described address calculation, reads address and second and reads address for calculate first according to the current state of the state machine of the first dual port RAM output and the external input signal that receives;
Described the first dual port RAM, reads described state-transition table for reading address according to described first, carries out state transitions;
Described the second dual port RAM, for reading address read signal output encoder table, output control signal according to described second.
Described address calculation, comprises shift unit, totalizer and selector switch; Wherein,
Described shift unit, for carrying out shifting processing to the current state receiving or external input signal;
Described totalizer, for the current state after displacement and described external input signal are added, obtains first and reads address; Or the external input signal after current state and displacement is added, obtains first and read address;
Described selector switch, in the time that the state transitions of state machine is only relevant to the current state of state machine, reads address using current state as second and exports, otherwise, read address using described first and read address as second and export.
Described the first dual port RAM, specifically for reading address according to described first, reads described first and reads storage content corresponding to address, exports as the current state of described state machine; Wherein, the current state before the described first high-order or low bit representation state machine state of reading address shifts, described first reads low level or the current initial conditions of high bit representation state machine of address.
Described the second dual port RAM, specifically for reading address according to described second, reads described second and reads storage content corresponding to address, and described storage content is exported as control signal; Wherein, the current state before the described second high-order or low bit representation state machine state of reading address shifts, described second reads low level or the current initial conditions of high bit representation state machine of address.
Described CPU (central processing unit) is central processor CPU or single-chip microcomputer.
By central processing unit, the state-transition table to dual port RAM memory state machine and signal output encoder table are reconstructed in the present invention, realize the restructural of state machine, not only can realize Moore type state machine, also can realize Mealy type state machine, implementation structure is simple, and cost is lower, can be effectively in programmable logic device (PLD), dynamically reconstruct complex state machine, easy care, meets the needs of actual design neatly.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the implementation method of restructural state machine of the present invention;
Fig. 2 is the idiographic flow schematic diagram of the implementation method embodiment of restructural state machine of the present invention;
Fig. 3 is the structural representation of the implement device of restructural state machine of the present invention;
Fig. 4 is the structure refinement schematic diagram of the address calculation of implement device shown in Fig. 3;
Fig. 5 is the state transitions schematic diagram of Mealy type state machine in the implementation method embodiment mono-of restructural state machine of the present invention;
Fig. 6 is the state transitions schematic diagram of Moore type state machine in the implementation method embodiment bis-of restructural state machine of the present invention.
Embodiment
Double Port Random Memory (Random Access Memory, RAM) has completely independently data line, address wire and read-write control line of two covers, and its maximum feature is storage data sharing, is applicable to real-time data buffer storage.
Basic thought of the present invention is: CPU (central processing unit) is reconstructed the state-transition table being stored in described the first dual port RAM by write address line and the write data line of the first dual port RAM; CPU (central processing unit) is reconstructed the signal output encoder table being stored in described the second dual port RAM by write address line and the write data line of the second dual port RAM.
For making the object, technical solutions and advantages of the present invention clearer, by the following examples and with reference to accompanying drawing, the present invention is described in more detail.
Fig. 1 shows the synchronous method realization flow signal of data of the present invention, and as shown in Figure 1, described method comprises the steps:
Here, described state-transition table comprises dual port RAM address and two list items of storage content, and wherein, the high position (or low level) in described dual port RAM address represents the current state before described state machine state shifts; Low level (or high-order) in described dual port RAM address represents the current outside initial conditions of state machine; The next state that described in described storage content representation, state machine state shifts.Be N when described state machine contains maximum number of states, when maximum input signal quantity is X, the degree of depth of this state-transition table is 2
x+M, the data bit width of storage content is M, wherein, the value of described M is more than or equal to Log
2n.
In addition, when the number of states of state machine is less than 2
mtime, inevitably there will be residual state.And in the time that this residual state is not reasonably processed, state machine may enter uncertain state, consequence is that state machine occurs of short duration out of control or cannot break away from residual state all the time and lose normal function to external world.Therefore, the address space at residual state place is set to conventionally: the value of described address space generally can be pointed to the initial state of state machine, makes state machine in the time makeing mistakes, still can get back to original state; And be to be understood that, in the time that the number of significant digit of the input signal of state machine is less than reserved input signal figure place X, in state table, can produce the address space of redundancy, but the value of these address spaces is clear and definite, because the value of these unnecessary figure places is 0 or 1 will can not affect the state transitions result of state machine.
Particularly, CPU (central processing unit) is by write address line and the write data line of the first dual port RAM, state transitions condition using state machine is carried out addressing as address, write in the state-transition table being stored in described the first dual port RAM using the next state of corresponding state machine as data; Here, described state transitions condition comprises the current state of described state machine and current outside initial conditions, according to state transitions condition, the dual port RAM address list item of described state-transition table is carried out to addressing; The next state of the described state machine of correspondence is write to the storage content list item of described state-transition table.This section of something wrong, the data of dual port RAM storage write, but address is not, and address is that itself is intrinsic, if you have selected fixing address, as long as the content of corresponding address is carried out to write operation.Be amended as follows:
Here, described signal output encoder table comprises dual port RAM address and two list items of storage content, and wherein, the high position (or low level) in described dual port RAM address represents the current state before described state machine state shifts; Low level (or high-order) in described dual port RAM address represents the current initial conditions of state machine; The control signal of state machine output described in described storage content representation.In the time that the control signal of described state machine output comprises maximum quantity and is K, the degree of depth of described signal output encoder table is 2
x+M, the data bit width of storage content is K.
Particularly, CPU (central processing unit) writes output transform condition and control signal in the signal output encoder table being stored in described the second dual port RAM respectively by write address line and the write data line of the second dual port RAM; Here, described output transform condition comprises the current state of described state machine and current outside initial conditions, as address, the dual port RAM address list item of described signal output encoder table is carried out to addressing using output transform condition, write the storage content list item of described signal output encoder table using the described control signal of correspondence as data.
Further, as shown in Figure 2, described method not only can comprise step 101-102 as above, can also comprise the steps:
Here, address calculation, to the current state the receiving processing of shifting left, is added the current state after displacement and described input signal, obtains first and reads address; Here, described shifting processing is specifically by the X position that moves to left by the current state of binary representation, here, described X is the input signal number receiving, now, described first reads the current state of the high bit representation state machine of address, and described first reads the current initial conditions of low bit representation state machine of address; Be to be understood that, described address calculation can also be to the processing of shifting left of described external input signal, external input signal after described current state and displacement is added, obtain first and read address, here, described shifting processing is specifically by the M position that moves to left with the input signal of binary representation, here, described M is the data bit width of storage content, and described first reads the current initial conditions of high bit representation state machine of address, and described first reads the current state of the low bit representation state machine of address;
In the time that the state transitions of state machine is only relevant to the current state of state machine, when described state machine is all Moore type state machine, current state is read to address as second and export; Otherwise described state machine comprises Mealy type state machine, read address using described first and read address as second and export.
Further, read address when described address calculation using described first and read address while exporting as second, in the time that described state machine comprises Mealy type state machine, the state-transition table of the signal output encoder table of described the second dual port RAM storage and described the first dual port RAM storage can also be merged, obtain state transitions and signal output encoder table, and be stored in described the first dual port RAM or the second dual port RAM; Wherein, the degree of depth of described state transitions and signal output encoder table is 2
x+M, the data bit width of storage content is (K+M), and a high position (or low level) for described storage content represents the next State-output of state machine, and the low level (or high-order) of described storage data represents the control signal of output.
Particularly, described the first dual port RAM is read address according to described first, reads described first and reads storage content corresponding to address, exports as the current state of described state machine; Wherein, described first high position (or low level) of reading address represents the current state before state machine state shifts, and the described first low level (or high-order) of reading address represents the current outside initial conditions of state machine.
Described the second dual port RAM is read address according to described second, reads described second and reads storage content corresponding to address, and described storage content is exported as control signal; Wherein, described second high position (or low level) of reading address represents the current state before state machine state shifts, and the described second low level (or high-order) of reading address represents the current outside initial conditions of state machine.
In addition, should be appreciated that described step 101-102 and step 103-104 do not have inevitable sequencing.
Fig. 3 shows the structure of the implement device of restructural state machine of the present invention, and as shown in Figure 3, described device comprises: CPU (central processing unit) 31, the first dual port RAM 32 and the second dual port RAM 33; Wherein,
Described CPU (central processing unit) 31, is reconstructed the state-transition table that is stored in described the first dual port RAM 32 for the write address line by described the first dual port RAM 32 and write data line; Also for the write address line by the second dual port RAM 33 and write data line, the signal output encoder table that is stored in described the second dual port RAM 33 is reconstructed.Here, described state-transition table comprises dual port RAM address and two list items of storage content, and wherein, the high position (or low level) in described dual port RAM address represents the current state before described state machine state shifts; Low level (or high-order) in described dual port RAM address represents the current outside initial conditions of state machine; The next state that described in described storage content representation, state machine state shifts.
Described signal output encoder table comprises dual port RAM address and two list items of storage content, and wherein, the high position (or low level) in described dual port RAM address represents the current state before described state machine state shifts; Low level (or high-order) in described dual port RAM address represents the current outside initial conditions of state machine; The control signal of state machine output described in described storage content representation.
Further, described CPU (central processing unit) 31, specifically for passing through write address line and the write data line of the first dual port RAM 32, state transitions condition using state machine is carried out addressing as address, write in the state-transition table being stored in described the first dual port RAM 32 using the next state of state machine as data.
Further, described CPU (central processing unit) 31, specifically for by write address line and the write data line of the second dual port RAM 33, carry out addressing taking output transform condition as address, write control signal as data in the signal output encoder table being stored in described the second dual port RAM 33.
Further, described device also comprises: address calculation 34; Wherein,
Described address calculation 34, calculates first for the current state of the state machine exported according to the first dual port RAM 32 and the external input signal that receives and reads address and second and read address;
Described the first dual port RAM 32, reads described state-transition table for reading address according to described first, carries out state transitions;
Described the second dual port RAM 33, for reading address read signal output encoder table, output control signal according to described second.
Further, with reference to Fig. 4, described address calculation 34 comprises shift unit 341, totalizer 342 and selector switch 343; Wherein,
Described shift unit 341, for carrying out shifting processing to the current state receiving or external input signal; Here, described shifting processing is specifically by the X position that moves to left by the current state of binary representation, and here, described X is the number of the input signal that receives; Or by the M position that moves to left with the input signal of binary representation, here, described M is the data bit width of storage content;
Described totalizer 342, for the current state after displacement and described external input signal are added, obtains first and reads address; Or the external input signal after current state and displacement is added, obtains first and read address;
Described selector switch 343, in the time that the state transitions of state machine is only relevant to the current state of state machine, reads address using current state as second and exports, otherwise, read address using described first and read address as second and export.
Wherein, described the first dual port RAM 32, specifically for reading address according to described first, reads described first and reads storage content corresponding to address, exports as the current state of described state machine; Wherein, described first high position (or low level) of reading address represents the current state before state machine state shifts, and the described first low level (or high-order) of reading address represents the current initial conditions of state machine.
Wherein, described the second dual port RAM 33, specifically for reading address according to described second, reads described second and reads storage content corresponding to address, and described storage content is exported as control signal; Wherein, described second high position (or low level) of reading address represents the current state before state machine state shifts, and the described second low level (or high-order) of reading address represents the current initial conditions of state machine.
Further, described CPU (central processing unit) specifically can be by central processing unit (CPU) or chip microcontroller.
In the implementation method embodiment mono-of the restructural state machine of the present invention illustrating respectively below in conjunction with Fig. 5 and Fig. 6, in Mealy type state machine and embodiment bis-, the signal of the state transitions of Moore type state machine is further described.
Fig. 5 shows the state transitions of Mealy type state machine, and this state machine comprises one of four states: A, B, C and D altogether, and there are two input signal I outside
0and I
1.State A has three branches: work as I
0=0 o'clock, state A kept; Work as I
0=1, I
1=0 time, jump to state B from state A; Work as I
0=1, I
1, jump to state C from state A at=1 o'clock; The next state of state B is C; The next state of state C is D; State D has 2 branches: work as I
0, jump to state A from state D at=0 o'clock; Work as I
0=1 o'clock, state D kept.The relation of input signal, current state and output signal that meanwhile, this state machine is corresponding is as shown in Table 1:
Table one
Fig. 6 shows the state transitions of Moore type state machine, and this state machine also comprises one of four states: A, B, C and D, and there are two input signal I outside
0and I
1.State A has two branches: work as I
1=0 o'clock, state A kept; Work as I
1, jump to state B from state A at=1 o'clock; The next state of state B is C; The next state of state C is D; State D has two branches: work as I
0, jump to state A from state D at=0 o'clock; Work as I
0, jump to state B from state D at=1 o'clock.Meanwhile, the current state that this state machine is corresponding and the relation of output signal be as shown in Table 2:
| Current state | Output signal |
| A（00） | C 0=0；C 1=0 |
| B（01） | C 0=0；C 1=1 |
| C（10） | C 0=1；C 1=0 |
| D（11） | C 0=1；C 1=1 |
Table two
Particularly, in the time wanting state machine as shown in Figure 5 and Figure 6 of reconstruct, comprise the steps:
Particularly, the degree of depth of described state-transition table is 2
x+M, data bit width is M, wherein M is binary number, meets 2
mbe more than or equal to N.Mealy type state machine and Moore type state machine all contain four different conditions (N=4), and 2 external input signals (X=2), and therefore, the degree of depth of described state-transition table is 16, data bit width is 2.
Particularly, described four duties: state A, state B, state C and state D, can use respectively binary number: 00,01,10,11 represent, in described state-transition table, the high two digit address of dual port RAM address represents current state, low two digit address represents initial conditions, i.e. input signal: I
0and I
1, wherein, I
0in a high position.
Step 2, CPU (central processing unit) can be reconstructed signal output encoder table by write address line and write data line port: be reconstructed according to the different state transitions condition of these two state machines and the corresponding relation of output signal;
Particularly, can be found out by Fig. 5 and Fig. 6, the quantity of the output control signal of Mealy type state machine is that the output quantity of 3, Moore type state machine is 2, and therefore, maximum output quantity K are 3.Owing to including Mearly type state machine, therefore, the degree of depth of described signal output encoder table is 2
x+M=16(address bit wide is 4), data bit width is 3.
Finally can obtain the state-transition table of the Mealy type state machine as shown in table three and table five respectively and signal output encoder table, state-transition table and the signal output encoder table of the Moore type state machine as shown in table four and table six respectively:
Table three
Wherein, in table three, the 1st classifies dual port RAM address as, and the 2nd and the 3rd row are respectively the annotation (current state and initial conditions), the 4th of high-low position in this dual port RAM address and classify storage content as, represent the next state of state machine, particularly:
1) when dual port RAM address is 0000 and 0001, the current state of state machine is A (00), outside initial conditions I
0i
1be respectively 00 and 01, according to Fig. 5, state A is at external condition I
0be 0 o'clock, state remains A (00), and the data of therefore storing under 0000 and 0001 address are all 00; In the time that dual port RAM address is 0010, current state is A (00), outside initial conditions I
0i
1be 10, according to Fig. 5, next state is B(01), the value of the data of 0010 address storage is 01; In the time that address is 0011, current state is A (00), outside initial conditions I
0i
1be 11, according to Fig. 5, next state is C(10), therefore the value of the data of this address storage is 10;
2) when dual port RAM address is 0100 ~ 0111, the current state of state machine is B (01), because the next state of state B can only be D(11), therefore the value of the data of this sector address storage is all 11;
3) address is 1000 ~ 1011, and current state is C (10), because the next state of state C is D(11), therefore the storage data of this sector address are all 11.
4) when dual port RAM address is 1100 ~ 1101, the current state of state machine is D(11), as outside initial conditions I
0be 0, according to Fig. 5, next state transition is to A(00), the storage content of these two addresses is all 00; When dual port RAM address is 1110 ~ 1111, current state is D, outside initial conditions I
0be 1, according to Fig. 5, next state remains D(11), therefore the storage data of 1110 and 1111 addresses are all 11.
Obtain the state-transition table of Moore type state machine as shown in Table 4:
Table four
Wherein, the 1st row dual port RAM address in table four, the 2nd and the 3rd row are respectively the annotation (current state and initial conditions), the 4th of high-low position in this dual port RAM address and classify storage content as, represent the next state of state machine, particularly:
1) when dual port RAM address is 0000 and 0010, the current state of state machine is A (00), outside initial conditions I
0i
1be respectively 00 and 10.According to Fig. 6, state A is at external condition I
1=0, state remains A(00), therefore the storage data of these two addresses are all 00; In the time that dual port RAM address is 0001 and 0011, current state is A (00), outside initial conditions I
0i
1be respectively 01 and 11, according to Fig. 6, next state is B(01), therefore, the storage data of 0001 and 0011 address are all 01.
2), when dual port RAM address is 0100 ~ 0111, being expressed as current state is B (01), because the next state of state B can only be C(10), therefore the storage data of this sector address are all 10.
3) when dual port RAM address is 1000 ~ 1011, current state is C (10), because the next state of state C is D(11), therefore the storage data of this sector address are all 11.
4) when dual port RAM address is 1100 ~ 1101, current state is D(11), outside initial conditions I
0be 0, according to Fig. 6, next state transition is to A(00), the data value of these two address storages is all 00; When dual port RAM address is 1110 ~ 1111, current state is D(11), outside initial conditions I
0be 1, according to Fig. 6, next state transition is B(01), therefore the data content of 1110 and 1111 address storages is all 01.
The signal output encoder table of Mealy type state machine is as shown in Table 5:
Table five
Wherein, in table five, the 1st classifies dual port RAM address as, the the 2nd and the 3rd row are respectively the annotation (current state and initial conditions) of high-low position in this dual port RAM address, the 4th classifies the control signal (C0, C1, C2) of the needs output under current state and initial conditions as, the 5th classifies storage content as, encodes according to the 4th row, encodes according to C0, C1, C2 order, C0, in a high position, obtains the data of the 5th row.
The signal output encoder table of Moore type state machine is as shown in Table 6:
Table six
Wherein, in table six, the 1st classifies dual port RAM address as, the the 2nd and the 3rd row are respectively the annotation (current state and initial conditions) of high-low position in this dual port RAM address, the 4th classifies the control signal (C0, C1, C2) of the needs output under current state and initial conditions as, as shown in Table 2, the output signal of described second finite state machine only has C0, C1, because the data bit width in table six is 3, lowest order must be filled up, in the present embodiment C2 is filled to 0, as shown in the 4th column data in table six, the 5th row are encoded according to the 4th row again.
Step 3, address calculation receives the first dual port RAM according to read data (current state) and 2 input signal (I of state-transition table output
0, I
1) calculate, generate first of state-transition table for reading the first dual port RAM read address and for read the second dual port RAM signal output encoder table second read address.
Particularly, first the shift unit of address calculation carries out shifting processing to current state: current state (binary data) moves to left 2, then outputs in the totalizer of address calculation; 2 input signal (I
0, I
1) composition binary data also send in totalizer, described I
0, I
1be added with the output data of shift unit, address is read in output first.First read address and current state is input to again in the selector switch of address calculation simultaneously, and owing to there is Mearly type state machine, therefore, selector switch is read address using first and read address as second and export.
Step 4, address calculation is read address signal by first and is input to the first dual port RAM, in the state transition table that described the first dual port RAM is stored at self, carries out addressing, and state machine is read address according to first and is carried out state transitions, the next state of output state machine;
Address calculation is read address signal by second and is inputted the second dual port RAM, in the signal output encoder table that described the second dual port RAM is stored at self, carry out addressing, state machine is read address according to second and is exported conversion, the control signal (C0, C1, C2) of output state machine.
In sum, the present invention can utilize state-transition table and the signal output encoder table of central processing unit to dual port RAM memory state machine to be reconstructed, and realizes the restructural of state machine, not only can realize Moore type state machine, also can realize Mealy type state machine.When use, CPU can modify and call according to actual conditions, simple in structure, can be effectively in programmable logic device (PLD), dynamically reconstruct complex state machine, easily safeguard in design, and easily meet the needs of actual design.
The above, be only preferred embodiment of the present invention, is not intended to limit protection scope of the present invention.
Claims (9)
1. an implementation method for restructural state machine, is characterized in that, described method comprises:
CPU (central processing unit) is reconstructed the state-transition table being stored in described the first dual port RAM by write address line and the write data line of the first Double Port Random Memory RAM;
CPU (central processing unit) is reconstructed the signal output encoder table being stored in described the second dual port RAM by write address line and the write data line of the second dual port RAM.
2. method according to claim 1, is characterized in that, the write address line of described CPU (central processing unit) by the first dual port RAM and write data line to be stored in state-transition table in described the first dual port RAM be reconstructed into:
CPU (central processing unit) is by write address line and the write data line of the first dual port RAM, state transitions condition using state machine is carried out addressing as address, write in the state-transition table being stored in described the first dual port RAM the next state of corresponding state machine as data.
3. method according to claim 1, is characterized in that, the write address line of described CPU (central processing unit) by the second dual port RAM and write data line to be stored in signal output encoder table in described the second dual port RAM be reconstructed into:
CPU (central processing unit), by write address line and the write data line of the second dual port RAM, is carried out addressing using output transform condition as address, writes in the signal output encoder table being stored in described the second dual port RAM using corresponding control signal as data.
4. method according to claim 1, is characterized in that, described method also comprises:
Address calculation calculates first according to the current state of the state machine of the first dual port RAM output and the external input signal that receives and reads address and second and read address;
Described the first dual port RAM is read address according to described first and is read described state-transition table, carries out state transitions, and described the second dual port RAM is read address read signal output encoder table according to described second, output control signal.
5. method according to claim 4, is characterized in that, described address calculation calculates first according to the current state of the state machine of the first dual port RAM output and the external input signal that receives and reads address and second and read address and be:
Address calculation is to the current state the receiving processing of shifting left, current state after displacement and described external input signal are added, obtain first and read address, wherein, described first reads the current state of the high bit representation state machine of address, and described first reads the current initial conditions of low bit representation state machine of address; Or to the processing of shifting left of described external input signal, external input signal after described current state and displacement is added, obtain first and read address, wherein, described first reads the current initial conditions of high bit representation state machine of address, and described first reads the current state of the low bit representation state machine of address;
In the time that the state transitions of state machine is only relevant to the current state of state machine, current state is read to address as second and export, otherwise, read address using described first and read address as second and export.
6. method according to claim 5, is characterized in that, reads address read address while exporting as second when address calculation using described first, and described method also comprises:
The state-transition table of the signal output encoder table of described the second dual port RAM storage and described the first dual port RAM storage is merged, obtain state transitions and signal output encoder table, and be stored in described the first dual port RAM or the second dual port RAM; Wherein, in described state transitions and signal output encoder table, store the next State-output of the high-order or low bit representation state machine of data, the control signal of the low level of described storage data or the output of high bit representation.
7. method according to claim 4, is characterized in that, described the first dual port RAM is read address according to described first and read described state-transition table, carries out state transitions and is:
Described the first dual port RAM is read address according to described first, reads described first and reads storage content corresponding to address, exports as the current state of described state machine; Wherein, the current state before the described first high-order or low bit representation state machine state of reading address shifts, described first reads the low level of address or the current outside initial conditions of high bit representation state machine.
8. method according to claim 4, is characterized in that, described the second dual port RAM is read address read signal output encoder table according to described second, and output control signal is:
Described the second dual port RAM is read address according to described second, reads described second and reads storage content corresponding to address, and described storage content is exported as control signal; Wherein, the current state before the described second high-order or low bit representation state machine state of reading address shifts, described second reads the low level of address or the current initial conditions of high bit representation state machine.
9. according to the method described in claim 1 to 8 any one, it is characterized in that, described CPU (central processing unit) is central processor CPU or single-chip microcomputer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105812365A (en) * | 2016-03-12 | 2016-07-27 | 武汉芯泰科技有限公司 | Programmable and reconfigurable frame processor |
| CN110543440A (en) * | 2019-08-13 | 2019-12-06 | 中国航空工业集团公司西安飞行自动控制研究所 | Software addressing method and device for double-port address bus |
| CN112363974A (en) * | 2020-09-27 | 2021-02-12 | 青岛矽昌通信技术有限公司 | Control method and system of programmable state machine |
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2012
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105812365A (en) * | 2016-03-12 | 2016-07-27 | 武汉芯泰科技有限公司 | Programmable and reconfigurable frame processor |
| CN105812365B (en) * | 2016-03-12 | 2018-09-28 | 武汉芯泰科技有限公司 | A kind of programmable restructural Frame Handler |
| CN110543440A (en) * | 2019-08-13 | 2019-12-06 | 中国航空工业集团公司西安飞行自动控制研究所 | Software addressing method and device for double-port address bus |
| CN110543440B (en) * | 2019-08-13 | 2023-05-23 | 中国航空工业集团公司西安飞行自动控制研究所 | Software addressing method and device for dual-port address bus |
| CN112363974A (en) * | 2020-09-27 | 2021-02-12 | 青岛矽昌通信技术有限公司 | Control method and system of programmable state machine |
| CN112363974B (en) * | 2020-09-27 | 2022-05-31 | 青岛矽昌通信技术有限公司 | Control method and system of programmable state machine |
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