CN110543440B - Software addressing method and device for dual-port address bus - Google Patents
Software addressing method and device for dual-port address bus Download PDFInfo
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- CN110543440B CN110543440B CN201910744503.2A CN201910744503A CN110543440B CN 110543440 B CN110543440 B CN 110543440B CN 201910744503 A CN201910744503 A CN 201910744503A CN 110543440 B CN110543440 B CN 110543440B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a software addressing method of a dual-port address bus, which is applied to a processor communicating with a RAM through a first port of a dual-port RAM, wherein the first port is a reversed end of the dual-port RAM address bus, and a second port of the dual-port RAM is a non-reversed end of the dual-port RAM address bus, and is characterized by comprising the following steps: acquiring an input address input by a processor; acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor; the input address is converted into an address of the first port access dual port according to the first least significant bit and the second least significant bit. The invention aims at the hardware state that one end of two sets of address buses of the dual-port RAM is inverted and the other end is not inverted, and finds the corresponding memory unit address by using a software method.
Description
Technical Field
The invention belongs to the technical field of computer bus communication, and relates to a software addressing method and device for a dual-port address bus.
Background
The dual-port RAM is a memory with two read-write ports, each of which has an independent set of data, address and control buses, which allow two processors to operate the memory to realize data sharing. The address space allocated by the two processor hardware needs to ensure that the respective software can access the same memory unit, otherwise the shared data will have errors. In conventional designs, the consistency of the address codes issued by the two processors ensures that the memory units accessed by the software are correct. However, there may be designs where the hardware (line driver or FPGA logic) at the sending end or the receiving end of the processor is not inverted at the other end, and there is a difference in the software addressing methods of the two ports.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: for the hardware state that one end of two sets of address buses of the dual-port RAM is inverted and the other end is not inverted, a software method is utilized to find the corresponding memory unit address.
The technical scheme of the invention is as follows:
the invention provides a software addressing method of a dual-port address bus, which is applied to a processor communicating with a RAM through a first port of a dual-port RAM, wherein the first port is a reversed end of the dual-port RAM address bus, and a second port of the dual-port RAM is a non-reversed end of the dual-port RAM address bus, and comprises the following steps:
acquiring an input address input by a processor;
acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor;
the input address is converted into an address of the first port access dual port according to the first least significant bit and the second least significant bit.
Further, converting the input address into the address of the first port access dual port according to the first least significant bit and the second least significant bit comprises:
determining the right shift number m according to the second lowest bit, wherein m is an integer;
according to the first lowest bit, determining a left shift number n, wherein n is an integer;
and shifting the input address by m bits to the right according to the binary system, inverting the address of the second port after the right shift, and shifting the inverted address to the left by n bits to obtain the base address of the first port access double port.
Further, the method further comprises:
and calculating the difference between the base address and the first least significant bit to obtain the offset address.
Further, the formula for determining m and n is:
m＝log 2 (Y/8)；n＝log 2 (X/8)；
wherein Y is the second lowest position; x is the first lowest order.
The invention provides a software addressing device of a dual-port address bus, which is applied to a processor communicating with a RAM through a first port of a dual-port RAM, wherein the first port is a reversed end of the dual-port RAM address bus, and a second port of the dual-port RAM is a non-reversed end of the dual-port RAM address bus, and comprises:
the acquisition module is used for acquiring an input address input by the processor; acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor;
and the conversion module is used for converting the input address into the address of the first port access double port according to the first least significant bit and the second least significant bit.
Further, the conversion module includes:
a determining unit, configured to determine, according to the second lowest bit, a right shift number m, where m is an integer; the method is also used for determining the left shift number n according to the first lowest bit, wherein n is an integer;
and the processing unit is used for shifting the input address by m bits according to the binary right, inverting the address of the second port after the right shift, and shifting the inverted address by n bits to the left to obtain the base address of the first port access double port.
Further, the device further comprises:
and the calculating module is used for calculating the difference between the base address and the first least significant bit to obtain an offset address.
Further, the formula for determining m and n is:
m＝log 2 (Y/8)；n＝log 2 (X/8)；
wherein Y is the second lowest position; x is the first lowest order.
The present invention provides a computer-readable storage medium storing a program executable by a computer to be executed by a processor to implement the method of any one of the present invention.
The invention has the beneficial effects that:
1. the operation of the double ports with the address line inversion design is realized by a software method under the condition of not changing hardware.
2. The method has wide applicability to address units with different bit widths.
Drawings
FIG. 1 is a schematic diagram of a hardware interface of a software addressing method of a dual port address bus according to the present invention.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings.
As shown in FIG. 1, the non-inverting end of the contracted dual-port RAM address bus is the A port (the second port), and the inverting end of the address bus is the B port (the first port). Firstly determining the memory address allocated by the A port, and then determining the data bit width X represented by the lowest bit of the output address bus of the B port processor and the data bit width Y represented by the lowest bit of the input dual-port RAM address bus of the B port.
The base address and offset address of the B-port access dual port are obtained according to the following operation:
first, the A mouthAddress right shift log 2 (Y/8) bits, then inverting by bit, then left shifting log 2 The (X/8) bit is obtained by accessing the base address by the B port, and other addresses in the memory space are obtained according to the base address-X/8.
Claims (5)
1. The software addressing method of the dual-port address bus is applied to a processor which communicates with a RAM through a first port of a dual-port RAM, wherein the first port is the opposite end of the dual-port RAM address bus, and a second port of the dual-port RAM is the non-opposite end of the dual-port RAM address bus, and is characterized by comprising the following steps:
acquiring an input address input by a processor;
acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor;
according to the first lowest bit and the second lowest bit, converting an input address into a first port access double-port address;
converting the input address into the address of the first port access dual port according to the first least significant bit and the second least significant bit comprises:
determining the right shift number m according to the second lowest bit, wherein m is an integer;
according to the first lowest bit, determining a left shift number n, wherein n is an integer;
shifting the input address by m bits to the right according to the binary system, inverting the address of the second port after the right shift, and shifting the inverted address to the left by n bits to obtain a base address of the first port access double port;
the formula for determining m and n is:
m＝log 2 (Y/8)；n＝log 2 (X/8)；
wherein Y is the second lowest position; x is the first lowest order.
2. The method according to claim 1, wherein the method further comprises:
and calculating the difference between the base address and the first least significant bit to obtain the offset address.
3. The utility model provides a software addressing device of two port address bus, is applied to the treater that communicates with the RAM through the first mouth of two port RAM, and first mouth is two port RAM address bus and reverses one end, and the second mouth of two port RAM is two port RAM address bus and does not reverse one end, its characterized in that includes:
the acquisition module is used for acquiring an input address input by the processor; acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor;
the conversion module is used for converting an input address into a first port access double-port address according to the first lowest bit and the second lowest bit; the conversion module comprises:
a determining unit, configured to determine, according to the second lowest bit, a right shift number m, where m is an integer; the method is also used for determining the left shift number n according to the first lowest bit, wherein n is an integer;
the processing unit is used for shifting the input address by m bits according to binary right, inverting the address of the second port after right shifting, and shifting the inverted address by n bits to the left to obtain the base address of the first port access double port;
the formula for determining m and n is:
m＝log 2 (Y/8)；n＝log 2 (X/8)；
wherein Y is the second lowest position; x is the first lowest order.
4. A device according to claim 3, characterized in that the device further comprises:
and the calculating module is used for calculating the difference between the base address and the first least significant bit to obtain an offset address.
5. A computer-readable storage medium storing a program executable by a computer, wherein the program is executed by a processor to implement the method of claim 1 or 2.
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| CN201910744503.2A CN110543440B (en) | 2019-08-13 | 2019-08-13 | Software addressing method and device for dual-port address bus |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5926648A (en) * | 1996-08-22 | 1999-07-20 | Zilog, Inc. | I/O port and RAM memory addressing technique |
| CN101996147A (en) * | 2009-08-25 | 2011-03-30 | 北京广利核系统工程有限公司 | Method for realizing dual-port RAM (Random-Access memory) mutual exclusion access |
| CN103853694A (en) * | 2012-12-04 | 2014-06-11 | 天津中兴软件有限责任公司 | Implementation method for reconfigurable state machine |
| CN205680092U (en) * | 2016-05-19 | 2016-11-09 | 金陵科技学院 | Dual port RAM shares interface circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4015867B2 (en) * | 2002-03-27 | 2007-11-28 | 松下電器産業株式会社 | Address signal output device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5926648A (en) * | 1996-08-22 | 1999-07-20 | Zilog, Inc. | I/O port and RAM memory addressing technique |
| CN101996147A (en) * | 2009-08-25 | 2011-03-30 | 北京广利核系统工程有限公司 | Method for realizing dual-port RAM (Random-Access memory) mutual exclusion access |
| CN103853694A (en) * | 2012-12-04 | 2014-06-11 | 天津中兴软件有限责任公司 | Implementation method for reconfigurable state machine |
| CN205680092U (en) * | 2016-05-19 | 2016-11-09 | 金陵科技学院 | Dual port RAM shares interface circuit |
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