JP6498557B2 - Programmable controller - Google Patents

Description

  The present invention relates to a programmable controller that controls operations of equipment and a mechanical system by a sequence program, and particularly has a feature in an IO access method between a CPU module and an IO module.

A programmable controller (hereinafter referred to as “PLC”) is a control device that cyclically executes a ladder program created by a user, and is used to control various machine facilities and plant facilities installed in factories and the like. Widely used as a general-purpose control device.
The PLC captures the operating status of mechanical equipment from devices such as sensors and switches as digital signals as ON / OFF information via the input module, or captures pressure information, temperature information, etc. of plant equipment as analog signals. Calculation is performed with the sequence program created by. Then, the calculation result is transmitted as a digital signal or an analog signal to the power source of the machine facility, the valve of the plant facility, or the like via the output module, thereby realizing advanced control of the entire facility. Taking input data from the input module and outputting the operation result to the output module is called “IO refresh”. One means for performing control by PLC at high speed is to perform this IO refresh at high speed.

  As a technique for speeding up the control by the PLC, for example, in Patent Document 1, “the update cycle of each module can be set in the input / output module allocation information, and the update cycle is set at the time of executing the refresh process for each scan. By refreshing only modules that are equal to or longer than the update cycle, the number of bus accesses between the CPU module and the I / O module is reduced, and the scan time is increased. " Has been.

  Although not in the technical field of PLC, in order to increase the access performance (read / write) of a memory device, the burst mode in which a plurality of data is transferred continuously by one address designation is a data transfer mode. This is a known technique (for example, Patent Document 2).

Japanese Patent Laying-Open No. 2015-60377 JP 2002-251319 A

  The module type PLC can mount various types of IO modules. For example, a module that inputs or outputs digital signals of 16 points (bits) / 32 points / 64 points, a module that inputs or outputs analog signals of 8 channels (1 channel is 16 bits), etc. A communication module or the like for sharing data between PLCs is used.

  The amount of data handled by the communication module handles a large amount of data such as 8k words or 32k words. The CPU module cyclically performs IO refresh of data between these IO modules and communication modules and sequence program calculation. For this reason, when the amount of data increases, the calculation cycle of the user program is delayed accordingly.

  Therefore, an object of the present invention is to provide a technique capable of accessing data in continuous areas (address spaces) at high speed.

  The PLC according to the present invention includes a CPU module, one or more IO modules, and an external bus connecting both modules. The CPU module designates an arbitrary address in the address space of each IO module, and the IO module designates The address is incremented or decremented from the given arbitrary address, and IO processing is executed on a continuous address space in the IO module.

  According to the present invention, data transfer can be performed at high speed.

FIG. 1 is a configuration diagram of a programmable controller according to an embodiment of the present invention. FIG. 2 is a configuration diagram of an internal block of the BUS controller included in the communication module. FIG. 3 is a time chart at the time of write access to a normal IO module. FIG. 4 is a time chart at the time of read access to a normal IO module. FIG. 5 is a time chart of high-speed continuous access when writing to the communication module. FIG. 6 is a time chart of high-speed continuous access at the time of reading with respect to the communication module. FIG. 7 is a flowchart showing the operation of the programmable controller (PLC).

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a PLC according to an embodiment of the present invention.
The CPU module 1 installed in the CPU slot of the PLC includes an MPU 11 for calculating a sequence program, a communication port 12 for communicating with a peripheral device such as a personal computer, a ROM 13 for storing a sequence program and a system program, a sequence program A BUS controller having a RAM 14 for storing data used for calculation, a DMAC 15 for transferring data between the RAM 14 and an IO module connected to the external bus 5, an address output unit serving as an interface with the external bus 3, and a data input / output unit M16 (M represents “master”). Further, the CPU module 1 is provided with a counter for counting the number of continuous accesses for high-speed continuous access to an IO module described later. This counter can be configured in hardware or software. Therefore, it is not shown in the CPU module 1 of FIG.

  The CPU module 1 needs to know in advance which IO module is connected to the IO slot 0, IO slot 1,... IO slot n. Normally, on the IO module side, information such as input / output type and data size can be recognized from the CPU module 1 as status information. By providing information indicating whether high-speed continuous access is supported or not in this status information, it is possible to determine in which IO slot an IO module capable of high-speed continuous access is mounted from the CPU module 1.

  The external IO module includes a communication module 2 in addition to an IO module (input module or output module) for digital signals and analog signals. The communication module 2 includes, for example, a 2-port RAM 21 inside the module, and transfers data between the CPU module 1 and an external communication device connected to the communication port of the communication module 2 via the 2-port RAM 21. At the time of access from the CPU module 1 side at that time, the communication module 2 accesses the internal 2-port RAM 21 by an address acquired via the external bus 3 or is continuously sent from the CPU module to the address. The address incremented or decremented by the number of accesses is sent to access the internal 2-port RAM 21. In order to enable this access, the communication module 2 comprises a BUS controller S22 (S stands for “slave”). The address is also called an address.

The external bus 3 connects the CPU module 1 and various IO modules connected to the IO slots 0 to n to exchange addresses, data, and control information. In the present embodiment, a multiplexed bus that is shared by addresses and data is used as the external bus 3. In FIG. 1, signal lines for a mode signal (mode_n) and a strobe signal (strobe_n), which will be described later, are separated from signal lines constituting the external bus 3.
The present invention does not limit the external bus to this multiplex bus, but may be a separate bus form. However, the multiplexed bus can reduce the number of necessary signal lines and the number of pins compared to a separate bus.

  FIG. 2 is a configuration diagram of an internal block of the BUS controller S22 included in the communication module 2. The BUS controller S22 that is an interface with the external bus 3 includes a flip-flop (FF) 31 that stores an address, an increase / decrease counter 32 that increments or decrements an address output from the flip-flop (FF), and a selector 33 for selecting an address. Composed. Since the external bus 3 is a multiplex bus, the input data from the external bus 3 is sent as it is to the 2-port RAM, and the address is sent to the selector 33. In FIG. 2, signal lines for the mode signal (mode_n) and the strobe signal (strobe_n) are omitted.

  The flip-flop (FF) 31 is incremented or decremented by the increment / decrement counter 32 as the input, the address input from the CPU module 1 via the external bus 3 or the address stored in the flip-flop (FF) 31 itself. An address is selected by the selector 33. That is, the flip-flop (FF) 31 selects and stores / outputs the address from the external bus 3 during normal access, and sequentially stores / outputs the incremented or decremented address during high-speed continuous access. Will be. For selection by the selector 33, a mode signal (mode_n) described later is used. Further, a mode signal (mode_n) and a strobe signal (strobe_n) described later are used to determine whether the increase / decrease counter 32 is incremented or decremented.

  Between the CPU module 1 and the communication module 2, a much larger amount of data is handled than the data amount handled by the CPU module 1 and the normal IO module. Therefore, the difference in data access between the two will be described using a time chart.

First, FIG. 3 and FIG. 4 are time charts when the CPU module 1 performs a refresh process for a normal IO module. FIG. 3 shows a write time and FIG. 4 shows a read time.
The external bus 3 is a multiplexed bus shared by addresses and data, and signals to be exchanged are selection signals (cs_n), address strobe signals (as_n), data strobe signals (wr_n / rd_n) and 16 bits for each slot. Address / data signal (ad [15: 0]).

  For example, in the refresh process for a 32-point (bit) output module, the write access shown in FIG. 3 is performed twice. Further, the refresh processing for the 8-channel analog input module is performed 8 times for the read access shown in FIG. 4 because one channel is 16 bits.

Next, FIG. 5 and FIG. 6 are time charts when high-speed continuous access is performed between the CPU module 1 and the communication module 2. FIG. 5 shows a write time and FIG. 6 shows a read time.
The CPU module 1 designates an address (ADR) of an address space to be accessed (designation of an arbitrary address) and a mode signal (mode_n) for identifying normal access or high-speed continuous access to the communication module 2. Output at the same timing as address output. At the rising edge of the address strobe signal (as_n), the communication module 2 side determines whether the CPU module 1 is accessing by normal access or high-speed continuous access according to the level of the mode signal (mode_n) (FIGS. 5 and 5). 6, when the mode signal (mode_n) is at the L level, the high-speed continuous access is performed.

  In the data cycle of the high-speed continuous access, the address in the communication module is updated according to the level change of the strobe signal (strobe_n). That is, the increment or decrement is selected according to the level of the mode signal (mode_n) at the start of level change of the strobe signal (strobe_n) (at the time of rising from the L level to the H level) (in FIGS. 5 and 6, the strobe signal is changed). At the start of the H level change from the (strobe_n) L level, the mode signal (mode_n) is incremented if it is L level, and decremented if it is H level).

  Then, the CPU module 1 designates the continuous access number (continuous address space) related to the high-speed continuous access. The CPU module 1 transmits a strobe signal (strobe_n) pulsed by the number of continuous accesses corresponding to the continuous address space to the communication module 2 using a counter provided therein. The increase / decrease counter 32 of the BUS controller S22 included in the communication module 2 receives this pulsed strobe signal and increments or decrements this specified number of consecutive accesses from an arbitrary address.

  Further, even when the CPU module 1 is a conventional CPU module that does not support high-speed continuous access and is combined with an IO module that supports high-speed continuous access, control signals (cs_n, as_n) required for normal access are used. , Wr_n and rd_n) are compatible, so normal access is possible.

  In this embodiment, the communication module 2 is shown as a module for high-speed continuous access, but this is not limited to the communication module. Furthermore, although the communication module 2 includes a 2-port RAM therein, in reality, an arbitration circuit (arbiter) may be added to the 1-port RAM instead of the 2-port RAM.

  FIG. 7 is a flowchart showing the operation of the PLC. The PLC normally performs a series of processing flows of input refresh related to data input, sequence calculation based on input data, and output refresh related to data output accompanying the calculation result until a stop operation such as power-off occurs. It will be executed cyclically. The time required for a series of cyclic processing by executing IO refresh (input refresh + output refresh) and sequence calculation is called “scan time”. Then, if the execution time of the sequence calculation is constant, the scan time depends on the time required for IO refresh.

  Next, according to the above flowchart, how much the cyclic calculation performance, that is, the scan time differs depending on the presence or absence of high-speed continuous access will be described. Here, as an example of the configuration of the PLC, as shown in FIG. 1, a communication module that handles 8,192 words of data in IO slot 0, an input module that handles 1 word of data in IO slot 1, and IO slot 2 Assume that an output module that handles 1-word data is mounted. Further, assuming that the unit time of IO access is “1 μsec”, the scan time required for a series of cyclic processes shown in the flowchart of FIG. 7 is calculated.

  Assume that the access to the normal IO module shown in FIGS. 3 and 4 is performed on the communication module. Since the communication module handles data of 8,192 words at the maximum, if input refresh and output refresh are performed with normal IO access, the IO refresh requires a maximum of “8,194 μsec” (about 8 msec). It becomes. Further, the time required for the sequence calculation depends on the capacity of the sequence program created by the user, and is generally “1 msec (= 1,000 μsec)”. Then, the maximum scan time is “9,194 μsec”, which is about 9 msec.

  On the other hand, when the IO refresh for the communication module is performed by the high-speed continuous access shown in FIGS. 5 and 6, only the address is updated inside the communication module. Then, the address can be updated at a higher speed than the sequential acquisition of addresses from the CPU module 1. Since the address update time inside the communication module is normally about 120 nsec, if it is “0.1 μsec”, the time required for IO refresh of the communication module can be regarded as about “819 μsec” at the maximum. In addition to this, the normal IO access for the input module and the output module (2 μsec) is added, and the maximum IO refresh is “821 μsec”. Furthermore, the maximum scan time including the sequence calculation time (1 msec) is “1,821 μsec”. That is, it can be seen that the performance is improved about 5 times compared to the scan time in the case of the above-mentioned normal IO access (in this case, even when the address update time is calculated as “0.12 μsec” The maximum scan time is “983 μsec”, and the scan time including the normal IO access and the sequence calculation time is “1,985 μsec” at maximum, which is a 4.6 times improvement in performance).

At the time of data communication, the address is designated once, and after performing data communication to the designated address, sequential data communication of read or write can be performed to the address after the designated address or before, When performing this sequential data communication, the address need not be specified.
As a result, the time required for address designation communication can be reduced.
That is, when one communication module starts communication, after specifying the address for data communication before performing data communication, one and the other communication modules are set to sequentially perform data communication. Since this information is included, data communication is repeated.
For example, communication specifying the designated address n is performed, and after data communication of the designated address n, communication specifying the address is performed for the addresses n + 1, n + 2,... Or n-1, n-2,. Since it becomes unnecessary, the overall data communication speed can be improved. In addition, although described as n + 1, n + 2,... For convenience, the address after the designated address or the previous address is appropriately changed depending on the number of buses for data communication, etc. n + m and n + 2m.

As described above, in this embodiment, in the IO refresh processing of the CPU module, it is possible to greatly speed up the processing time by using the above-described high-speed continuous access for the access to the continuous area (address space). It becomes.
In other words, the bus access from the CPU module to the continuous address space can be read or written by toggling the data strobe signal by the access size after the designation output of an arbitrary address once, and data can be transferred at high speed.
In addition, by performing data transfer at high speed, the calculation cycle in the CPU module becomes faster, and control for external devices can be executed at high speed.

  In addition, this invention is not limited to said Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of the embodiment.

1 ... CPU module, 2 ... communication module, 3 ... external bus,
11 ... MPU, 12 ... communication port, 13 ... ROM, 14 ... RAM, 15 ... DMAC,
16 ... BUS controller M, 21 ... 2-port RAM, 22 ... BUS controller S,
31 ... flip-flop (FF), 32 ... increase / decrease counter, 33 ... selector

Claims (4)

A CPU module, one or more IO modules, and an external bus connecting the two modules;
The CPU module specifies the number of consecutive accesses corresponding to the address space contiguous in any address or the IO module of the IO module individual address space,
The IO module increments or decrements the address from the specified arbitrary address by the number of consecutive accesses , and executes IO processing on a continuous address space in the IO module ,
The external bus has a first signal line for communicating a mode signal designating execution of IO processing for the continuous address space and increment or decrement of the address, and update timing for incrementing or decrementing the address. A programmable controller , wherein a second signal line for communicating a prescribed strobe signal is attached . The programmable controller according to claim 1,
The programmable controller , wherein the update timing for incrementing or decrementing the address is when the level of the strobe signal changes . The programmable controller according to claim 1 or 2 ,
The programmable controller , wherein the CPU module outputs a pulsed signal corresponding to the number of continuous accesses as the strobe signal . The programmable controller according to any one of claims 1 to 3 ,
The programmable controller , wherein the external bus is a multiplexed bus shared by the address and data .

Images