JP3862031B2 - Microprocessor - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a microprocessor and, for example, to a technique that is particularly effective when used for its external bus interface.
[0002]
[Prior art]
A microprocessor (microcontroller) having an external bus capable of directly connecting various semiconductor memories such as a synchronous DRAM (dynamic random access memory) is, for example, “Nikkei Electronics” dated February 14, 1994 issued by Nikkei McGraw-Hill. 79-91.
[0003]
On the other hand, there are PC cards such as memory cards and I / O cards, and interface conditions for coupling PC cards to microprocessors etc. are standardized by Japan Electronics Industry Promotion Association (JEIDA) and PCMCIA (Personal Computer Memory Card International Association). ing. For the PC card interface, Guidelines Ver. 4.1 “6. 68-pin IC memory card interface and I / O card interface defined in “Electrical / Interface Specification” are included. In order to cope with such a PC card interface, a dedicated IC (integrated circuit) chip such as 82365SL is prepared.
[0004]
[Problems to be solved by the invention]
In a conventional microprocessor or the like, a bus for coupling a PC card is provided separately from a bus for coupling a semiconductor memory or the like, and the PC card is coupled to the bus via the dedicated IC chip. Interface control is performed by these dedicated IC chips. For this reason, when a PC card interface is to be incorporated into a personal computer, a portable information terminal, or the like, the bus configuration becomes complicated, the design man-hour increases, and the number of external parts of the microprocessor increases. As a result, the development period of personal computers, portable information terminals, etc. increases, and the cost reduction is impeded.
[0005]
An object of the present invention is to provide a microprocessor with improved usability. Another object of the present invention is to reduce the design man-hour of a personal computer having a built-in microprocessor and a PC card interface, to reduce the number of external parts, and to reduce the cost. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0006]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, various semiconductor memories such as ROM, burst ROM, SRAM, PSRAM, DRAM, and synchronous DRAM, a memory card, and an I / O card are coupled to an external bus to a microprocessor built in a personal computer and a portable information terminal. A bus state controller capable of controlling the PC card interface in parallel is provided. The bus state controller BSC is provided with a control register (PCR) for controlling the setup time of the PC card activation signals (-OE, -WE) when the synchronous DRAM is connected.
[0007]
In addition, the address space of the external bus is divided into a predetermined number of areas, and various semiconductor memories or PC cards are fixedly assigned to the respective areas, and as physical addresses and memories when the I / O card functions as an input / output device. A memory management unit is provided for independently assigning a physical address for functioning and converting a logical address in the microprocessor to a physical address in an external bus.
[0008]
[Action]
According to the above-described means, the above object is achieved for the following reason. Coupling various semiconductor memories and PC cards such as memory cards and I / O cards directly and simultaneously to the external bus of the microprocessor without being restricted by the physical address and reducing external parts for interface control can do. As a result, it is possible to improve the usability of the microprocessor, reduce the design man-hours such as a personal computer having a built-in microprocessor and a PC card interface, reduce the number of external parts, and reduce the cost. .
[0009]
The bus state controller BSC is provided with a control register (PCR) for controlling the setup time of the PC card activation signals (-OE, -WE) when the synchronous DRAM is connected. It is possible to control the fall of the clock signal CKIO of the output enable signal -OE or write enable signal -WE or the setup time for the address signal. As a result, even if the PC card and the synchronous DRAM are simultaneously coupled to the microprocessor MPU of the present invention, the microprocessor MPU of the present invention can access the PC card and the synchronous DRAM without any inconvenience.
[0010]
【Example】
FIG. 1 shows a system configuration diagram of an embodiment of a personal computer including a microprocessor MPU according to the present invention. In the figure, a personal computer uses a motherboard MBD on which a microprocessor MPU is mounted as its basic component. Although not particularly limited to the motherboard MBD, two kinds of PC cards, that is, a memory card MEMC and an I / O card IOC are respectively coupled via PC card slots PCSL1 and PCSL2, and a man-machine interface is coupled via connectors LCDCON and KBDCON. A liquid crystal display LCD and a keyboard KBD are respectively coupled.
[0011]
The memory card MEMC is composed of SRAM (static RAM), EPROM (electrically writable read-only memory), EEPROM (electrically erasable / writable read-only memory), flash EEPROM, or the like. , A data storage card. On the other hand, the I / O card IOC is a modem for facsimile or data transfer, a control circuit used for a LAN, a control circuit used for a global positioning system (GPS), or a small computer system interface controller.
[0012]
The microprocessor MPU of the motherboard MBD is not particularly limited, but six types of semiconductor memory, that is, ROM, burst ROM (BROM), SRAM, PSRAM (pseudo SRAM), DRAM (dynamic RAM) via the external bus E-BUS And a synchronous DRAM (SDRAM). PC card buffers BUF1 and BUF2, a display controller LCDC, and a keyboard controller KBDC are further coupled to the external bus E-BUS. Of these, the PC card buffers BUF1 and BUF2 are connected to the PC card slots PCSL1 and PCSL2, that is, the memory card MEMC and the I / O card IOC, respectively. A display LCD and a keyboard KBD are respectively coupled. A predetermined operating power is supplied from the power supply unit POWU to various semiconductor memories, PC card buffers, and controllers mounted on the motherboard MBD.
[0013]
The microprocessor MPU performs a step operation according to a program read from the ROM or burst ROM, executes a predetermined logical operation process, and controls and supervises each part of the personal computer. The PC card buffers BUF1 and BUF2 perform interface matching with the memory card MEMC or the I / O card IOC mounted in the PC card slot PCSL1 or PCSL2, and the display controller LCDC and the keyboard controller KBDC are connected to the connector LCDCON or Control the liquid crystal display LCD or keyboard KBD coupled via KBDCON.
[0014]
In this embodiment, as will be described later, the microprocessor MPU includes various semiconductor memories such as ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous DRAM coupled to an external bus E-BUS, memory cards MEMC, and I / O. A bus state controller BSC capable of controlling an interface with a PC card such as an O card IOC in parallel is provided. The address space of the external bus E-BUS is divided into a predetermined number of areas, and a semiconductor memory or a PC card is fixedly allocated to these areas, and the I / O card functions as an I / O card. The physical address is assigned independently of the physical address when functioning as a memory card.
[0015]
Therefore, the microprocessor MPU further includes a memory management unit MMU that converts a logical address inside the microprocessor MPU into a physical address on the external bus. As a result, it is possible to directly and simultaneously connect various semiconductor memories and PC cards, that is, the memory card MEMC and the I / O card IOC, without being restricted by the physical address and reducing external components for interface control. This can be coupled to the E-BUS, thereby improving the usability of the microprocessor MPU, and reducing the design man-hour of the personal computer and the number of external parts, thereby reducing the cost.
[0016]
FIG. 2 shows an external configuration diagram of three embodiments of the personal computer of FIG. First, in FIG. 2A, the personal computer is a so-called notebook type, and has a built-in file Ffile consisting of a memory card MEMC or an I / O card IOC mounted in a PC card slot MSLOT (PCSL1, PCSL2). As an input / output device, a keyboard KB (KBD) and a liquid crystal display DP (LCD) are provided. Of these, the liquid crystal display can be folded inward, thereby making it convenient for carrying.
[0017]
2B, the personal computer is a so-called desktop type, and includes a floppy disk drive FDD and a file Ffile made up of a memory card MEMC or an I / O card IOC installed in a PC card slot (not shown). Also, a keyboard KB and a liquid crystal display DP are provided as input / output devices, and a predetermined floppy disk FD is inserted into the floppy disk drive FDD. Thereby, the personal computer has both a storage area as software by the floppy disk FD and a storage area as hardware by the file Ffile.
[0018]
In FIG. 2C, the personal computer is a so-called pen-portable type, and includes two PC card slots into which a file card FfileCARD composed of a memory card MEMC or an I / O card IOC can be mounted. In addition, a liquid crystal display DP with pressure sensitive sheet and an input pen PEN are provided as input / output devices, enabling input by handwritten characters.
[0019]
In these embodiments, the microprocessor MPU constituting the motherboard MBD of the personal computer can directly and simultaneously couple various semiconductor memories and a PC card comprising the memory card MEMC and the I / O card IOC as described above. Has an interface. As a result, the configuration of the motherboard MBD and personal computer is simplified, and it is possible to adopt a form that is convenient for portability due to its miniaturization, weight reduction, and thinning, and high-capacity information can be obtained at high speed by using a burst function to be described later. Therefore, the processing capability as a personal computer is enhanced.
[0020]
FIG. 3 shows a block diagram of an embodiment of a microprocessor MPU included in the personal computer of FIG. 1, and FIG. 4 shows an embodiment of a layout of the microprocessor MPU on a semiconductor substrate (semiconductor chip). It is shown. That is, the microprocessor MPU is formed on a semiconductor substrate such as single crystal silicon by a known semiconductor manufacturing method.
[0021]
In FIG. 3, the microprocessor MPU has a stored program type central processing unit CPU including an arithmetic unit ALU as its basic component. The central processing unit CPU is coupled to a multiplier MULT, a memory management unit MMU, and a cache memory CACHE via a system bus S-BUS (first internal bus), and an address translation buffer TLB is coupled to the memory management unit MMU. Is done. The memory management unit MMU and the cache memory CACHE are further coupled to a cache bus C-BUS (second internal bus) on the other side, and a bus state controller BSC is coupled to the cache bus C-BUS.
[0022]
The bus state controller BSC is coupled to the peripheral bus P-BUS on the other side and to the external bus E-BUS via a bus interface unit and a bus connector (not shown). Among these, the peripheral bus P-BUS (third internal bus) includes a refresh controller REFC, a direct memory access controller DMAC, a timer circuit TIM, a serial communication interface SCI, a digital / analog conversion circuit D / A, and an analog / digital conversion circuit. Peripheral device controllers such as A / D are coupled, and the external bus E-BUS is coupled with the PC card buffers BUF1 and BUF2, the display controller LCDC, and the keyboard controller KBDC for coupling the various semiconductor memories and PC cards. The
[0023]
The bus state controller BSC, refresh controller REFC, direct memory access controller DMAC, timer circuit TIM, serial communication interface SCI, digital / analog conversion circuit D / A and analog / digital conversion circuit A / D are further coupled to an interrupt controller INTC. The interrupt controller is coupled to the central processing unit CPU via an interrupt request signal IRQ.
[0024]
Although not shown in the figure, each of the system bus S-BUS, the cache bus C-BUS and the peripheral bus P-BUS includes an internal address bus for transmitting an address signal, an internal data bus for transmitting data, and , Each including an internal control bus for transmitting control signals. On the other hand, the external bus E-BUS is considered to include an external address bus for transmitting address signals, an external data bus for transmitting data, and an external control bus for transmitting control signals.
[0025]
The central processing unit CPU operates synchronously in accordance with a predetermined system clock signal supplied from the clock pulse generation circuit CPG, executes predetermined arithmetic processing in accordance with a control program read from the cache memory CACHE, and controls each part of the microprocessor MPU. Control and control. At this time, the arithmetic unit ALU executes a predetermined arithmetic logic operation, and the multiplier MULT executes a multiplication process or a product-sum process effective for digital signal processing or the like.
[0026]
The memory management unit MMU converts a logical address output from the inside of the microprocessor MPU, that is, from the central processing unit CPU or the like at the time of memory access into a physical address with reference to an address translation look-aside buffer TLB. The signal is transmitted to the outside of the microprocessor MPU, that is, the external bus E-BUS via the bus state controller BSC. The cache memory CACHE is composed of a semiconductor memory that can be accessed at high speed, and reads and holds control programs or data stored in an external ROM or burst ROM in predetermined block units, contributing to the high-speed operation of the central processing unit CPU. To do.
[0027]
On the other hand, the bus state controller BSC manages the bus access of each peripheral device controller coupled to the peripheral bus P-BUS, controls and supervises the operation thereof, and various semiconductor memories coupled to the external bus E-BUS. Control and control the operation of PC cards and various input / output controllers.
[0028]
In this embodiment, the physical address space of the external bus E-BUS is not particularly limited, but is divided into eight areas, of which seven areas are fixedly assigned to various semiconductor memories and PC cards with a predetermined combination. It is done. In addition, the bus state controller BSC has a function of controlling and managing the timing of control signals for various semiconductor memories and PC cards assigned to each area of the external bus E-BUS under predetermined conditions in parallel. Various control registers are provided for selectively designating these timing conditions.
[0029]
As a result, the external bus E-BUS, as described above, includes various semiconductor memories including ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous DRAM, and a PC including a memory card MEMC and an I / O card IOC. The card can be connected directly and simultaneously. The signal configuration of the external bus E-BUS and the specific configuration of the bus state controller BSC will be described later in detail.
[0030]
Next, the refresh controller REFC, which is one of the peripheral device controllers, controls the refresh operation of the DRAM and SDRAM coupled to the external bus E-BUS, and the direct memory access controller DMAC is coupled to, for example, the external bus E-BUS. Supports high-speed data transfer between the read ROM or burst ROM and the cache memory CACHE or the like.
[0031]
The timer circuit TIM supports time management necessary for the central processing unit CPU, and the serial communication interface SCI supports serial data transfer with an external communication control device or the like. On the other hand, the analog / digital conversion circuit A / D converts an analog signal input from an external sensor or the like into a predetermined digital signal, and the digital / analog conversion circuit D / A is output from the central processing unit CPU. The digital signal is converted into a predetermined analog signal and output externally. The interrupt controller INTC selectively accepts an interrupt request from the bus state controller BSC or each peripheral device controller with a predetermined priority and transmits it as an interrupt request signal IRQ to the central processing unit CPU.
[0032]
In this embodiment, each part constituting the microprocessor MPU is arranged on one semiconductor substrate with predetermined layout conditions as illustrated in FIG. Also, each part of the microprocessor MPU is so-called modularized, selectively formed based on user specifications, and selectively enabled.
[0033]
In FIG. 4, the bus controller corresponds to the bus state controller BSC of FIG. 3, and Timer corresponds to the timer circuit TIM. The system clock formed by the clock pulse generation circuit CPG is distributed and supplied to each part of the microprocessor MPU via a predetermined clock driver Driver.
[0034]
FIG. 5 shows an address map of an embodiment for explaining allocation of physical addresses in the external bus E-BUS of the microprocessor MPU of FIG. 3, and FIG. 6 shows physical addresses in the areas 5 and 6. A partial address map of one embodiment for illustrating address assignment is shown. First, in FIG. 5, the physical address space of the external bus E-BUS of the microprocessor MPU of this embodiment is not particularly limited, but is divided into eight areas 0 to 7, and seven of these areas 0 to 6 are included. It can be used by various semiconductor memories and PC cards coupled to the external bus E-BUS.
[0035]
Of these, area 0 is selectively allocated to normal memory including SRAM and ROM or burst ROM, and area 1 and area 4 are selectively allocated to normal memory. Area 2 is selectively assigned to normal memory, SDRAM or DRAM, and area 3 is selectively assigned to normal memory, SDRAM, DRAM or PSRAM. On the other hand, area 5 is selectively assigned to normal memory or burst ROM or memory card MEMC, and area 6 is selectively assigned to normal memory or burst ROM or memory card MEMC or I / O card IOC. In this specification, the normal memory means an address non-multiplex type memory that is accessed by simultaneously supplying row and column addresses, such as SRAM and ROM, and row and column like DRAM and SDRAM. It is distinguished from an address multiplex type memory in which addresses are supplied in a time division manner and accessed.
[0036]
The area 7 is assigned to an internal device address of the microprocessor MPU, for example, an internal register address of the CPU or a register address in the peripheral device controller, and cannot be used by an external device. Further, which semiconductor memory or PC card is coupled to area 0 to area 6 is selectively designated by a bus control register BCR1 of a bus state controller BSC described later.
[0037]
In this embodiment, the internal address buses of the system bus S-BUS, the cache bus C-BUS and the peripheral bus P-BUS of the microprocessor MPU include signal lines capable of transferring 32-bit address signals A0 to A31. The logical address in the processor MPU is composed of a so-called 4 GB (gigabyte) address space that is alternatively specified by these address signals A0 to A31. On the other hand, the physical address external to the microprocessor MPU, that is, the external bus E-BUS, is alternatively specified by 29-bit address signals A0 to A28 excluding the upper 3 bits, but the upper 3 bits of the address signals A0 to A31. That is, the address signals A26 to A28 are provided for generating chip select signals -CS0 to -CS6 for alternatively designating the areas 0 to 6, and the lower 26 bits of the address signals A0 to A25 are provided. , Provided to alternatively specify addresses within each area. That is, the external address bus in the external bus E-BUS includes signal lines that can transfer the address signals A0 to A25.
[0038]
As a result, physical addresses H'00000000 to H'03FFFFFF are assigned to area 0 in hexadecimal notation, and physical addresses H'04000000 to 07FFFFFF are assigned to area 1. Areas 2 to 4 are assigned physical addresses of H'08000000 to H'0BFFFFFF, H'0C000000 to H'0FFFFFFF, and H'10000000 to H'13FFFFFF, respectively. Physical addresses of '14000000 to H'17FFFFFF and H'18000000 to H'1BFFFFFF are assigned, respectively. As a result, each area has a so-called 64 MB (megabyte) physical address space. Note that the physical address obtained by adding H'20000000 × n (n = 1 to 6) to the physical addresses of area 0 to area 6 is the shadow space of each area, and this multiplier n is the upper 3 bits of the logical address. That is, it is selectively specified by the address signals A29 to A31.
[0039]
The physical addresses of area 5 and area 6 assigned to the memory card MEMC and the I / O card IOC are further divided into two as shown in FIG. Among these, in area 5, a lower area consisting of addresses H'14000000 to H'15FFFFFF is allocated as a common memory or attribute memory area for the memory card MEMC, and an upper area consisting of addresses H'16000000 to H'17FFFFFF The area is a use-prohibited area. In area 6, a lower area composed of addresses H'18000000 to H'19FFFFFF is assigned as a common memory or attribute memory area when the memory card MEMC or the I / O card IOC functions as a memory, and the address H ' The upper area composed of 1A000000 to H′1BFFFFFF is an I / O area when the I / O card IOC functions as an input / output device. As a result, the common memory or attribute memory area in the areas 5 and 6 is a so-called 32 MB address space.
[0040]
Although not particularly limited, whether the area divided into two, that is, the I / O card IOC, functions as a memory or an input / output device is selectively designated by an address signal A25, and the remaining 25 MB of address space is 25. It is alternatively designated by bit address signals A0 to A24. As is well known, the PCMCIA standard allows a PC card to have a maximum address space of 64 MB. In this case, as will be described later, an address signal A25 of the most significant bit further passes through the output port of the microprocessor MPU. Is output on another route. As described above, the physical address space of the area 6 is divided into two and can be selectively designated by the address A25, so that the function of the I / O card IOC coupled to the area 6 as a memory or an input / output device can be realized by software. As a result, it is possible to dynamically switch, and the convenience of the microprocessor MPU is improved.
[0041]
As described above, the physical address space of the microprocessor MPU is divided into eight areas, seven of which are fixedly assigned to various semiconductor memories or PC cards coupled to the external bus E-BUS of the microprocessor MPU. From the user's point of view, this seems to cause a restriction on the distribution of logical addresses in software. However, in this embodiment, as described above, the microprocessor MPU is provided with the memory management unit MMU, and the correspondence between the internal logical address and the physical address on the external bus E-BUS is the rewriting of the address translation buffer TLB, That is, it can be easily changed by rewriting the contents of an address translation pair in an address translation table stored in an external memory coupled to the external bus E-BUS, for example, a DRAM. For this reason, the user is released from the restriction by the physical address of the external bus E-BUS, and can construct software having a free logical address space.
[0042]
7 and 8 are connection diagrams of an embodiment for explaining the connection form of the external bus E-BUS of the microprocessor MPU of FIG. 9 shows an interface configuration diagram of an embodiment when the external bus E-BUS of FIG. 7 and FIG. 8 and the PC card are combined, and FIG. 10 and FIG. A signal configuration diagram of one embodiment of eight external buses E-BUS is shown. 7 and 8, semiconductor memories that can be coupled to areas 0 to 4 are appropriately assigned. However, in some cases, combinations that can be coupled are limited depending on the area. 10 and 11 should be referred to as appropriate in the course of the description of FIGS.
[0043]
In FIG. 7, the external bus E-BUS includes 26-bit external address buses EBA0 to EBA25 that are address output buses when viewed from the microprocessor MPU, and 32-bit external data buses EBD0 to EBD31 that are input / output buses. . Of these, the address signals A0 to A25 transmitted through the address buses EBA0 to EBA25 are commonly supplied to all areas to which various semiconductor memories and PC cards are coupled, but the external data buses EBD0 to EBD31 are A selective connection form is adopted according to the bus size of the semiconductor memory and the PC card coupled to the external bus E-BUS. In DRAM and SDRAM, row and column addresses are supplied to the same line on the address bus in a time-sharing manner, so that each address input terminal of the DRAM and SDRAM has a predetermined number of external address buses EBA0 to EBA25. Will be connected to the line.
[0044]
That is, in the microprocessor MPU of this embodiment, the bus sizes of area 0 to area 6 can be designated for each area by a bus control register BCR2 of the bus state controller BSC described later. Of these, in area 0, the bus size of bytes (8 bits), words (16 bits), and long words (32 bits) can be arbitrarily selected. In areas 1 to 6, each area is SRAM, ROM, or burst. When assigned to ROM, byte, word or long word can be selected arbitrarily, but when assigned to SDRAM, DRAM or PSRAM, it is limited to selection of word or long word by combination with memory control register MCR1. The Further, when area 2 and area 3 are allocated to the DRAM, the bus size is limited to only words, and when area 5 and area 6 are allocated to the PC card, either byte or word is selected.
[0045]
Thereby, the lower 16-bit data buses EBD0 to EBD15 are coupled to all the semiconductor memories and PC cards assigned to the areas 0 to 6, but the upper 16-bit data buses EBD16 to EBD23 and EBD24 to EBD31 are These are selectively coupled according to the bus size of each area. The 8-bit data buses EBD16 to EBD23 can also be used as general-purpose ports PORT0 to PORT7 on condition that the area bus size is 16 bits or less, as will be exemplified later. In this case, however, the port function enable bit of the bus state controller BSC2 is set to logic "1".
[0046]
The external bus E-BUS is a bus start signal -BS indicating that data on the external bus E-BUS is valid (here, a so-called inverted signal or the like that is selectively set to a low level when it is valid). Is provided with an external control bus EBC as a control signal line for transmitting-. This signal -BS is converted into an activation signal necessary for various semiconductor memories and PC cards by the bus state controller BSC. For this reason, the bus start signal -BS is supplied to an I / O controller having a bus management function, such as the display controller LCDC and the keyboard controller KBDC, but is not supplied to a semiconductor memory and a PC card having no bus management function. .
[0047]
On the other hand, the external control bus EBC of the external bus E-BUS includes a control signal line for transmitting chip select signals -CS0 to -CS6 for alternatively designating area 0 to area 6, and an area 0 bus. A control signal line is provided for transmitting mode signals MD3 to MD5 used for specifying the size and endian. Of these, the chip select signals -CS5 and -CS6 are used together as card enable signals -CE1 for the area 5 and area 6 PC cards, that is, -CE1A and -CE1B, respectively. The mode signals MD3 and MD4 are used together as card enable signals -CE2 for these PC cards, that is, -CE2A and -CE2B, respectively. The mode signal MD5 is a row address strobe for the second set of DRAMs coupled to the area 3. It is used together as signal -RAS2.
[0048]
The external control bus EBC of the external bus E-BUS further includes a control signal line for transmitting a row address strobe signal -RAS serving as an activation control signal for various semiconductor memories and PC cards, and column address strobe signals -CASLL, -CASLH. , -CASHL and -CASHH, control signal lines, write enable signals -WE0 to -WE3, read / write status signal RD / -WR, read control signal -RD, I / O clock signal CKIO, A control signal line for transmitting each of the clock enable signals CKE is provided. The I / O clock signal CKIO indicates a system clock input to the microprocessor MPU or an operation clock signal supplied to the SDRAM when the SDRAM is connected. The microprocessor MPU receives the I / O clock signal CKIO. Based on this, the timing management of various output signals is performed.
[0049]
Among these, the row address strobe signal -RAS is supplied as the row address strobe signal -RAS for the DRAM and SDRAM, and is also used as the chip enable signal -CE for the PSRAM in the area 3. The column address strobe signals -CASLL, -CASLH, -CASHL and -CASHH are columns corresponding to the data buses D0 to D7, D8 to D15, D16 to D23 and D24 to D31 for a 32-bit bus size DRAM. Of these, the column address strobe signal -CASLL is used as the column address strobe signal -CAS for the SDRAM or the output enable signal -OE for the PSRAM, and the column address strobe signals -CASHL and -CASHH are supplied as the address strobe signal. The byte address column address strobe signals -CAS2L and -CAS2H for the second set of DRAMs are used together.
[0050]
Write enable signals -WE0 to -WE3 are write enable signals or data corresponding to data buses EBD0 to EBD7, EBD8 to EBD15, EBD16 to EBD23, and EBD24 to EBD31, respectively, for 32-bit bus size SRAM and PSRAM or SDRAM. The control signals DQMLL, DQMLU, DQMUL, and DQMUU are supplied. Of these, the write enable signal -WE2 is used together as the I / O read control signal -ICIOORD for the I / O card IOC in the area 6, and the write enable signal- WE3 is used together as an I / O write control signal-ICIOWR.
[0051]
The read / write status signal RD / -WR is supplied as a write enable signal -WE for DRAM and SDRAM, and is also used as a read / write signal R / -W for an I / O controller (not shown). The read control signal -RD is supplied as an output enable signal -OE for the ROM and SRAM and the memory card MEMC and the I / O card IOC, and the I / O clock signal CKIO and the clock enable signal CKE are supplied to the SDRAM. Is done.
[0052]
In this embodiment, the external bus E-BUS includes a control signal line for transmitting a write protect signal WP as an external input bus dedicated to a PC card, and wait control signals -WAIT, bus request signals as bus control signals. A control signal line for transmitting each of the BREQ and the bus acknowledge signal BACK is provided. Of these, the write protect signal WP is selectively input from the memory card MEMC that requires write prohibition, and 16 for notifying the microprocessor MPU that the bus size of the I / O card IOC is 16 bits. It is also used as a bit I / O port signal-IOIS16.
[0053]
The wait control signal -WAIT is selectively input as necessary from a PC card, an I / O controller, and the like that require the microprocessor MPU to wait for a cycle. Further, the bus request signal -BREQ is selectively input as needed from a bus master who wants to occupy the external bus E-BUS, and the bus acknowledge signal BACK is output from the microprocessor MPU as a bus use permission signal for these bus masters. . The write enable signal -WE1 output from the microprocessor MPU is transmitted to the PC card as the write enable signal -WE / -PGM. Note that the various semiconductor memories and PC cards shown in FIG. 8 do not have a function as a bus master.
[0054]
Although not included in the external bus E-BUS, the memory card MEMC and the I / O card IOC receive card detection signals -CD1 and -CD2 respectively indicating that the PC card is installed in the PC card slots PCSL1 and PCSL2. A control signal line for transmitting and a control signal line for transmitting the reset signal RESET are coupled. These control signals are detected by a board controller BC provided in the mother board MBD and used for board control. The motherboard MBD further includes a terminal for inputting a power supply voltage VCC and a ground potential GND as an operation power supply. The power supply voltage and the ground potential are paired with various semiconductor memories, PC cards, I / O controllers and a microprocessor MPU. Distribute via the power supply line.
[0055]
As described above, the PC card such as the memory card MEMC or the I / O card IOC is coupled to the external bus E-BUS via the PC card buffer BUF1 or BUF2, and the address signal A25 is the I / O card in the area 6. It serves to identify whether the IOC functions as a memory or an input / output device. Therefore, when the memory card MEMC and the I / O card IOC have a 64 MB address area, as shown in FIG. 9, the address used for selecting the highest address through the port PORT of the microprocessor MPU. The signal A25 is output again. The port PORT includes a reset signal RESET and an attribute memory space selection signal -REG.
[0056]
Motherboard MBD includes an encoder ENCODER for setting interrupt levels IRL0 to IRL3. Needless to say, these signals conform to the PCMCIA standard. As shown in FIG. 9, the PC card buffer BUF1 or BUF2 includes a bidirectional buffer B1 provided in the external data buses EBD0 to EBD7 and a bidirectional buffer B2 provided in the external data buses EBD8 to EBD15. In the bidirectional buffers B1 and B2, the data transmission direction (DIR) is controlled by the read / write status signal RD / -WR, respectively, and the gating operation (G) is controlled by the card enable signals -CE1B and -CE2B. Is done.
[0057]
FIG. 12 is a block diagram showing an embodiment of the bus state controller BSC included in the microprocessor MPU of FIG. In the figure, the bus state controller BSC is connected to the cache bus interface unit CBIF via the cache bus interface unit CBIF coupled to the cache bus C-BUS of the microprocessor MPU and the module bus M-BUS in the bus state controller BSC. Combined address register ADR, data register DTR, wait control registers WCR1 and WCR2, bus control registers BCR1 and BCR2, memory control register MCR, DRAM control register DCR, PCMCIA control register PCR, refresh count register RFCR, refresh timer count register RTCNT , Refresh time constant register RTCOR and Refre And a shoe timer control status register RTCSR.
[0058]
The contents of these registers can be arbitrarily rewritten by the central processing unit CPU of the microprocessor MPU, that is, its software. That is, the central processing unit CPU sends each register (ADR, DTR, WCR1, WCR2, BCR1, BCR2, MCR, DCR, PCMCIA, through the cache bus C-BUS, the cache bus interface unit CBIF, and the module bus M-BUS. The contents of PCR, RFCR, RTCNT, RTCOR and RTCSR) can be written or changed.
[0059]
The bus driver BSC is supplied with an operation clock CK generated from a clock pulse generator CPG shown in FIG. 4 as an operation clock for determining the operation timing. The clock signal CK is a clock having the same frequency as the operation clock of the central processing unit CPU, and is output from the system clock input / output terminal CKIO as a system clock to the outside of the micro processor MPU. As will be described later, the system clock output from the system clock input / output terminal CKIO is used as an operation clock of the synchronous DRAM.
[0060]
Address register ADR is coupled to address controller ADC. The output terminal of the data register DTR is coupled to one input terminal of the multiplexer MPX, and the other input terminal of the multiplexer MPX is coupled to the ports PORT0 to PORT7. On the other hand, the wait control registers WCR1 and WCR2 are coupled to the wait control unit WATEC, and the bus control register BCR1 is coupled to the area control unit AREAC.
[0061]
The bus control register BCR2, the memory control register MCR, the DRAM control register DCR, and the PCMCIA control register PCR are coupled to the memory timing control unit MTC, and the refresh count register RFCR, the refresh timer count register RTCNT, the refresh time constant register RTCOR, and the refresh timer control The status register RTCSR is coupled to the refresh control unit RFC.
[0062]
The output terminals of address control unit ADC are coupled to address buses EBA0 to EBA25 of external bus E-BUS, respectively, and the output terminals of multiplexer MPX are coupled to data buses EBD0 to EBD31, respectively. Further, the output signal of the wait control unit WATEC is the wait control signal -WAIT, and the output signals of the area control unit AREAC are the chip select signals -CS0 to -CS6 and the card enable signals -CE2A and -CE2B.
[0063]
The output signal of the memory timing control unit MTC is a bus start signal-BS, a row address strobe signal-RAS / chip enable signal-CE, a column address strobe signal-CAS / -CASxx (here, for example, four column address strobe signals- CASLL, -CASLH, -CASHL, and -CASHH are collectively referred to as -CASxx, and the same applies hereinafter), write enable signal -WEx / data control signal DQMxx, I / O read control signal -ICIORD / I / O write control signal -ICIOWR, read / write status signal RD / -WR, read control signal -RD, write protect signal WP / 16 bit I / O port signal -IOIS16 and clock enable signal The KE.
[0064]
The address control unit ADC transmits address signals A0 to A25 transmitted through the address bus of the cache bus C-BUS to the address buses EBA0 to EBA25 of the external bus E-BUS and continuously accesses a series of addresses. Address generation function for autonomously updating predetermined bits of the address signal in the burst mode.
[0065]
The multiplexer MPX couples the data buses EBD0 to EBD31 of the cache bus C-BUS and the external bus E-BUS, and switching control when predetermined bits of the data bus, that is, the data buses EBD16 to EBD23 are used as the ports PORT0 to PORT7. I do. As described above, the bus state controller BSC is provided with the address control unit ADC and has an address generation function for the burst mode, so that the semiconductor memory and the PC card having the burst mode can be obtained without increasing the number of external components of the microprocessor. Can be connected, and the continuous access can be speeded up.
[0066]
The wait control unit WATEC transmits a cycle wait request from the PC card or the I / O controller, which is performed via the wait signal -WAIT of the external bus E-BUS, to the microprocessor MPU. Also, based on the constants written in the wait control registers WCR1 and WCR2, insertion of an idle cycle when switching from read access to write access and insertion of wait states for each area are selectively executed.
[0067]
The area control unit AREAC has attributes related to the allocation of the areas 0 to 6 written in the bus state control register BSC1 and area selection signals supplied via the address buses A26 to A28 of the cache bus C-BUS. And chip select signals -CS0 to -CS6 and card enable signals -CE2A and -CE2B are selectively formed.
[0068]
The memory timing control unit MTC is based on the attributes related to the bus size of area 0 to area 6 written in the bus control register BCR2 and the constants written in the memory control register MCR, DRAM control register DCR and PCMCIA control register PCR. In addition, activation control signals and the like necessary for operation control of various semiconductor memories and PC cards are selectively formed under predetermined timing conditions. Further, the refresh control unit RFC controls the refresh operation of the DRAM and SDRAM using the overflow interrupt function of the refresh counter.
[0069]
FIG. 13 shows a state transition diagram of one embodiment of the bus state controller BSC of FIG. FIG. 14 shows a state configuration diagram of one embodiment of the bus state controller BSC of FIG. 12, and FIG. 15 shows a transition condition diagram of one embodiment regarding the state transition. Further, FIG. 16 to FIG. 18 show an embodiment when accessing the memory card MEMC without the wait of the microprocessor MPU of FIG. 3, accessing the memory card MEMC with the wait, and accessing the memory card MEMC using the burst mode. FIG. 19 and FIG. 20 show an embodiment of the microprocessor MPU of FIG. 3 when accessing the I / O card IOC without a wait and when accessing the I / O card IOC with a wait. The signal waveform diagrams are respectively shown.
[0070]
Hereinafter, a specific description of the state transition of the bus state controller BSC will be made with reference to FIG. 13, but FIGS. 14 to 20 should be referred to as needed in the course of these descriptions. The state shown in FIGS. 13 to 15 is a partial state related to the control of the SRAM, burst ROM, and PC card, and the bus state controller BSC has many other states related to the control of other semiconductor memories and the like. Have.
[0071]
16 to 20 also show an I / O clock signal CKIO, a bus start signal −BS, and a read / write status signal RD / −WR that are not supplied to the memory card MEMC and the I / O card IOC for reference. Has been. The I / O clock signal CKIO used as the system clock or the operation clock of the central processing unit has a meaning as a reference clock signal for generating various timing signals shown in FIGS.
[0072]
In FIG. 13, the bus state controller BSC of this embodiment is a so-called state machine, and has 10 states ST1 to ST10 relating to control of SRAM and burst ROM, memory card MEMC and I / O card IOC. Among these, the state ST1 is an IDLE state as shown in FIG. 14, and corresponds to a standby state of the microprocessor MPU.
[0073]
States ST2 to ST4 are PCMCIA TED1 to PCMCIA TED3 states, which correspond to the address signals A0 to A25 of the write enable signal -WE1 and the output enable signal -OE serving as activation control signals for the PCMCIA, that is, the memory card MEMC and the I / O card IOC. This is for delaying the setup time by one cycle.
[0074]
States ST5, ST6, and ST7 are a NORM T1 state corresponding to an access start cycle, a NORM TW state corresponding to a wait cycle, and a NORM T2 state corresponding to an access end cycle, and states ST8 to ST10 are write enable signals. -WE1 and output enable signal-PCMCIA TEH1 state, PCMCIA TEH2 and PCMCIA TEH3 state for delaying the hold time of OE for address signals A0 to A25 by one cycle. The states ST1 to ST10 correspond to the cycles shown in FIGS. 16 to 20 in the form shown in the rightmost column of FIG.
[0075]
When the bus state controller BSC is in the IDLE of the state ST1, that is, in the standby state, the access request to the memory, that is, the external bus E-BUS is generated when the external bus E-BUS is empty, and the constant TED relating to the setup delay of the PCMCIA control register PCR is When the transition condition (1) of 1 to 3 is satisfied, the bus state controller BSC transitions to the state ST2 and enters a delay cycle of the setup time of the write enable signal -WE1 and the output enable signal -OE. At this time, in the memory card MEMC and the I / O card IOC, as illustrated in FIG. 17 and FIG. 20, first, the bus start signal -BS, that is, the write enable signal -WE1 and the output enable signal -by the Tpcm0 cycle or the Tpci0 cycle- The setup time of OE (read control signal-RD) is delayed by one cycle of the I / O clock signal CKIO.
[0076]
When the one cycle delay of the setup time by the state ST2 is completed and the transition condition (4) in which the constant TED of the PCMCIA control register PCR is 2 or 3 is satisfied, the bus state controller BSC transits to the state ST3 and is again write-enabled. A delay cycle of the setup time of signal -WE1 and output enable signal -OE is entered.
[0077]
At this time, in the memory card MEMC and the I / O card IOC, as illustrated in FIG. 17 and FIG. 20, the bus start signal -BS, that is, the write enable signal -WE1 and the output enable signal -OE is performed by the Tpcm0w cycle or the Tpci0w cycle. Is further delayed by one cycle of the I / O clock signal CKIO. Further, when the one-cycle delay of the setup time by the state ST3 is completed and the transition condition (3) in which the constant TED of the PCMCIA control register PCR is 2 is satisfied, the bus state controller BSC transits to the state ST5, and the access start cycle to go into.
[0078]
At this time, in the memory card MEMC and the I / O card IOC, as illustrated in FIG. 17 and FIG. 20, the bus start signal -BS, that is, the output enable signal -OE (I / O read control) is performed in the Tpcm1 cycle or the Tpci1 cycle. The signal -ICIOORD) or the write enable signal -WE1 (I / O write control signal -ICIOWR) is set to the low level effective level, and substantial data reading or writing is executed for the address specified by the address signals A0 to A25. The
[0079]
When the transition condition (2) in which the one cycle delay of the setup time is completed in the state ST2 and the constant TED of the PCMCIA control register PCR is 1, the bus state controller BSC shifts to the state ST5 as it is, and enters the access start cycle. enter. When the transition condition (5) in which the one cycle delay of the setup time is completed and the constant TED of the PCMCIA control register PCR is 3 is satisfied in the state ST3, the bus state controller BSC transits to the state ST4, and the write enable signal -We delay the setup time of WE1 and output enable signal -OE by one more cycle. Then, in response to the end of the one cycle delay of the setup time in the state ST4, that is, the transition condition (6), the state transitions to the state ST5.
[0080]
On the other hand, when the transition condition (7) in which the external bus E-BUS is empty and a memory access request is generated and the constant TED of the PCMCIA control register PCR is 0 is satisfied in the standby state of the state ST1, the bus state controller BSC Directly transit to state ST5 and enter an access start cycle. At this time, in the memory card MEMC and the I / O card IOC, as illustrated in FIGS. 16 and 19, the Tpcm1 cycle without interposing the cycle for the setup delay of the write enable signal -WE1 and the output enable signal -OE. Alternatively, the Tpci1 cycle is executed, and data is read or written.
[0081]
Next, when the access start cycle by the state ST5 is completed and the transition condition (9) in which the constant WAIT of the wait control register WCR2 is 1, for example, is satisfied, the bus state controller BSC transits to the state ST6 and enters the wait cycle. . At this time, in the memory card MEMC and the I / O card IOC, as illustrated in FIG. 17 and FIG. 20, one wait state by two Tpcm1w or Tpci1w is inserted, and the output enable signal -OE (I / O The rise of the read control signal -ICIOORD) or the write enable signal -WE1 (I / O write control signal -ICIOWR) to the high level, that is, the end of the data read or write operation is delayed. During this time, the wait control signal -WAIT is set to the low level at a predetermined timing including the next rising edge of the I / O clock signal CKIO, and returned to the high level at the predetermined timing including the next rising edge.
[0082]
When the wait cycle in state ST6 ends and the transition condition (12) is satisfied, the bus state controller BSC transitions to state ST7 and enters an access termination cycle. At this time, in the memory card MEMC and the I / O card IOC, as illustrated in FIGS. 16 to 20, the output enable signal -OE (I / O read control signal -ICIOORD) or the write enable is performed by the Tpcm2 cycle or the Tpci2 cycle. The signal -WE1 (I / O write control signal -ICIOWR) is returned to the high invalid level, and the data read or write operation for the designated address is terminated. In the state ST6, when the constant WAIT of the wait control register WCR2 is set to 2 or more and the transition condition (10) that continuously requires the wait is satisfied, the bus state controller BSC inserts the wait cycle by the state ST6 again.
[0083]
When the access termination cycle by the state ST7 is completed, the bus state controller BSC selectively selects according to the termination state of the burst mode or all cycles and the constants TED and TEH of the PCMCIA control register PCR, that is, the setup time and hold time delay conditions. Transition to state ST1, ST2, ST5 or ST6. That is, the bus state controller BSC returns to the state ST6 when the transition condition (12) in which the burst mode is not completed is satisfied in the access termination cycle of the state ST7, and repeats this until the burst mode is terminated. At this time, in the memory card MEMC and the I / O card IOC, as illustrated in FIG. 18, the bus start signal -BS, the output enable signal -OE, and the like are intermittently formed by the number of bursts, and the bus state controller The address control unit ADC of the BSC sequentially generates lower 4 bits of address signals A0 to A3, and continuous access to a series of addresses is performed.
[0084]
On the other hand, in the access termination cycle of state ST7, for example, because the bus size is small, divided access is performed in units of bytes or words, the entire cycle is not completed, and the setup time and hold time are not delayed. When (13) is established, the bus state controller BSC returns to the state ST5 and repeats access. At this time, when the transition condition (14) that requires the setup time delay is satisfied, the bus state controller BSC transitions to the state ST2, and the transition conditions (16) to (18) that require the hold time delay are satisfied. Then, the state transits to the state ST8, ST9 or ST10 according to the number of delay cycles.
[0085]
The burst mode of the memory card MEMC and the I / O card IOC in the areas 5 and 6 is for realizing 16-byte access in the case of a cache file in the same manner as the page mode of the burst ROM. At this time, the number of times of data transfer in the burst mode can be set by the bus control register BCR1, and continuous access can be arbitrarily selected 4, 8, or 16 times. In the head access cycle at the time of reading in the burst mode, the data causing the read request is accessed, and in the remaining cycles, the 16-byte boundary data including the data is accessed in a wraparound. At the time of writing in the burst mode, writing is sequentially performed from the head corresponding to 16-byte boundary data. As described above, the number of wait state insertions during the first access and the second and subsequent accesses can be selectively set by the constant WAIT of the wait control register WCR2.
[0086]
When the transition condition (15) in which the end of all the cycles is confirmed and the hold time is not required is satisfied in the access termination cycle of the state ST7, the bus state controller BSC returns to the state ST1. At this time, if the constant TEH of the PCMCIA control register PCR is set to 1 or more and the transition conditions (16) to (18) requiring hold time delay are satisfied, the bus state controller BSC determines the number of delay cycles, that is, PCMCIA control. Depending on the value of the constant TEH of the register PCR, a transition is selectively made to the state ST8, ST9 or ST10.
[0087]
When the bus state controller BSC transitions to the delay cycle of the state ST8 in response to the establishment of the transition condition (16), the memory card MEMC and the I / O card IOC have Tpcm2w cycles as illustrated in FIGS. Alternatively, the Tpci2w cycle is inserted, and the next transition of the address signals A0 to A25 from the rising edge of the output enable signal -OE (I / O read control signal -ICIOORD) or the write enable signal -WE1 (I / O write control signal -ICIOWR). Hold time is delayed by one cycle. When the bus state controller BSC transitions to the delay cycle of the state ST9 in response to the establishment of the transition condition (17), the Tpcm2w cycle or the Tpci2w cycle is inserted twice, and the hold time is delayed by two cycles. When the BSC transitions to the delay cycle of the state ST9 in response to the establishment of the transition condition (18), three Tpcm2w cycles or Tpci2w cycles are inserted and the hold time is delayed by three cycles.
[0088]
In the state ST8, the termination condition similar to that in the state ST7 is selected at the end of the delay cycle, and the bus state controller BSC responds according to the termination state of all cycles and the constant TED of the PCMCIA control register PCR, that is, the setup time delay condition. Selectively transition to state ST1, ST2 or ST5. That is, the bus state controller BSC receives a transition condition (22) in which all cycles are not completed at the end of the delay cycle of state ST8 and does not require a setup time delay, and the delay of the setup time is changed to state ST5. In response to the establishment of the necessary transition condition (21), the process returns to the state ST2 to repeat access. When the end of all cycles is confirmed in the state ST8 and the transition condition (23) is satisfied, the process returns to the state ST1 and enters a standby state.
[0089]
In this way, by making the bus state controller BSC having a complicated function capable of supporting various semiconductor memories and PC cards as a state machine, the transition condition can be selectively set by constant rewriting of each control register. The interface conditions in areas 0 to 6 of the external bus E-BUS can be efficiently adapted to those of the semiconductor memory or PC card coupled to each area, and the logical configuration of the bus state controller BSC itself can be simplified. System flexibility can be increased.
[0090]
FIG. 21 shows a connection example when a synchronous DRAM and a PC card (MEMC / (IOC)) are connected to the microprocessor MPU of the present invention. Since the connection between the PC card (MEMC / (IOC)) and the microprocessor MPU has been described in detail in FIG. 9, only one part thereof is shown in FIG. In addition, the connection between the PC card (MEMC / (IOC)) and the microprocessor MPU is described in detail in FIG.
[0091]
As shown in FIG. 21, each of SDRAM1 and SDRAM2 has a memory configuration of 256K × 16 bits. SDRAM 1 includes address terminals A9-A0 coupled to receive address signals A11-A2 output from microprocessor MPU, a clock terminal CKL coupled to system clock input / output terminal CKIO of microprocessor MPU, and a microprocessor. A clock enable signal terminal CKE coupled to the clock enable signal terminal CKE of the MPU, a chip select signal terminal −CS coupled to the microprocessor MPU −CS 3, and a row address strobe signal terminal − of the microprocessor MPU A row address strobe signal terminal -RAS coupled to RAS / -CE and a column address strobe signal coupled to column address strobe signal terminal -CAS / -OE of the microprocessor MPU. Data input / output coupled to terminal -CAS, write enable signal terminal -WE coupled to read / write status signal terminal RD / -WR of microprocessor MPU, and data input / output terminals D31-D16 of microprocessor MPU, respectively. Terminal I / O15-I / O0 and data control signal terminals DQMU and DQML respectively coupled to data control signal terminals DQMUU and DQMUL of the microprocessor MPU.
[0092]
The SDRAM 2 includes address terminals A9-A0 coupled to receive address signals A11-A2 output from the microprocessor MPU, a clock terminal CKL coupled to the system clock input / output terminal CKIO of the microprocessor MPU, and a microprocessor. A clock enable signal terminal CKE coupled to the clock enable signal terminal CKE of the MPU, a chip select signal terminal −CS coupled to the microprocessor MPU −CS 3, and a row address strobe signal terminal − of the microprocessor MPU A row address strobe signal terminal -RAS coupled to RAS / -CE and a column address strobe signal coupled to column address strobe signal terminal -CAS / -OE of the microprocessor MPU. Data input / output coupled to terminal -CAS, write enable signal terminal -WE coupled to read / write status signal terminal RD / -WR of microprocessor MPU, and data input / output terminals D15-D0 of microprocessor MPU, respectively. Terminal I / O15-I / O0 and data control signal terminals DQMU and DQML respectively coupled to data control signal terminals DQMLU and DQMLL of the microprocessor MPU.
[0093]
As shown in FIG. 21, by combining a microprocessor MPU and a synchronous DRAM (SDRAM1, SDRAM2) having a fast address access time, the above-mentioned synchronous DRAM (SDRAM1, SDRAM2) is used as a 32-bit width memory. It can be used. The system clock signal output from the system clock input / output terminal CKIO of the microprocessor MPU is a clock signal having the same frequency as the operation clock of the central processing unit CPU, and is also supplied to the bus state controller BSC.
[0094]
FIG. 22 shows a bus cycle waveform diagram for explaining the burst read operation of the synchronous DRAM (SDRAM1, SDRAM2) shown in FIG. Although not shown in the figure, the clock enable signal CKE is at a high level. The clock enable signal CKE is selectively set to a low level when the synchronous DRAM is refreshed. The bus start signal -BS is a strobe signal for monitoring a bus cycle and is not connected to the synchronous DRAM.
[0095]
In the first cycle Tr, the signal -CS3 corresponding to the space to which the synchronous DRAM is allocated is set to the low level, the row address strobe signal -RAS is set to the low level, and the row address is taken into the synchronous DRAM. In the next cycle Tc, the column address strobe signal -CAS is set to the low level, and the column address is taken into the synchronous DRAM. As described above, the rising edge of the clock signal CKIO in the synchronous DRAM with respect to the signals -CS2, -RAS, -CAS and the address signal output in synchronization with the rising edge of the clock signal CKIO from the central processing unit CPU side. Each of the above signals is captured in synchronization with the above. That is, the reading operation of the synchronous DRAM or various operations not shown are controlled based on the clock signal CKIO.
[0096]
In the third cycle Td1, -CAS is reset to high level. Then, the data D31 to D0 are continuously read from the synchronous DRAM as shown as 1D-4D over the fourth and subsequent cycles of Td1 to Td4. By such burst read, data of 4 bytes × 4 cycles = 16 bytes can be read. The generation of the control signal at the timing as described above is formed by the bus state controller BCS.
[0097]
FIG. 23 is a block diagram showing an embodiment of the synchronous DRAM (hereinafter simply referred to as SDRAM). The SDRAM shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
[0098]
The SDRAM of this embodiment includes a memory array 200A that constitutes a memory bank A (BANKA) and a memory array 200B that constitutes a memory bank (BANKB). Each of the memory arrays 200A and 200B includes dynamic memory cells arranged in a matrix, and according to the figure, the selection terminals of the memory cells arranged in the same column are coupled to word lines (not shown) for each column, Data input / output terminals of memory cells arranged in the same row are coupled to complementary data lines (not shown) for each row.
[0099]
One word line (not shown) of the memory array 200A is driven to a selected level according to the decoding result of the row address signal by the row decoder 201A. Complementary data lines (not shown) of memory array 200A are coupled to sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplification circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from the memory cell. In this case, the column switch circuit is a switch circuit for selecting a complementary data line and making it conductive to the complementary common data line 204. The column switch circuit is selectively operated according to the decoding result of the column address signal by the column decoder 203A.
[0100]
Similarly, a row decoder 201B, a sense amplifier and column selection circuit 202B, and a column decoder 203B are also provided on the memory array 200B side. The complementary common data line 204 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. The input terminal of the input buffer 210 and the output terminal of the output buffer 211 are connected to 16-bit data input / output terminals I / O0 to I / O15.
[0101]
The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. The row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of the column address counter 207. The column address counter 207 receives the column address signal as the preset data or the column address signal according to the operation mode specified by the command or the like. The sequentially incremented value is output to the column decoders 203A and 203B.
[0102]
The controller 212 is not particularly limited, but includes an input terminal CLK to which the clock signal CKIO is input, an input terminal to which the clock enable signal CKE is input, an input terminal to which the chip select signal -CS is input, and a column address strobe signal. An input terminal to which CAS is input, an input terminal to which a row address strobe signal -RAS is input, an input terminal to which a write enable signal -WE is input, and an input terminal to which data control signals DQMU and DQML are input Combined with The controller 212 is supplied with the external control signals supplied from the input terminals and the control data from the address input terminals A0 to A9. Based on the level change and timing of these signals, the operation mode of the SDRAM and the above-described control data are supplied. It forms an internal timing signal for controlling the operation of the circuit block, and includes a control logic (not shown) and a mode register 30 for that purpose.
[0103]
The clock signal CKIO is the SDRAM's macter clock, and other external input signals are significant in synchronization with the rising edge of the clock signal CKIO. The chip select signal -CS instructs the start of the command input cycle according to its low level. When the chip select signal -CS is at a high level (chip non-selected state) or other inputs are meaningless. However, the memory bank selection state and the internal operation such as the burst operation are not affected by the change to the chip non-selection state. Each of the -RAS, -CAS, and -WE signals has a function different from that of a corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle.
[0104]
The row address signal is defined by the levels of A0 to A8 in the row address strobe / bank active command cycle synchronized with the rising edge of the clock signal CKIO. The input from A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is low level, the memory bank BANKA is selected, and when it is high level, the memory bank BANKB is selected. The selection control of the memory bank is not particularly limited, but only the row decoder on the selected memory bank side is activated, all the column switch circuits on the non-selected memory bank side are not selected, only the input buffer 210 and the output buffer on the selected memory bank side It can be performed by a process such as connection to 211.
[0105]
The input of A8 in the precharge command cycle indicates the mode of the precharge operation for the complementary data line, etc., the high level indicates that the target of the precharge is both memory banks, and the low level is indicated by A9. It is instructed that one of the memory banks being subjected to the precharge. The column address signal is defined by the levels of A0 to A7 in a read or write command (column address / read command, column address / write command) cycle synchronized with the rising edge of the clock signal CKIO. The column address thus defined is used as a burst access start address.
[0106]
Thus, the operation of the synchronous DRAM is controlled based on the clock signal CKIO. On the other hand, the operation control of the memory card MEMC or the I / O card IOC as the PC card is also controlled based on the clock signal CKIO as understood from the operation description of the bus state controller BSC. Therefore, when controlling the operation of the PC card (memory card MEMC, I / O card IOC) while operating the synchronous DRAM at high speed, the output enable signal -OE or write enable signal -WE as the PC card activation signal is used. There is a case where the falling edge of the clock signal CKIO or the setup time for the address signal cannot satisfy the PC card standard.
[0107]
Therefore, as will be understood from the explanation of the operation of the bus state controller BSC or FIGS. 17 and 20, the PCMCIA control register PCR is provided in the bus state controller BSC, and the constant TED or hold delay related to the setup delay of the PCMCIA control register PCR. Based on the constant TEH, the fall of the clock signal CKIO of the output enable signal -OE or write enable signal -WE as the PC card activation signal or the setup time and hold time for the address signal are controlled.
[0108]
In this way, the fall of the clock signal CKIO of the output enable signal -OE or write enable signal -WE as the PC card activation signal or the setup time for the address signal can be controlled, so that the PC card and the synchronous DRAM can be controlled. Can be simultaneously coupled to the microprocessor MPU of the present invention, the microprocessor MPU of the present invention can access the PC card and the synchronous DRAM without any inconvenience.
[0109]
The operational effects obtained by the above embodiment are as follows. That is,
(1) Various semiconductor memories such as ROMs, burst ROMs, SRAMs, PSRAMs, DRAMs and synchronous DRAMs, and PCs such as memory cards and I / O cards, which are coupled to an external bus to a microprocessor incorporated in a personal computer or the like By providing a bus state controller that can control the interface of the card in parallel, it is possible to couple various semiconductor memories and PC cards directly and simultaneously to the external bus of the microprocessor, while reducing external parts for interface control. The effect that it can be obtained.
[0110]
(2) In the above item (1), the address space of the external bus is divided into a predetermined number of areas, and various semiconductor memories or PC cards are fixedly allocated to these areas, and the internal logical addresses are assigned to the microprocessor. By providing a memory management unit for converting to a physical address on the external bus, it is possible to release the user from the restriction by the physical address of the external bus E-BUS and to construct software having a free logical address space.
[0111]
(3) In the above items (1) and (2), the physical address space of the I / O card is further divided into two, and the physical address when the I / O card functions as a memory and the function as an input / output device The function of the I / O card as a memory or input / output device is dynamically switched by software by allocating the physical address independently and selectively specifying these address spaces by predetermined bits of the address signal. The effect that it can be obtained.
[0112]
(4) In the above items (1) to (3), the bus state controller is a state machine, and the type of semiconductor memory or PC card assigned to each area and its operating conditions can be easily set by software. By providing registers, the interface conditions in each area can be efficiently adapted to the interface conditions of the corresponding semiconductor memory or PC card, and the logical configuration of the bus state controller itself is simplified and the flexibility of the system is increased. be able to
[0113]
(5) In the above items (1) to (4), by providing the bus state controller with an address generation function for the burst mode, the semiconductor having the burst mode without increasing the number of external components of the microprocessor. The effect that the memory and the PC card can be combined and the access speed can be increased is obtained.
[0114]
(6) According to the above items (1) to (5), the usability of the microprocessor can be improved, and the number of external components can be reduced by reducing the design man-hours for personal computers with built-in microprocessors and PC card interfaces. And the effect that the cost reduction can be achieved is acquired.
[0115]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the types and number of semiconductor memories and PC cards coupled to the external bus E-BUS of the microprocessor MPU, that is, the motherboard MBD, and combinations thereof may take various embodiments. Further, the personal computer can be provided with various input / output devices, and the block configuration and connection form thereof are arbitrary. In FIG. 2, the external configuration of the personal computer is not restricted by these embodiments. In FIG. 3, the microprocessor MPU can take an arbitrary block configuration, and its bus form is also arbitrary. In FIG. 4, the substrate arrangement of the microprocessor MPU shown is an example of the present invention and does not limit the present invention.
[0116]
5 and 6, the physical address space of the external bus E-BUS can be divided into an arbitrary number of areas, and the allocation to various semiconductor memories and PC cards can be arbitrarily set. 7 to 11, the signal configuration of the external bus E-BUS, the effective level and function of each signal, the combination with various semiconductor memories and PC cards, etc. are not restricted by these embodiments.
[0117]
In FIG. 12, the block configuration of the bus state controller BSC is arbitrary including the type and combination of registers provided. 13 to 15, the logical configuration as the state machine of the bus state controller BSC, the function of each state, the transition condition, and the like can take various embodiments. In FIG. 16 to FIG. 20, the logic levels and time relationships of the address signal and the activation control signal in each access mode are not restricted by this embodiment.
[0118]
In the above description, the case where the invention made mainly by the present inventor is applied to the microprocessor constituting the personal computer which is the field of use behind the invention has been described. However, the present invention is not limited thereto. The present invention can also be applied to a similar microprocessor constituting a portable information terminal and a computer. The present invention can be widely applied to a microprocessor having at least an external bus and an apparatus or system including such a microprocessor.
[0119]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a microprocessor incorporated in a personal computer, a portable information terminal, etc., is coupled to its external bus, and various semiconductor memories such as ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous DRAM, memory cards, and I / O By providing a bus state controller capable of controlling the interface of a PC card such as a card in parallel, various semiconductor memories and PC cards can be directly and simultaneously coupled to a microprocessor while reducing external components for interface control.
[0120]
The address space of the external bus of the microprocessor is divided into a predetermined number of areas, and various semiconductor memories or PC cards are fixedly assigned to each area, and the internal logical address is converted to a physical address on the external bus to the microprocessor. By providing the memory management unit, it is possible to release the user from the restriction due to the physical address of the external bus of the microprocessor and to construct software having a free logical address space.
[0121]
The physical address space of the I / O card is further divided into two, and the physical address when the I / O card functions as a memory and that when the I / O card functions as an input / output device are assigned independently, and these address spaces are assigned to address signals. The function as the memory or input / output device of the I / O card can be dynamically switched by software.
[0122]
A semiconductor that corresponds to interface conditions in each area by providing a control register that can easily set the type of semiconductor memory or PC card assigned to each area and its operating conditions by software, using a bus state controller as a state machine It is possible to efficiently adapt to the interface conditions of the memory or PC card, simplify the logical configuration of the bus state controller itself, and increase the flexibility of the system.
[0123]
By giving the bus state controller an address generation function for burst mode that continuously accesses a series of addresses, semiconductor memory and PC cards having burst mode can be added to the microprocessor without increasing the number of external components of the microprocessor. It can be combined to speed up access.
[0124]
As a result, the usability of the microprocessor can be improved, the design man-hours for personal computers with built-in microprocessors and PC card interfaces can be reduced, the number of external parts can be reduced, and the cost of personal computers, etc. can be reduced. Can be achieved.
[Brief description of the drawings]
FIG. 1 is a system configuration diagram showing an embodiment of a personal computer including a microprocessor according to the present invention.
FIG. 2 is an external configuration diagram showing an embodiment of the personal computer shown in FIG. 1;
3 is a block diagram showing an embodiment of a microprocessor included in the personal computer of FIG. 1. FIG.
4 is a board layout showing an embodiment of the microprocessor of FIG. 3; FIG.
FIG. 5 is an address map showing an embodiment for explaining an address space of an external bus of the microprocessor of FIG. 3;
6 is an address map showing one embodiment for explaining an address space in areas 5 and 6 of the external bus of the microprocessor of FIG. 3; FIG.
7 is a partial connection diagram showing an embodiment for explaining a connection form of an external bus of the microprocessor of FIG. 3; FIG.
FIG. 8 is another partial connection diagram showing an embodiment for explaining the connection form of the external bus of the microprocessor of FIG. 3;
9 is a partial interface configuration diagram showing an embodiment when a PC card is coupled to the external bus of FIGS. 7 and 8. FIG.
10 is a partial signal configuration diagram showing an embodiment of the external bus shown in FIGS. 7 and 8. FIG.
11 is another partial signal configuration diagram showing an embodiment of the external bus shown in FIGS. 7 and 8. FIG.
12 is a block diagram showing an embodiment of a bus state controller included in the microprocessor of FIG. 3; FIG.
13 is a state transition diagram showing an embodiment of the bus state controller of FIG.
FIG. 14 is a state configuration diagram showing an embodiment of the bus state controller of FIG. 13;
FIG. 15 is a transition condition diagram showing an embodiment for explaining state transition of the bus state controller of FIG. 13;
16 is a signal waveform diagram showing an embodiment when accessing a memory card without a wait of the microprocessor of FIG. 3; FIG.
FIG. 17 is a signal waveform diagram showing an embodiment when a memory card is accessed with a wait of the microprocessor of FIG. 3;
FIG. 18 is a signal waveform diagram showing one embodiment when a memory card is accessed using the burst mode of the microprocessor of FIG. 3;
FIG. 19 is a signal waveform diagram showing an embodiment when accessing an I / O card without the wait of the microprocessor of FIG. 3;
FIG. 20 is a signal waveform diagram showing an example of accessing the I / O card with the wait of the microprocessor of FIG. 3;
FIG. 21 is an interface configuration diagram partially showing an embodiment when a PC card and a synchronous DRAM are coupled to the microprocessor of FIG. 3;
FIG. 22 is a signal waveform diagram showing an embodiment when accessing a synchronous DRAM;
FIG. 23 is a block diagram showing an embodiment of a synchronous DRAM.
[Explanation of symbols]
MBD ... Motherboard, POWU ... Power supply unit, MPU ... Microprocessor, E-BUS ... External bus, ROM ... Read only memory, BROM ... Burst ROM, SRAM ... Static RAM, PSRAM ... Pseudo SRAM, DRAM ... Dynamic RAM, SDRAM ... Synchronous DRAM, BUF1 to BUF2 ... PC card buffer, PCSL1 to PCSL2 ... PC card slot, MEMC ... Memory card, IOC ... I / O card, LCDC ... Display controller, LCDCON ... Display connector, LCD (DP) ... Liquid crystal Display, KBDC ... Keyboard controller, KBDCON ... Keyboard connector, KBD (KB) ... Keyboard,
MSLOT ... PC card slot, Ffile ... file, FDD ... floppy disk drive, PEN ... input pen.
CPU: Central processing unit, ALU: Arithmetic unit, MULT: Multiplier, MMU ... Memory management unit, TLB ... Address translation table, CACHE (Cache) ... Cache memory, BSC ... Bus state controller, REFC ... Refresh controller, DMAC ... Direct Memory access controller, TIM (Timer) ... Timer circuit, SCI ... Serial communication interface, D / A (D / A converter) digital / analog converter circuit, A / D (A / D converter) ... Analog / digital converter circuit, INTC ... Interrupt Controller, CPG ... Clock generation circuit, S-BUS ... System bus, C-BUS ... Cache bus, P-BUS ... Peripheral bus,
ENCODER ... Encoder, OG ... Or gate, PORT ... Port,
CBIF: Cache bus interface unit, M-BUS: BSC module bus, ADR: Address register, ADC: Address control unit, DTR: Data register, MPX ... Multiplexer, WCR1 to WCR2: Wait control register, WATEC: Wait control unit, BCR1 BCR2: Bus control register, AREAC ... Area control unit, MCR ... Memory control register, DCR ... DRAM control register, PCR ... PCMCIA control register, MTC ... Memory timing control unit, RFCR ... Refresh count register, RTCNT ... Refresh timer count register , RTCOR: Refresh time constant register, RTCSR: Refresh timer control status Register, RFC ... refresh control unit, ST1~ST10 ... state,
22 ... SDRAM, 30 ... mode register, 200A, 200B ... memory array, 201A, 201B ... row decoder, 202A, 202B ... sense amplifier and column selection circuit, 203A, 203B ... column decoder, 205 ... column address buffer, 206 ... row Address buffer, 207 ... column address counter, 208 ... refresh counter, 210 ... input buffer, 211 ... output buffer, 212 ... controller.

Claims (6)

A microprocessor on a semiconductor substrate, comprising a central processing unit, a first terminal, a second terminal, an address control circuit, a data input / output circuit, a control signal generation circuit, and a control register,
The central processing unit provides an address signal for accessing an address in the external address space of the microprocessor;
The control register stores information for determining access timing when connected to a PCMCIA card by the central processing unit ,
The information includes a constant that defines an output timing for the address signal,
The address control circuit is connected to the first terminal, and outputs an address signal from the central processing unit to the outside of the microprocessor;
The data input / output circuit is connected to the second terminal;
The control signal generation circuit responds to an address signal, generates a control signal for output to the outside of the microprocessor,
When the control signal generation circuit detects an address signal indicating an address in the first address space for the PCMCIA card, it generates a card enable signal as a control signal,
When the control signal generation circuit detects an address signal indicating an address in the second address space for the semiconductor memory, the control signal generation circuit generates a chip select signal as a control signal for the semiconductor memory,
The control signal generation circuit generates a read or write strobe control signal in response to the output of the address signal, and outputs the strobe control signal to the PCMCIA card according to a constant that defines information output timing of the control register. Adjust the timing and output,
The microprocessor receives a detection signal indicating that the PCMCIA card is inserted,
The microprocessor, wherein the control signal generation circuit outputs the card enable signal and the strobe control signal when the detection signal indicates insertion of the PCMCIA card. In claim 1,
The external address space of the microprocessor is divided into a plurality of address spaces including first and second address spaces,
The microprocessor includes a register for storing data for deciding to allocate the first address space to a PCMCIA card and to allocate the second address space to a semiconductor memory. In claim 1,
The microprocessor according to claim 1, wherein the address control circuit includes an address generation circuit for automatically updating an address signal in a burst mode in which a series of addresses in the external address space are continuously accessed. In claim 1,
A memory management unit,
The memory management unit converts an address signal as a logical address signal generated from the central processing unit into a physical address,
The microprocessor according to claim 1, wherein the address control circuit receives a physical address as an address signal and supplies the address signal to the first terminal. In claim 1,
The PCMCIA card connected to the microprocessor can be connected to either or both of a memory card and an IO card,
The microprocessor characterized in that the control signal generation circuit outputs the card enable signal according to the number of PCMCIA cards to be connected. In claim 1,
In addition, it has a bus control register,
2. The microprocessor according to claim 1, wherein the bus control register stores information capable of determining a bus width for the first address space for the PCMCIA card and a bus width for the second address space for the semiconductor memory .

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