JP2002049608A - Microprocessor, interface unit, interface method and data movement method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor, an interface unit, an interface method and a data movement method which are improved in usability. SOLUTION: The microprocessor has a system clock, and there are provided an interface unit, an address access unit, a PC card control means and an external clock means. The interface unit makes a memory and the PC card directly connectable to the microprocessor. The address access unit corresponds to the system clock changing from the first status to the second status in order to access an external address space. The PC card control means stores setup data of the PC card including a setup time for address signal control and a hold time for holding address signal. The external clock means is connected to the memory, and also the system clock is connected to be used for a synchronous DRAM(dynamic random access memory).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, an interface unit, an interface method, and a data moving method, and more particularly to a technique effective when used in a bus interface technique.

[0002]

2. Description of the Related Art PCMCIA (Personal Computer Memo)
(ry Card International Association) interface is an IC in the PC card guidelines ver4.1 and 4.2
There are an IC memory card interface and an I / O card interface of a 68-pin IC memory card specified by the memory card guideline ver4.1. A dedicated IC chip (82365SL) is prepared for such a PCMCIA interface.

[0003]

The inventor of the present application has noticed that an IC memory card or an I / O card is indispensable as an external peripheral device of various small portable information devices.
It has been considered that a PCMCIA interface is mounted on a microprocessor.

An object of the present invention is to provide a microprocessor, an interface unit, an interface method, and a data moving method which are easy to use. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, it has a system clock,
An interface unit, an address access unit, a PC card control unit and an external clock unit,
The interface unit allows a memory and a PC card to be directly connected to the microprocessor, and the address access unit corresponds to a system clock that transitions from a first state to a second state to access an external address space. The PC card control means includes a setup time for controlling an address signal;
The external clock means is connected to a memory for storing setup data of a PC card including a hold time for holding an address signal.
A system clock is also connected for use by the random access memory.

According to the above-mentioned means, an IC memory card or an I / O card can be directly connected to the microprocessor, so that the microprocessors constituting various portable information devices can be used more easily.

[0007]

FIG. 1 is a block diagram showing one embodiment of a bus state controller mounted on a microprocessor according to the present invention. Each circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique together with other circuit blocks constituting a microprocessor.

The bus state controller BSC divides a physical address space, outputs control signals according to various memory and bus state interface specifications, and the like. With the function of the bus state controller BSC, DRAM, SDRAM, PSR
AM, SRAM, ROM, etc. can be directly connected. Here, the DRAM is a dynamic RAM (random access memory), the SDRAM is a synchronous dynamic RAM, the PSRAM is a pseudo static RAM, the SRAM is a static RAM, and the ROM is read only.・ It is a memory.

In the present invention, a PCMCIA interface is mounted on the bus state controller BSC as described above. As a result, the IC memory card and the I / O card can be directly connected to each other, so that the system design of various information devices using a microprocessor is facilitated, and at the same time, high-speed data transfer is performed by a compact system. It is convenient for small portable information devices.

[0010] The wait control unit can be inserted a wait state by a WAIT terminal. The insertion of such a wait state can be controlled by a program, and the wait insertion of a state composed of 1 to 10 is designated in all the areas 0 to 6 by setting a register. However, areas 1 to 3 are common. In addition, a function is provided for automatically inserting wait weights in order to avoid data bus collision such as continuous memory access to different areas and write access immediately after read access to the same area.

The physical address space is divided into seven parts and managed by the area control unit. The area is made up of 0 to 6, and each area has a maximum of 64 Mbytes. The bus width of each area can be set by a register. However, only area 0 is set by an external pin.

In the memory control section, the physical address space is divided into seven areas as described above, and the type of memory that can be connected is specified for each area (physical address). And outputs a control signal that can be directly connected to the memory.

The DRAM direct connection interface is DRA
Row address / column address multiplex according to M capacity, burst operation (high-speed page mode, hyper page mode), CAS-before-RAS refresh and self-refresh, 4-bit CAS byte control corresponding to low power consumption, DRAM direct control signal Has various functions of controlling the timing of the register by setting a register.

The SDRAM direct connection interface is SD
It has various functions of controlling the row address / column address multiplex according to the RAM capacity, burst operation, auto refresh and self refresh, and the timing of the SDRAM direct connection control signal by setting a register.

The PSRAM direct connection interface has a burst operation (static column mode), an auto refresh function and a self refresh function.

The ROM burst interface allows the insertion of wait states to be controlled by a program, and has a burst transfer operation the number of times set by a register.

The PCMCIA direct connection interface has a wait state insertion controllable by a program, and has a burst operation (page mode) for high-speed data transfer and a bus sizing function of an I / O bus width. .

The refresh control unit supports the refresh operation immediately after the end of the self-refresh in the low power DRAM by the overflow interrupt function of the refresh counter, enables the refresh counter to be used as an interval timer, and generates an interrupt request upon a compare match. And an interrupt request is generated when the refresh counter overflows.

Register WC corresponding to weight control unit
R1 and R2 are wait control registers. The register BCR1 corresponding to the area control unit is a bus control register. This register BCR1 stores B
It is also used for the memory control unit together with CR2. Other registers MCR corresponding to the memory control unit are memory control registers, DCR is a DRAM control register, and PCR is a PCMCIA control register. Register RFCR corresponding to refresh control unit
Is a refresh count register, RTCNT is a refresh timer count register, RTCOR is a refresh time constant register, and RTCSR is a refresh timer control / status register.

Each register provided in the bus state controller BSC is connected to a module bus, and the module bus is connected to an internal bus via a bus interface. The internal bus is a central processing unit CP
U and other peripheral circuits are connected. Then, the address control section outputs an address signal including A0 to A25. The address control unit includes the ROM and PCMCI.
An address generation circuit (address counter) for realizing the burst operation of A is provided.

FIG. 2 is a partial terminal configuration diagram for explaining the bus state controller BSC, and FIG. 3 is a partial remaining terminal configuration diagram. In these terminal configuration diagrams, terminal names and signal names, input / output, and functions are shown.

In the microprocessor of this embodiment, both the logical space and the physical space have a 32-bit address space as an architecture. The logical space is divided into five spaces according to the value of the upper address. The physical space is divided into eight spaces. Of the eight spaces, one is a built-in IO area and a reserved area, and the remaining seven spaces used for external memory access are as described above. The logical space can be allocated to an arbitrary physical space by a built-in address translation mechanism (MMU).

FIG. 4 is an address space diagram for explaining the allocation of the physical space. The physical address is divided into eight as described above.
Six seven spaces are used. Area 0 is a normal memory or burst ROM, area 1 is a normal memory, area 2 is a normal memory or SDRAM, DRAM, area 3
Is normal memory or SDRAM, DRAM, PSRAM
However, the area 4 is usually allocated with a memory.
Areas 5 and 6 are respectively assigned a normal memory, a burst RAM, or a PCMCIA.

The bus size of the memory can be set for each space. In area 0, the bus size is changed to byte (8 bits), word (16 bits),
It can be selected from long words (32 bits). Area 1
In the case of using any one of the normal memory, ROM, and burst ROM, the bus control register B
The bus width can be selected from byte, word or longword by CR2.
When any of the SRAMs is used, the bus width can be selected from a word or a long word by using the individual memory control register MCR1. Area 2 DR
When used as an AM area, the bus width of areas 2 and 3 is word. And areas 5 and 6 are PCM
When used as a CIA interface, the bus width is set to either bytes or words.

When the use of the PCMCIA-compliant interface is supported in such areas 5 and 6, the IC memory card interface and the I / O card interface defined by the PCMCIA specification version (ver) 4.2 are basically used. In addition, in order to improve usability, in other words, an IC memory card or an I / O
In order to enable high-speed access to the card, such a specification is extended and a burst access function is added. That is, continuous access is enabled as in the page mode in the ROM. For such continuous access, an address generation function for continuous access is added to the address control unit.

The PCMCIA interface of this embodiment is defined by the PCMCIA specification version 4.1 and has the above-mentioned burst access function in addition to random access. The data bus width can be specified as byte (8 bits) / word (16 bits) as described above. Memory types include mask ROM, OTPR
OM, EPROM, EEPROM, flash memory and SRAM. The memory capacity is a maximum of 32 Mbytes, and an attached memory (REG function) for holding card attributes is provided.

An address conversion function M as will be described later
By using the MU, the address of the PCMCIA interface assigned to the area 5 or 6 is converted, and the access can be made in an arbitrary logical address space. The PCMCIA space allocation is as shown in Table 1.

[0028]

That is, the area 5 is the physical address A2
Areas 8 to 26 are 101, and address A31 to A31
A29 is ignored and the address range is H'140000
00 + H'20000000 * n ~ H'17FFFFF
F + H'20000000 * n (n = 0 to 7, n = 1 to 1)
7 is a shadow space (64 MB). When using the PCMA interface, only the IC memory card interface is used, and the address range is H'140000.
00 + H'2000000-H'15FFFFFF +
32 MB of H'20000000 * n (n = 0 to 7, n = 1 to 7 is a shadow space).

As for the bus width, either a byte or a word is selected from the bus control register BCR2 as described above. When the PCMCIA interface is connected, the CE1 and CE2 signals, the OE signal, and the WE signal are valid. In the bus cycle, the number of waits can be selected from 0 to 10 by the wait control register WCR2. When the burst function is used, the number of bus cycle pitches of the burst cycle is 2 in accordance with the number of waits.
It is determined in the range of 10 to 10.

Area 6 includes physical addresses A28 to A26.
Is the area 101, the addresses A31 to A29 are ignored, and the address range is H'14000000 +
H'20000000 * n-H'17FFFFFF +
H'20000000 * n (n = 0 to 7, n = 1 to 7 is a shadow space) is 64 MB. When using the PCMA interface, the IC memory card interface is used, and the address range is H'14000000 +
H'20000000-H'15FFFFFF + H'20
0000- * n (n = 0-7, n = 1-7 is shadow space) 32MB, I / O card interface,
The address range is H'1600000 + H'20000
00 ~ H'17FFFFFF + H'20000000 *
32M of n (n = 0 to 7, n = 1 to 7 is a shadow space)
B.

As for the bus width, either a byte or a word is selected from the bus control register BCR2 as described above. When the PCMCIA interface is connected, CE1, CE2 signals, OE signals, WE, IOR
D and IOWR are valid. In the bus cycle, the number of waits can be selected from 0 to 10 by the wait control register WCR2. When the burst function is used, the bus cycle pitch number of the burst cycle is determined in the range of 2 to 10 corresponding to the number of waits.

In the burst mode, a 16-byte access at the time of a cache file is accessed in a burst mode similar to the page mode of the ROM. That is, the number of data transfers in the burst transfer is determined by the bus control register B
It can be set by CR1, 4, 8, and 16 times. The first access cycle at the time of reading in burst transfer is data including data for which an internal request has occurred. The remaining access is to wrap around 16-byte boundary data including the data. At the time of writing in the burst transfer, writing is performed sequentially since the capital is changed according to 16-byte boundary data. The insertion of the wait state at the time of the head access and the second and subsequent accesses can be set by the wait control register WCR2.

FIG. 5 is a block diagram showing an embodiment of a microprocessor (single-chip microcomputer) according to the present invention. In the figure, the main circuits are illustrated as representatives, and each block is drawn according to the geometrical arrangement on the actual semiconductor substrate.

The CPU is a central processing unit. Cache
Is a cache memory, and the arithmetic unit performs arithmetic and logical operations. The multiplier performs multiplication. INTC is an interrupt control circuit. The MMU is a memory management unit that converts between a logical address and a physical address. DMAC is a direct memory access control circuit, D / A converter is a digital / analog converter, and A / D converter
Is an analog / digital converter. SCI is a serial communication interface. Timer
Is a timer circuit. CPG is a clock pulse generating circuit for supplying clock pulses necessary for the operation to each circuit block via a driver. The bus controller corresponds to the bus state controller BSC according to the present invention.
In addition to the above, various peripheral modules are provided as needed.

In the microprocessor of this embodiment, since the memory management unit is built in as described above,
The above physical address can be converted to a logical address for access. Therefore, the user can access various memories by an arbitrary logical address without being bound by the physical address.
Combined with the CMCIA interface, the usability is improved. In particular, in the PCMCIA interface of this embodiment, since the IC memory card and the I / O card are separated by the physical address space, the mode setting for the IC memory card or the I / O card as in a conventional dedicated chip is made. Can be eliminated, thus improving usability.

FIG. 6 shows an application example using a computer system using a microprocessor according to the present invention. FIG. 7A shows an IC card slot MSL.
A notebook type personal computer having an OT and a built-in file “File” constituted by the IC memory card or the I / O card, and having a keyboard KB and a display DP as input / output devices.

FIG. 1B shows a system in which a floppy disk drive FDD and a file Ffile constituted by the above-mentioned IC memory card or I / O card are built. Then, the input / output device is a keyboard KB and a display DP, and the floppy disk FD is inserted into the floppy disk drive FDD. As a result, the floppy disk FD as software and the file Ffil as hardware
e becomes a desktop type personal computer that can store information.

FIG. 3C shows the IC memory card or I
File card FileCARD as / O card
Is a pen portable type personal computer in which an input / output device is an input-only pen PEN and a display DP. Thus, by mounting the PCMCIA interface according to the present invention on a microprocessor,
The portable computer system as described above can be simplified. This makes it possible to reduce the size of the entire system,
Lighter and thinner, power consumption can be reduced,
Further, by adding a burst function, a large amount of information can be read and written at a high speed, so that the processing capability of the entire computer system can be improved.

The functions and effects obtained from the above embodiment are as follows. (1) A PCMCIA interface is mounted on a bus state controller that divides a physical address space in a microprocessor and outputs control signals in accordance with various memory and bus interface specifications. Since the / O card can be directly connected, the effect that the usability of the microprocessors constituting various portable information devices can be improved is obtained.

(2) In the PCMCIA interface, a memory card interface and an I / O
Separating the card interface from the card interface by the physical address space makes it unnecessary to set the mode one by one, so that the effect of improving the usability can be obtained.

(3) By providing the PCMCIA interface with an address generating circuit for burst access, an effect is obtained that an IC memory card or an I / O card can be accessed at a high speed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the functions mounted on the microprocessor can adopt various embodiments other than the example of FIG. Further, in the bus state controller, other interfaces than the PCMCIA interface can be configured by various combinations. The present invention can be widely used for various microprocessors, interface units, interface methods, and data movement methods.

[0044]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a PCMCIA interface is mounted on a bus state controller that divides a physical address space in a microprocessor and outputs control signals according to various memory and bus interface specifications, so that an IC memory card or an I / O card is mounted on the microprocessor. Can be directly connected,
The usability of the microprocessor constituting various portable information devices can be improved.

In the PCMCIA interface, since the memory card interface and the I / O card interface are separated by the physical address space, it is not necessary to set the mode one by one as in the prior art, so that the usability can be improved.

The PCMCIA interface can access an IC memory card or an I / O card at high speed by providing an address generating circuit for burst access.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a bus state controller mounted on a microprocessor according to the present invention.

FIG. 2 is a partial terminal configuration diagram for explaining the bus state controller BSC.

FIG. 3 is a terminal configuration diagram of the remaining part for describing the bus state controller BSC.

FIG. 4 shows a microprocessor according to the present invention.
FIG. 3 is an address space diagram for explaining allocation of a physical space.

FIG. 5 is a block diagram showing an embodiment of a microprocessor (single-chip microcomputer) according to the present invention.

FIG. 6 is a configuration diagram showing an application example using a computer system using a microprocessor according to the present invention.

[Explanation of symbols]

BSC: bus state controller, WCR1, 2 ... wait control register, BCR1, 2 ... bus control register, MCR: memory control register, DCR: DRAM control register, PCR ...
PCMCIA control register, RFCR: refresh count register, RTCNT: refresh timer count register, RTCOR: refresh time constant register, RTCSR: refresh timer control / status register, CPU: central processing unit, Cache: cache memory, INTC ...
Interrupt control circuit, MMU: memory management unit, DM
AC: direct memory access control circuit, D / A converter
… Digital / analog converter, A / D converter… Analog / digital converter, SCI… Serial communication interface, Timer… Timer circuit,
CPG: Clock pulse generation circuit, Driver: Driver, MSLOT: IC card slot, File: File, KB: Keyboard, DP: Display, FD
D: floppy (registered trademark) disk drive FDD,
PEN: Pen.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Susumu Narita Inventor, Central Research Laboratory, Hitachi, Ltd. 1-280, Higashi Koikekubo, Kokubunji-shi, Tokyo (72) Inventor Masato Nemoto 3-2-1, Sachimachi, Hitachi City, Hitachi, Hitachi, Hitachi, Japan Engineering Co., Ltd. F term (reference) 5B014 GE07 HB02 HB21 HB26 5B062 EE09 HH01 5B065 BA09 CC01

Claims (15)

[Claims] 1. A microprocessor having a system clock, comprising: an interface unit, an address access unit, a PC card control means, and an external clock means, wherein the interface unit has a memory and a PC card for the microprocessor. The address access unit corresponds to a system clock that transitions from a first state to a second state in order to access an external address space, and the PC card control means controls an address signal. A setup time and a setup data of a PC card including a hold time for holding an address signal are stored. The external clock means is connected to a memory and used by a synchronous dynamic random access memory. Microprocessor, characterized in that the system clock is also connected. 2. The microprocessor according to claim 1, further comprising a clock generation unit connected to the interface unit and generating a system clock. 3. An integrated microprocessor having a clock generator, a first external terminal, a second external terminal, and a controller, wherein the clock generator generates a system clock signal, The system clock signal periodically changes between a first state and a second state, wherein the second state is different from the first state, wherein the first external terminal receives the system clock signal, and wherein the system clock signal is Output to the outside of the microprocessor, the system clock signal is used as an operation clock of the synchronous dynamic random access memory, the second external terminal receives a clock enable signal, and the clock enable signal is Synchronous
Supplied to a dynamic random access memory, the controller receives the system clock signal, the controller is connected to the second external terminal, the address generation circuit, a first control register, a timing signal generation circuit, And a refresh circuit, wherein the address generation circuit generates an address signal for accessing an external address space according to a change of a system clock signal from a first state to a second state, and the first control register First data and second data are stored. The first data corresponds to a setup time for preparing a start control signal for a PC card for generating an address signal, and the second data is a start control for the PC card. The hold time for holding the address signal that matches the signal, A timing signal generation circuit for generating a start signal including a start control signal for a PC card according to the first data and the second data; The microprocessor controls a refresh operation for the synchronous dynamic random access memory. 4. The microprocessor according to claim 3, wherein the timing signal generation circuit is connected to a second external terminal. 5. The clock enable signal according to claim 4, wherein the clock enable signal has a first state and a second state, and the clock enable signal has a first state and a second state when the synchronous dynamic random access memory is refreshed. A microprocessor characterized by a transition to. 6. The system according to claim 3, further comprising a second control register and a control signal generation circuit, wherein the second control register is assigned to each of the synchronous dynamic random access memory and the PC card. Storing the attribute data for determining the attribute of the external address space, wherein the control signal generation circuit is connected to a second control register,
A microprocessor which generates a card enable signal in accordance with a chip select signal or an address signal for the synchronous dynamic random access memory. 7. An interface unit for use in an integrated microprocessor, the interface unit comprising:
A first terminal for receiving a system clock signal and outputting a memory clock signal to the outside of the microprocessor, wherein the memory clock signal is a synchronous dynamic random access memory; Output to an access memory, wherein the second terminal receives a clock enable signal, wherein the clock enable signal is for controlling the synchronous dynamic random access memory; A controller for receiving a signal, wherein the controller is connected to the second terminal, the controller includes an address generation circuit, a first control register, a timing generation circuit, and a refresh control circuit; Is the system clock signal An address signal for accessing the external address space is generated as the state changes from the first state to the second state. The first control register stores the first data and the second data.
The first data corresponds to a setup time for preparing a start control signal for the PC card for generating an address signal, and the second data is for holding an address signal that matches the start control signal for the PC card. The timing signal generation circuit is connected to a first control register, and the timing signal generation circuit generates a control signal including a start control signal for a PC card according to first and second data. The refresh control circuit controls a refresh operation on the synchronous dynamic random access memory. 8. The device according to claim 7, wherein the clock enable signal has first and second states, and the clock enable signal is changed from a first state to a second state when the synchronous dynamic random access memory is refreshed. An interface unit characterized by changing to. 9. A method for interfacing a microprocessor integrated with a plurality of external devices, comprising: generating a system clock for the microprocessor; and using a system clock external to the microprocessor for use by an external memory. And generates a first address for accessing a first external address space corresponding to the first external device other than the external memory, and includes control information for the first external device including information on a setup time and a hold time. And according to the control information and according to the system clock, the first
An interface method comprising the steps of generating a control signal for controlling an external device. 10. The interface method according to claim 9, wherein the external memory is a synchronous dynamic random access memory. 11. The interface method according to claim 10, wherein the first external device is a PC card. 12. The interface method according to claim 11, further comprising a step of supplying a refresh control signal to the synchronous dynamic random access memory. 13. The PC card according to claim 10, wherein the PC card and the synchronous dynamic random access memory are both connected to the microprocessor, and wherein the control signal generating step for controlling the first external device is performed by the PC.
An interface method comprising the steps of controlling a clock enable signal and a write enable signal according to a system clock according to an operation of a card, and controlling generation of an address signal according to an operation of the PC card. 14. A method for data movement in an integrated microprocessor, the integrated microprocessor including a microprocessor communicating with an external device, and a system clock for the microprocessor. One external device is a synchronous memory, one external device supplies a system clock to at least two external devices that are PC cards, and a first address is a first address corresponding to the PC card. The PC which generates a first address for accessing an external address space and includes information on a setup time and a hold time
A data movement method, comprising: storing control information to a card; generating a control signal for controlling the PC card according to a system clock according to the control information; and performing a refresh cycle on the synchronous memory. 15. The data movement method according to claim 14, wherein said synchronous memory is a synchronous dynamic random access memory.