CN214253209U - IP core of user interface module of SDRAM controller - Google Patents

Abstract

The utility model discloses a SDRAM controller user interface module IP is nuclear, including multiport user interface module, MIG _ v2.3IP nuclear and DDRx SDRAM memory group unit, accomplish automatic refresh through MIG _ v2.3IP nuclear control DDRx SDRAM memory group unit, precharge, burst write, burst read, further encapsulate into two independent operation ports MIG _ v2.3IP nuclear application interface through multiport user interface module, provide independent read-write operation to the user with the form similar to FIFO respectively. The utility model overcomes SDRAM controller control logic is complicated, the use degree of difficulty is big, the poor scheduling problem of application flexibility, has guaranteed the high reliability of performance simultaneously to shorten the design time of product greatly, richened SDRAM's application scenario.

Description

IP core of user interface module of SDRAM controller

Technical Field

The utility model relates to an electronic information technical field especially relates to a SDRAM controller user interface module IP core.

Background

With the high-speed development of modern science and technology, in the fields of high-speed data acquisition, high-speed image processing and the like, the processing requirements of high speed, large capacity, strong real-time performance and high bandwidth generally exist for data caching. The fourth generation SDRAM has been developed so far, and becomes the preferred scheme of the cache memory by virtue of the advantages of low price, high density, fast data read-write speed, etc. However, compared with other memory devices such as SRAM and FIFO, SDRAM requires a series of operations such as timing refresh, precharge and row and column addressing, so that its control logic is complex and the requirement for timing is strict. The scheme of adopting the special chip not only makes the hardware circuit become complicated, increases the design cost, but also mostly can not be flexibly customized for specific occasions, and is not beneficial to the special application of the SDRAM. Therefore, it is necessary to design an SDRAM controller with simple interface, flexible use and reliable performance. Therefore the utility model provides a SDRAM controller user interface module IP core solves above-mentioned problem.

SUMMERY OF THE UTILITY MODEL

The utility model provides a SDRAM controller user interface module IP nuclear has overcome SDRAM controller control logic complicacy, has used the degree of difficulty big, uses the poor scheduling problem of flexibility.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

an SDRAM controller user interface module IP core comprises a multi-port user interface module, an MIG _ v2.3IP core and a DDRx SDRAM memory group unit, wherein the MIG _ v2.3IP core controls the DDRx SDRAM memory group unit to complete automatic Refresh (Auto Refresh), pre-charge (Precharge), Burst Write (Burst Write) and Burst Read (Burst Read), an application interface of the MIG _ v2.3IP core is further packaged into two independent operation ports through the multi-port user interface module, and independent Read-Write operation is provided for a user in a form similar to FIFO respectively.

Preferably, the DDRx SDRAM bank units include DDR2, DDR3, LPDDR 2.

Preferably, the MIG _ v2.3IP core converts the complicated read-write time sequence of the DDRx SDRAM into the simple read-write time sequence of the user, and converts the double-clock edge data of the DDRx SDRAM interface into the single-clock edge data of the user, so that the user controls the DDRx SDRAM like operating a common SRAM.

Preferably, the multi-port user interface module comprises a parameter configuration unit, two port write data cache units, two port read data cache units and a multi-port read-write arbitration unit, wherein the multi-port read-write arbitration unit adopts a mechanism of taking command control right in turn, processes read operation or write operation from two ports in a time-sharing manner, converts the read operation or write operation into a corresponding read-write command, sends the read-write command to the MIG _ v2.3IP core, and completes user data exchange at the same time.

Preferably, the two port write data buffer units have the same function, the two port read data buffer units have the same function, and the independently operating operation interfaces respectively comprise a write data buffer unit and a read data buffer unit to complete the writing and reading of the user data.

Compared with the prior art, the beneficial effects of the utility model are that: the utility model discloses the inside memory controller IP core MIG _ v2.3 of Xilinx 7 series device has been combined ingeniously, but has designed a parameterization multiport access's user interface. The SDRAM controller not only flexibly supports common SDRAMs such as DDR2, DDR3 and LPDDR2, but also provides a read-write operation port similar to FIFO, supports two ports to independently read and write data of a memory at the same time, well overcomes the problems of complex control logic, high use difficulty, poor application flexibility and the like of the SDRAM controller, and simultaneously ensures high reliability of performance, thereby greatly shortening the design time of products and enriching the application occasions of the SDRAM. The utility model discloses be applied to in the product design, compare the mode that adopts special chip, every product can reduce 12% PCB area, has reduced 15% total consumption, has practiced thrift 20% product development time. Meanwhile, the IP core has strong portability and high universality, can be compatible with most mainstream SDRAM in the market, simplifies the hardware design of products, and improves the miniaturization degree, stability and reliability of the products.

Drawings

Fig. 1 is a schematic block diagram of an IP core of a user interface module of an SDRAM controller according to the present invention.

Fig. 2 is a schematic block diagram of a multi-port user interface module of an SDRAM controller user interface module IP core according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.

Referring to fig. 1, the SDRAM controller user interface module IP core provided by the present invention includes a multi-port user interface module, an MIG _ v2.3IP core, and a DDRx SDRAM memory bank unit, where the DDRx SDRAM memory bank unit includes DDR2, DDR3, and LPDDR2, the DDRx SDRAM memory bank unit is controlled by the MIG _ v2.3IP core to complete automatic refresh, precharge, burst write, and burst read, an application interface of the MIG _ v2.3IP core is further encapsulated into two independent operation ports by the multi-port user interface module, and independent read and write operations are provided to a user in a form similar to FIFO, respectively.

In this embodiment, the MIG _ v2.3IP core has the main functions of completing initialization of the DDRx SDRAM, converting a complex read-write timing sequence of the DDRx SDRAM into a simple read-write timing sequence of a user, and converting double-clock-edge data of the DDRx SDRAM interface into single-clock-edge data of the user, so that the user controls the DDRx SDRAM like operating a normal SRAM. Meanwhile, the IP core also generates a periodic refresh command to maintain the data of the DDRx SDRAM.

Referring to fig. 2, in this embodiment, the multi-port user interface module mainly includes a parameter configuration unit, a port 1 write data cache unit, a port 1 read data cache unit, a port 2 write data cache unit, a port 2 read data cache unit, and a multi-port read-write arbitration unit, where the port 1 and the port 2 are two operation interfaces with the same function and running independently, and each operation interface includes a write data cache unit and a read data cache unit, so as to complete writing and reading of user data. The multi-port read-write arbitration unit adopts a mechanism of taking command control right in turn, processes read operation or write operation from two ports in a time-sharing way, converts the read operation or the write operation into a corresponding read-write command and sends the read-write command to the MIG _ v2.3IP core, and completes the exchange of user data at the same time.

(1) Parameter configuration unit

The unit can independently configure the bit width of the user data of the two ports, the burst length of read-write operation, the initial address and the space size of the memory allocation of each port and other parameters.

(2) Port 1 write data buffer unit

The function of this unit is to buffer the user data written from port 1, then to follow 1: 4, and finally reading the data bit width under the control of a multi-port read-write arbitration unit and sending the data bit width to an MIG _ v2.3IP core.

(3) Port 1 read data buffer unit

The function of this unit is to buffer the user data read from the DDRx SDRAM memory chip under the control of the multi-port read-write arbitration unit, then according to 4: the bit width conversion of the data is carried out according to the proportion of 1, and finally the data is provided for a user interface of the port 1 to read.

(4) Port 2 write data buffer unit

The function of this unit is to buffer the user data written from port 2, then to follow 1: 4, and finally reading the data bit width under the control of a multi-port read-write arbitration unit and sending the data bit width to an MIG _ v2.3IP core.

(5) Port 2 read data buffer unit

The function of this unit is to buffer the user data read from the DDRx SDRAM memory chip under the control of the multi-port read-write arbitration unit, then according to 4: the bit width conversion of the data is carried out according to the proportion of 1, and finally the data is provided for a user interface of a port 2 to read.

(6) Multi-port read-write arbitration unit

The function of the unit is to adopt an operation mechanism which takes command control right in turn to process 4 transactions of port 1 read operation, port 1 write operation, port 2 read operation and port 2 write operation in a time-sharing way. The method comprises the following steps: an operation mark symbol containing 4 kinds of numerical values is defined, and the operation mark symbol respectively represents the 4 kinds of operation transactions. Then, an arbitration state machine is designed to define 7 states of idle, port 1 read command, port 1 write command, port 2 read command, port 2 write command, port 1 operation completion and port 2 operation completion. In idle state, the operation mark symbol continuously updates the value, and the command control right of MIG _ v2.3IP core is circularly circulated in the 4 transactions. When a certain transaction obtains the control right and meets the condition of triggering transaction operation, the arbitration state machine jumps to a corresponding state to finish reading the data with the specified length from the DDRx SDRAM memory chip or writing the data with the specified length into the DDRx SDRAM memory chip. After the process is completed, the arbitration state machine returns to the idle state, the operation mark symbol is continuously updated, and the next trigger is waited for, and the processes are circulated in sequence.

The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.

Claims (4)

1. The utility model provides a SDRAM controller user interface module IP core, includes multiport user interface module, MIG _ v2.3IP core and DDRx SDRAM memory bank unit, its characterized in that, DDRx SDRAM memory bank unit includes DDR2, DDR3, LPDDR2, accomplishes automatic refresh, precharge, burst write, burst read through MIG _ v2.3IP core control DDRx SDRAM memory bank unit, further encapsulates into two independent operation ports through multiport user interface module MIG _ v2.3IP core's application interface, provides independent read-write operation to the user with the form similar to FIFO respectively.

2. An IP core of a user interface module of an SDRAM controller according to claim 1, wherein the MIG _ v2.3IP core converts a complicated read-write timing of the DDRx SDRAM into a simple read-write timing of a user and converts a double clock edge data of the DDRx SDRAM interface into a single clock edge data of the user, so that the user controls the DDRx SDRAM like operating a general SRAM.

3. The IP core of the SDRAM controller user interface module according to claim 1, wherein the multi-port user interface module comprises a parameter configuration unit, two port write data buffer units, two port read data buffer units and a multi-port read-write arbitration unit, the multi-port read-write arbitration unit uses a mechanism for taking command control right in turn to process read operation or write operation from two ports in a time-sharing manner, then converts the read operation or write operation into a corresponding read-write command and sends the read-write command to the MIG _ v2.3IP core, and completes user data exchange.

4. An IP core of SDRAM controller user interface module according to claim 3, wherein the two port write data buffer units have the same function, the two port read data buffer units have the same function, and the independently operating operation interfaces respectively comprise a write data buffer unit and a read data buffer unit to complete the writing and reading of user data.

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