CN101221532B

CN101221532B - Interface method for implementing dynamic RAM with data processing capability

Info

Publication number: CN101221532B
Application number: CN2008100467263A
Authority: CN
Inventors: 戴葵
Original assignee: Individual
Current assignee: Individual
Priority date: 2008-01-21
Filing date: 2008-01-21
Publication date: 2010-06-09
Anticipated expiration: 2028-01-21
Also published as: CN101221532A

Abstract

The invention relates to an interface method for realizing a dynamic RAM (DRAM) provided with data processing capacity, which is used for information transfer between a master processor and the DRAM provided with data processing capacity. The invention comprises control of internal processing units and access of internal memory units, and all accesses adopt a standard DRAM interface protocol and are performed through a standard DRAM interface. The DRAM provided with data processing capacity can be applied in various data processing systems under the condition of no modification performed on any hardware through the interface; the DRAM not only can be taken as a conventional memory to provide memory power of programs and data but also can provide the capacity for processing data in the memory so as to improve performance of the data processing systems.

Description

Realization has the interface method of the dynamic RAM of data-handling capacity

Technical field

Patent of the present invention relates to the memory interface method of data handling system, relates in particular to the interface method that realization has the dynamic RAM (DRAM) of data-handling capacity.

Background technology

In the past few decades, performance of processors promotes with the surprising speed of doubling in per 18 months according to Moore's Law always.This all has benefited from the huge raising of integrated circuit fabrication process and architecture technology.But people have also come to realise increasing factor and hamper performance of processors and further promote.Wherein " storage wall " is exactly insoluble problem in existing Feng's Von Neumann architecture.During former design was produced, processor and storer all were independent design and optimizations.The manufacturing process of processor is that logic is a target to produce fast; And the manufacturing process of DRAM memory is to be purpose to obtain storage density.Therefore adopt different manufacture methods to obtain processor and inexpensive high-density storage fast.But this method also produces a very serious negative effect, and that is exactly because processor performance is at a high speed shielded by at a slow speed DRAM main memory, thereby does not reach its performance boost desired to total system.

At storage wall problem, be that people use the level storage system under the framework at center with the processor in tradition, and adopted a large amount of methods to reduce or the access delay of concealing memory.These technology comprise that improving high-capacity cache memory (Cache), software and hardware looks ahead, infers and carry out and multithreading etc.But these methods are also inevitable must introduce more restriction.As the access delay of storer under the meeting increase failure conditions, the some of them technology also more is subjected to the restriction of bandwidth of memory.

In order can to start with from architecture from solving the problem of storage wall in essence.Existing a solution is exactly PIM (Processor In Memory) architecture.It is the progress along with technology, and processor and DRAM storer can integrate and produce.Thereby avoided the storage wall performance bottleneck of traditional Feng's Neumann structure.The PIM technology directly is integrated into logical device in the storer, has characteristics such as low delay, high bandwidth and low-power consumption, and use PIM technology can be from alleviating storage wall problem in essence.In more than ten years in the past, the whole world has many universities or research institution hand starting to study this technology, comprise ActivePage, IRAM, HTMT, DIVA, FlexRAM, Blue GeneBG/C, Pim-Lite and Gilgamesh etc.Can be divided into two classes according to these PIM chips role in computer system.One class is processor chips, and method is that handle is with high capacity DRAM and the status that suitable processor is integrated into a chip and serves as processor.Another kind of is the storage chip of band computing power, and it is that the PIM chip is replaced original memory chip, thus for the original computer system provides stronger computing power, as IRAM, FlexRAM.Yet these memory chips all can not effectively not be integrated in the existing data processing system owing to satisfy the sequential agreement of existing storer.

In sum, the DRAM storage arrangement with data-handling capacity is badly in need of a kind of system architecture of being integrated into the interface method in the available data disposal system and matching of being easy to.By adopting sequential agreement and the interface identical with existing storer, the DRAM storage arrangement that will have data-handling capacity is applied in the available data disposal system, to improve the data-handling capacity of available data disposal system.

Summary of the invention

Purpose of the present invention provides a kind of DRAM interface method of realizing having data-handling capacity.This method adopts the sequential agreement identical with having storer now, provides to the control of inner data processing unit with to the visit of internal storage.By this interface method and structure, can be under the situation of changing without any hardware, the DRAM storer that effectively will have data-handling capacity is integrated in the available data disposal system.

Purpose of the present invention is achieved through the following technical solutions:

Design a kind of DRAM interface method of realizing having data-handling capacity, relate to corresponding application interface (API) function, system software method for supporting and interface sequence.DRAM device inside with data-handling capacity has internal storage and internal data processing unit, the program and the data of internal storage storage data handling system, the internal data processing unit is in the processing of memory inside realization to the storage data, to solve the problem of " storage wall ".Main Processor Unit in the data handling system by general access instruction, is the internal storage physical address corresponding by the Storage Mapping module in the system software with access map when internal storage is conducted interviews; Main Processor Unit in the data handling system calls corresponding api function when inner data processing unit is operated, be internal data processing unit physical address corresponding by the Storage Mapping module in the system software with access map.General DRAM memory interface is all passed through in these two kinds of different visits, sends to the DRAM storer with data-handling capacity with general DRAM memory access sequential.

Design the system architecture that a kind of DRAM interface method of realizing having data-handling capacity matches, in DRAM memory inside interface module is set above-mentioned two kinds of different visits are handled with data-handling capacity.Interface module is distinguished this two kinds of visits by address wire, if visit to internal storage, directly interrogation signal is connected to the internal storage interface, and some bit address lines are deciphered obtains chip selection signal, respond this visit to select corresponding internal storage unit; If to the visit of inner data processing unit, by the sequential converting unit, the DRAM accessing time sequence is converted to the SRAM accessing time sequence, the control register of inner data processing unit is conducted interviews.

Realization has dynamic RAM (DRAM) interface method of data-handling capacity, comprise and adopt of the visit of different flow processing internal storage unit and internal data processing unit, adopt the interface sequence of general-purpose storage that the DRAM storer with data-handling capacity is operated, by the visit of internal interface unit differentiation to internal storage unit and internal data processing unit, and finish corresponding sequential conversion, it is characterized in that:

Described interface method is by the visit of general access instruction realization to internal storage unit, and idiographic flow is:

The program of A, data handling system is sent visit to internal storage by general access instruction;

The system software address mapping module of B, data handling system is the respective physical space with DRAM storage address of data-handling capacity with the map addresses in the general access instruction;

C, data handling system are sent the signal of conformance with standard DRAM memory interface sequential by standard DRAM memory interface, and the DRAM storer with data-handling capacity is conducted interviews;

Described interface method is by the visit of API realization to inner data processing unit, and idiographic flow is:

The program of A, data handling system is sent visit to inner processing unit by calling API;

The system software address mapping module of B, data handling system is the respective physical space with DRAM storage address of data-handling capacity with the map addresses among the API;

Described internal interface unit is distinguished to internal storage with to the visit of inner data processing unit by address signal;

Described internal interface unit will directly send to internal storage to the visit order of internal storage;

Described internal interface unit will be carried out the sequential conversion to the visit order of data processing unit, realize the visit to data processing unit control register.

Described data handling system Main Processor Unit and the passage with exchange message between the DRAM storage arrangement of data-handling capacity are flash memory (FLASH), static RAM (SRAM), synchronous DRAM (SDRAM), Double Data Rate synchronous DRAM (DDR), second generation Double Data Rate synchronous DRAM (DDR2), third generation Double Data Rate synchronous DRAM (DDR3), the sequential of special-purpose Double Data Rate synchronous DRAM (GDDR2) of second generation figure or special-purpose Double Data Rate synchronous DRAM (GDDR3) the interface standard regulation of third generation figure.

Described DRAM internal interface unit with data-handling capacity comprises state machine, sequential modular converter, refresh count module and decoding module, state machine links with sequential modular converter, refresh count module and decoding module respectively, switching between wherein state machine record current accessed state, and the realization different access state; The sequential modular converter is realized the conversion of general DRAM memory access sequential to SRAM memory access sequential, to realize the visit to inner data processing unit; The refresh count module is counted the refresh command that sends, and according to the numerical value of counting, selects different internal repository to refresh; Decoding module is deciphered some position of address, and selects corresponding internal repository to operate, to realize the visit to internal storage unit.

The present invention can be under the situation of not carrying out any hardware change by this interface, the DRAM storage arrangement that will have data-handling capacity is applied to various data handling systems, both can be used as normal memory the storage capacity of program and data was provided, can provide the ability that data in the storer are handled again, to improve the performance of data handling system.

Description of drawings

Fig. 1 is the DRAM architecture of memory device synoptic diagram with data-handling capacity;

Fig. 2 is the memory interface method operating process;

Fig. 3 is the memory interface structural representation.

Embodiment

Realization, the functional characteristics of the object of the invention will be in conjunction with the embodiments, are described further with reference to accompanying drawing.

There is the DRAM storage arrangement of data-handling capacity to divide in the described scheme from functional module, comprise memory interface, processing unit, processing unit control interface, communication network, inner DRAM storer, inner DRAM memory controller composition, its annexation as shown in Figure 1.In most preferred embodiment, we adopt standard second generation Double Data Rate dynamic RAM (DDR2) interface and standard, the embedded DRAM of integrated 4 each 64KByte sizes (eDRAM) on-chip memory and 4 processing units.But the present invention is not limited to adopt above-mentioned interface specification and configuration.

Described software interface method with DRAM of data-handling capacity, adopt different address spaces to divide to internal storage and inter-process unit, internal storage occupies low half part of address space, and inter-process unit controls register occupies height half part of address space.This interface method adopts different flow processs that internal storage and inter-process unit are conducted interviews, and concrete browsing process as shown in Figure 2.

Access method to internal storage is as follows:

A. program is sent visit to internal storage by general access instruction;

B. the system software address mapping module is low half segment space with DRAM storage address of data-handling capacity with the map addresses in the general access instruction;

C. by general DDR2 interface, send the signal that meets general DDR2 interface sequence, the DRAM storer with data-handling capacity is conducted interviews.

Access method to inner processing unit is as follows:

A. program is sent visit to inner processing unit by calling API;

B. the system software address mapping module is height half segment space with DRAM storage address of data-handling capacity with the map addresses among the API;

To the interrogation signal of internal storage and inter-process unit, send to DRAM storer according to general DDR2 interface sequence with data-handling capacity.This DRAM storer passes through memory interface, accept and resolve read-write and operational order by general DDR2 transmission specification definition, on the basis of the sequential operation that guarantees the transmission specification definition, provide primary processor to having data-handling capacity DRAM storage arrangement on-chip memory and the access path of data processing unit.Described memory interface is connected with chip pin, processing unit control interface and inner DRAM memory controller respectively, and distinguishes storage space by row address.If visit to processing unit, by memory interface the row, column address is spliced, and the accessing time sequence of general DRAM storage arrangement normalized definition is converted into the required SRAM in access process unit (static RAM) storer sequential, to realize the startup and the inquiry of processing unit.If visit to inner DRAM storer, select a certain inner DRAM storer by memory interface, and the operational order and the data of interface are directly delivered to this memory input, with realize to on-chip memory activation, preliminary filling, reading and writing, operation such as refresh.

Most preferred embodiment adopts general DDR2 standard as interface and transmission specification with DRAM storage arrangement of data-handling capacity.In other embodiments, also can adopt FLASH (flash memory), SRAM, SDRAM (synchronous DRAM), DDR (Double Data Rate synchronous DRAM), DDR3 (third generation Double Data Rate synchronous DRAM), GDDR2 (the special-purpose Double Data Rate synchronous DRAM of second generation figure), GDDR3 (the special-purpose Double Data Rate synchronous DRAM of third generation figure) general DRAM memory device interface and transmission specification.

Adopt the DRAM memory device interface signal with data-handling capacity of DDR2 standard and describe as shown in table 1.Memory interface one end connects interface signal as shown in table 1, and an end connects inner DRAM memory interface and processing unit control interface, and its concrete module map as shown in Figure 3.Data-signal Data among the figure comprises DQ, DQS, DM, and control signal Ctrl comprises CKE, ODT, CS#, RAS#, CAS#, WE#.

Table 1 DDR2 standard interface signal and description

Title	Direction	Describe
Title	Direction	Describe	CK, CK#	Input	Clock signal: CK and CK# are the clock signal of difference.The input data also are that the negative edge of CK# is sampled all at the rising edge of CK; Output data is all exported at the rising edge of CK and CK#.
CKE	Input	Clock enables: activate (for high) or close (for low) sheet internal clock circuit.	CK, CK#	Input
CKE	Input		ODT	Input	Terminal enables on the sheet: internal resistance is connected to pin DQ, DQS and DM when high.If EMR (1) register is programmed for calcellation ODT, then ignore this signal.

Title	Direction	Describe
Title	Direction	Describe	CS#	Input	Sheet choosing: enable (for low) or close (for high) storage arrangement.
RAS#, CAS#, WE#	Input	Order input: RAS#, the different input command of combination definition that CAS# is different with WE#.	CS#	Input
RAS#, CAS#, WE#	Input		DM	Input	Input data mask: to writing the signal that data shield.If the DM signal is high when write command, then shields this and write data, not with its write store.
BA0～BA2	Input	The body address: definition to which body is operated.	DM	Input
BA0～BA2	Input	The body address: definition to which body is operated.	A0～A15	Input	Address: row address is provided when activation command; When read write command, provide column address and preliminary filling control bit.A10 is as the preliminary filling control bit, if low, preliminary filling is by the body of BA0～BA2 definition; If high, all bodies of preliminary filling.
DQ	Two-way	Data input and output: two-way data bus.	A0～A15	Input
DQ	Two-way	Data input and output: two-way data bus.	DQS	Two-way	Data strobe pulse: when read data as output, when write data as input.Align with lower edge on the sense data, and write the data stage casing and align.
VDDQ	Power supply	The input of DQ power supply	DQS	Two-way
VDDQ	Power supply	The input of DQ power supply	VSSQ	Power supply	The input of DQ ground
VDLL	Power supply	The input of DLL power supply	VSSQ	Power supply	The input of DQ ground
VDLL	Power supply	The input of DLL power supply	VSSDL	Power supply	The input of DLL ground
VSS	Power supply	The power supply input	VSSDL	Power supply	The input of DLL ground
VSS	Power supply	The power supply input	VDD	Power supply	The ground input
VREF	Power supply	The reference power source input	VDD	Power supply	The ground input

Adopt the DRAM memory device interface protocol command truth table with data-handling capacity of DDR2 standard as shown in table 2.Memory interface is responsible for receiving and resolving various command as shown in table 2, is at inner DRAM storer or processing unit by state machine (State Machine) according to current order, the control store interface enters internal memory operations pattern or processing unit operation pattern, and current operator scheme is retained to always and receives the order that next changes current operator scheme.The Data of memory interface, Ctrl, address signal directly link to each other with inner DRAM memory interface, under the internal memory operations mode state, determine the value of CS0～CS3 by the current command, operate to select one or more internal storages.Because the processing unit interface adopts the SRAM interface, so under the processing unit operation pattern, realize the sequential conversion of DRAM to SRAM by sequential conversion (Timing Transfer) module.

Table 2 DDR2 standard agreement order truth table

Memory interface is as follows to the concrete processing of various memory access orders:

1. mode register is set: enter the internal memory operations pattern under the mode register command being provided with, by state machine (State Machine) control decoding unit (Decoder), with the whole gatings of CS0～CS3, be provided with the mode register of realization to all internal storages.

2. refresh: under refresh command, enter the internal memory operations pattern, by refresh counter (Refresh Counter) refresh command is carried out cycle count from 0～3, if the current i that count down to, gating CSi then is to realize the refresh operation to a certain internal storage.

3. enter self-refresh mode: enter the internal memory operations pattern under the self-refresh mode order entering, by state machine (State Machine) control decoding unit (Decoder), with the whole gatings of CS0～CS3, control all internal storages and enter self-refresh mode.

4. go out self-refresh mode: going out to enter the internal memory operations pattern under the self-refresh mode order,,, controlling all internal storages and withdraw from self-refresh mode with the whole gatings of CS0～CS3 by state machine (StateMachine) control decoding unit (Decoder).

5. preliminary filling monomer: under the order of preliminary filling monomer, enter the internal memory operations pattern,,, control all internal storages certain one is carried out preliminary filling with the whole gatings of CS0～CS3 by state machine (State Machine) control decoding unit (Decoder).

6. all bodies of preliminary filling: under all body orders of preliminary filling, enter the internal memory operations pattern,,, control all internal storages all bodies are carried out preliminary filling with the whole gatings of CS0～CS3 by state machine (StateMachine) control decoding unit (Decoder).

7. activate: determine that according to the value of row address A15 this activation manipulation is at internal storage or processing unit.If A15 is high, enter the processing unit operation pattern, sequential conversion (Timing Transfer) module is sent in row address and body address carry out buffer memory, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3; If A15 is low, enter the internal storage unit operator scheme, (Decoder) deciphers address signal A14, A13 by decoding unit, operates with one among gating CS0～CS3.

8. write: if current for the processing unit operation pattern, column address is sent into sequential conversion (Timing Transfer) module, with preceding when once activating row address, the body address of buffer memory splice, carry out corresponding sequential conversion simultaneously, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3, so that adopt the SRAM interface that processing unit is carried out write operation; If current be the on-chip memory operator scheme, and control decoding unit (Decoder) by state machine (State Machine), when keeping last activation manipulation among the CS0～CS3 of gating one is so that carry out write operation to a certain internal storage.

9. write the back preliminary filling: if current for the processing unit operation pattern, column address is sent into sequential conversion (Timing Transfer) module, with preceding when once activating row address, the body address of buffer memory splice, carry out corresponding sequential conversion simultaneously, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3, so that adopt the SRAM interface that the data processing unit is carried out write operation; If current be the internal memory operations pattern, and by state machine (State Machine) control decoding unit (Decoder), when keeping last activation manipulation among the CS0～CS3 of gating one operates so that a certain internal storage is write the back preliminary filling.

10. read: if current for the processing unit operation pattern, column address is sent into sequential conversion (Timing Transfer) module, with preceding when once activating row address, the body address of buffer memory splice, carry out corresponding sequential conversion simultaneously, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3, so that adopt the SRAM interface that processing unit is carried out read operation; If current be the on-chip memory operator scheme, and control decoding unit (Decoder) by state machine (State Machine), when keeping last activation manipulation among the CS0～CS3 of gating one is so that carry out read operation to a certain internal storage.

11. read the back preliminary filling: reading under the preliminary filling order of back, if current is the data processing unit operator scheme, column address is sent into sequential conversion (Timing Transfer) module, with preceding when once activating row address, the body address of buffer memory splice, carry out corresponding sequential conversion simultaneously, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3, so that adopt the SRAM interface that the data processing unit is carried out read operation; If current be the internal memory operations pattern, and by state machine (State Machine) control decoding unit (Decoder), when keeping last activation manipulation among the CS0～CS3 of gating one operates so that a certain internal storage is read the back preliminary filling.

12. there is not operation: under no mode of operation, keep current operator scheme, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3.

13. the cancellation device is chosen: keep current operator scheme, and by state machine (State Machine) control decoding unit (Decoder), with the whole gating not of CS0～CS3.

14. enter low-power consumption mode: enter the on-chip memory operator scheme under the low-power consumption mode order entering, by state machine (State Machine) control decoding unit (Decoder), with the whole gatings of CS0～CS3, control all internal storages and enter low-power consumption mode.

15. go out low-power consumption mode: going out to enter the on-chip memory operator scheme under the low-power consumption mode order,,, controlling all internal storages and withdraw from low-power consumption mode with the whole gatings of CS0～CS3 by state machine (StateMachine) control decoding unit (Decoder).

The present invention's realization has the interface method of the DRAM storer of data-handling capacity, adopt of the visit of different flow processing to internal storage and inter-process unit, by system software it is mapped to corresponding address space, and carry out alternately according to general DRAM interface sequence and the DRAM storer with data-handling capacity, it is at internal storage or inter-process unit that the interface module of memory inside is distinguished this visit by address wire, and the conversion that accessing time sequence is provided is to realize effective visit.Adopt this interface method and structure, the DRAM storer that can will have data-handling capacity on the basis of not carrying out any hardware change is integrated into the available data disposal system, has and uses advantage easily.

Claims

1. realization has the interface method of the dynamic RAM DRAM of data-handling capacity, comprise and adopt of the visit of different flow processing internal storage unit and internal data processing unit, adopt the interface sequence of general-purpose storage that the DRAM storer with data-handling capacity is operated, by the visit of internal interface unit differentiation to internal storage unit and internal data processing unit, and finish corresponding sequential conversion, it is characterized in that:

The program of A, data handling system is sent visit to internal storage unit by general access instruction;

The program of A, data handling system is sent visit to inner data processing unit by calling API;

Described internal interface unit is distinguished to internal storage unit with to the visit of inner data processing unit by address signal;

Described internal interface unit will directly send to internal storage unit to the visit order of internal storage unit;

Described internal interface unit will be carried out the sequential conversion to the visit order of inner data processing unit, realize the visit to inner data processing unit control register.

2. realization according to claim 1 has the interface method of the dynamic RAM DRAM of data-handling capacity, it is characterized in that: described standard DRAM memory interface sequential is the sequential of FLASH, SRAM, SDRAM, DDR, DDR2, DDR3, GDDR2 or GDDR3 interface standard regulation.

3. realization according to claim 1 has the interface method of the dynamic RAM DRAM of data-handling capacity, it is characterized in that: described internal interface unit comprises state machine, sequential modular converter, refresh count module and decoding module, state machine links with sequential modular converter, refresh count module and decoding module respectively, switching between wherein state machine record current accessed state, and the realization different access state; The sequential modular converter is realized the conversion of general DRAM memory access sequential to SRAM memory access sequential, to realize the visit to inner data processing unit; The refresh count module is counted the refresh command that sends, and according to the numerical value of counting, selects different internal repository to refresh; Decoding module is deciphered some position of address, and selects corresponding internal repository to operate, to realize the visit to internal storage unit.