CN103632708A - Self-refreshing control device and method for synchronous dynamic random access memory - Google Patents
Self-refreshing control device and method for synchronous dynamic random access memory Download PDFInfo
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- CN103632708A CN103632708A CN201210311491.2A CN201210311491A CN103632708A CN 103632708 A CN103632708 A CN 103632708A CN 201210311491 A CN201210311491 A CN 201210311491A CN 103632708 A CN103632708 A CN 103632708A
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Abstract
The invention discloses a self-refreshing control device and method for a synchronous dynamic random access memory. The method comprises steps: a frequency modulation control unit of a synchronous dynamic random access memory receives control instructions sent from a CPU through bus and is started; the states of real-time modules are inquired, that the synchronous dynamic random access memory permits no response to read-write requests of all the real-time modules in frequency modulation control time is determined, pause instructions are sent to a controller of the synchronous dynamic random access memory, and the controller is controlled to pause all the read-write requests to the synchronous dynamic random access memory; updating instructions are sent to the controller, thus the controller controls the synchronous dynamic random access memory into a self-refreshing mode; taking instructions are sent to a clock control unit, frequency modulation information of target frequency is taken, the clock control unit sends the clock signal of the target frequency to the controller, finally, the controller performs frequency modulation operation to the synchronous dynamic random access memory. The method can achieve self-refreshing control to a synchronous dynamic random access memory through hardware chips.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit) technical field, particularly relate to a kind of self refresh control apparatus and method of synchronous DRAM.
Background technology
The power consumption of digital circuit is divided into dynamic power consumption and quiescent dissipation, and the in the situation that of special process and Circuits System, dynamic power consumption is directly proportional to frequency, therefore generally by reducing voltage and frequency, reduces dynamic power consumption.
In the prior art, the storage medium of mass storage adopts Synchronous Dynamic Random Access Memory (Synchronous Dynamic Random Access Memory conventionally, SDRAM), it is Synchronous Dynamic Random Access Memory, also comprise Double Data Rate synchronous DRAM (Double Data Rate SDRAM simultaneously, DDR SDRAM), people's custom is called DDR, DDR internal memory develops on sdram memory basis, still continue to use SDRAM production system, therefore for internal memory manufacturer, only need improve a little manufacturing the equipment of common SDRAM, can realize the production of DDR internal memory.
The frequency of Synchronous Dynamic Random Access Memory is determined by the bandwidth demand of Circuits System, and the bandwidth demand of Circuits System can be with application scenarios acute variation, therefore according to the bandwidth demand of system, on-the-fly modify the frequency of Synchronous Dynamic Random Access Memory, can realize in the object that meets the situation decline low-power consumption of performance.
Generally, Synchronous Dynamic Random Access Memory adopts and automatically refreshes (Auto refresh) pattern, and this pattern needs controller regularly to SDRAM, to send refreshing instruction.Under this pattern, SDRAM chip can carry out data access operation, but power consumption is larger.Yet sdram controller also has another kind of refresh mode, it is self-refresh (self refresh) pattern, this pattern does not need outside regular refreshing instruction, SDRAM chip will oneself produce refresh pulse inner, under this pattern, the relative auto refresh mode of power consumption of SDRAM chip has greatly reduced, but while SDRAM chip cannot make an immediate response, the accessing operation of data, only can keep available data not lose.The relevant criterion of formulating according to joint electron device engineering council (Joint Electron Device Engineering Council, JEDEC), only has Synchronous Dynamic Random Access Memory under self-refresh mode, can carry out the adjustment of frequency.But, the adjustment period of frequency between, must cause Synchronous Dynamic Random Access Memory cannot normally access within a period of time.
In prior art, when the self-refresh of realizing synchronous DRAM is controlled, being all to control and transmission and the data transmission of frequency modulation instruction by software, often there are a lot of technological deficiencies in this method; Wherein, the problem of major embodiment three aspects:.One, CPU is when processing frequency modulation program, because software control self-refresh control procedure has taken a large amount of frequency modulation control time, SDRAM outside sheet again can not be accessed simultaneously, so CPU will read RAM or the Cache in sheet when processing frequency modulation programmed instruction, but will significantly reduce cpu performance like this.Two, when using software frequency modulation, CPU may outage program, at this moment the SDRAM outside sheet can not be accessed, so CPU will wait for reading of interrupt instruction, because software control self-refresh control procedure has taken a large amount of frequency modulation control time, SDRAM also needs the frequency modulation instruction that waiting for CPU sends simultaneously, is easy to like this system mistake.Three, when using software self-refresh frequency modulation, because software control self-refresh control procedure has taken a large amount of frequency modulation control time, SDRAM outside sheet can not be accessed, and in software control system, a plurality of Real time capable modules need a large amount of buffer registers (Buffer), and this will increase more cost.
In a word, this method has reduced system performance greatly, and software control simultaneously needs long time frequency modulation removal to control and response, and this,, by badly influencing the performance of synchronous DRAM, is also easy to cause system mistake; In addition, use all processes of software control self-refresh, will have to use more buffer register, this uses resource by occupying a large amount of CPU, reduces memory system travelling speed and has also increased production cost.
Therefore in prior art, it is a very scabrous problem that the self-refresh that how to overcome in prior art the technological deficiency by software control self refresh operation and realize more at high speed synchronous DRAM is controlled.
Summary of the invention
Based on the problems referred to above, the invention provides self-refresh control method and the device of synchronous DRAM, by hardware chip device, realize at high speed the self-refresh control operation of synchronous DRAM, thereby overcome in prior art by the technological deficiency of software control self refresh operation.
The invention provides a kind of self refresh control apparatus of synchronous DRAM, comprise main control unit and synchronous DRAM, described main control unit comprises clock control cell, one or more Real time capable module, synchronous DRAM frequency modulation control unit and controller of synchronous dynamic random storage; Described synchronous DRAM frequency modulation control unit is electrically connected to described clock control cell, described Real time capable module and described controller of synchronous dynamic random storage respectively; Described controller of synchronous dynamic random storage is connected by external interface with synchronous DRAM;
Described clock control cell comprises clock generator, wherein:
Described clock generator, for after receiving frequency modulation instruction, produces the synchronous DRAM clock signal of target frequency, and sends to controller of synchronous dynamic random storage;
Described Real time capable module, for carrying out data interaction with synchronous DRAM;
Described synchronous DRAM frequency modulation control unit comprises receiver module, enquiry module, time-out module, update module and frequency modulation module, wherein:
Described receiver module, the steering order the execution startup execution subsequent operation that for receiving CPU, by bus, send;
Described enquiry module, for inquiring about the state of judging all Real time capable modules, and after judging that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond, jumps to described time-out module and carries out corresponding operating;
Described time-out module, for sending pause instruction to controller of synchronous dynamic random storage, controls controller of synchronous dynamic random storage and suspends all to synchronous DRAM read-write requests;
Described update module, for sending update instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM and enters self-refresh mode;
Described frequency modulation module, for sending, transfer instruction to clock control cell, transfer clock control cell internal object frequency frequency modulation information, clock control cell sends to controller of synchronous dynamic random storage by the clock signal of target frequency, and described controller of synchronous dynamic random storage is controlled synchronous DRAM and started frequency modulation operation;
Described controller of synchronous dynamic random storage, for directly carrying out frequency modulation operation to synchronous DRAM.
Preferably, as a kind of embodiment.Described clock control cell also comprises the first buffer register, and first sends subelement, the second buffer register, and second sends subelement, wherein:
Described the first buffer register, after the target frequency frequency modulation information sending by bus at clock control cell reception CPU, preserves target frequency frequency modulation information;
Described first sends subelement, for when the frequency modulation, the first buffer register internal object frequency frequency modulation information is sent in described the second buffer register;
Described the second buffer register, for before frequency modulation not, keeps the frequency of former clock frequency control synchronous DRAM;
Described second sends subelement, for when the frequency modulation, frequency modulation instruction is sent to described clock generator after receiving the target frequency frequency modulation information from the first buffer register.
Preferably, as a kind of embodiment.Described frequency modulation module comprises transfers submodule, wherein:
The described submodule of transferring, transfers instruction to clock control cell for sending, and clock control cell starts presetting extract operation.
Preferably, as a kind of embodiment.Described controller of synchronous dynamic random storage also comprises and exits module, recovers module and finish module, wherein:
The described module that exits, for after frequency modulation EO, sends exit instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM and exits self-refresh state;
Described recovery module, recovers instruction to controller of synchronous dynamic random storage for sending, and control controller of synchronous dynamic random storage recovers all synchronous DRAM read-write requests is responded;
Described end module, for finishing the self-refresh control operation of synchronous DRAM.
Preferably, as a kind of embodiment.Described a plurality of Real time capable module also comprises corresponding a plurality of the 3rd buffer registers; Described Real time capable module is corresponding one by one with the 3rd buffer register;
Described a plurality of the 3rd buffer register, in the time, carrying out reading and writing data with a plurality of Real time capable modules in frequency modulation control.
Preferably, as a kind of embodiment.Described enquiry module comprises judgement submodule and return to submodule, wherein:
Described judgement submodule, for judging whether that the data volume that all Real time capable modules read its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the data volume that the 3rd buffer register is stored; Or the data volume whether all Real time capable modules write its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the 3rd buffer register residual memory space; If so, suspend module described in redirect and carry out corresponding operating; If not, redirect is returned to submodule and is carried out corresponding operation;
The described submodule that returns, for returning to described judgement submodule and carrying out corresponding operating in next sequential.
Correspondingly, as a kind of embodiment.The present invention also provides a kind of self-refresh control method of synchronous DRAM, and described method comprises the steps:
Steps A, synchronous DRAM frequency modulation control unit receive steering order the execution startup subsequent operation that CPU sends by bus;
The state of all Real time capable modules is judged in step B, the inquiry of synchronous DRAM frequency modulation control unit, and performs step C after judgement frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond;
Step C, synchronous DRAM frequency modulation control unit send pause instruction to controller of synchronous dynamic random storage, control controller of synchronous dynamic random storage and suspend all to synchronous DRAM read-write requests;
Step D, synchronous DRAM frequency modulation control unit send update instruction to controller of synchronous dynamic random storage, make controller of synchronous dynamic random storage control synchronous DRAM and enter self-refresh mode;
Step e, synchronous DRAM frequency modulation control unit send transfers instruction to clock control cell, transfer clock control cell internal object frequency frequency modulation information, clock control cell sends to controller of synchronous dynamic random storage by the clock signal of target frequency, and described controller of synchronous dynamic random storage is controlled synchronous DRAM and carried out frequency modulation operation.
Preferably, as a kind of embodiment.Described steps A comprises the steps:
Step a1, clock control cell receive the target frequency frequency modulation information that CPU sends by bus, are saved in the first buffer register in clock control cell;
Step a2, described the second buffer register keep the frequency of former clock frequency control synchronous DRAM.
Preferably, as a kind of embodiment.Described step e specifically comprises the steps:
Step e1, synchronous DRAM frequency modulation control unit send transfers instruction to clock control cell, and clock control cell starts presetting extract operation;
Step e2, after presetting extract operation starts, described first sends subelement sends to target frequency frequency modulation information in described the second buffer register; After described the second transmission subelement receives the target frequency frequency modulation information from the first buffer register, frequency modulation instruction is sent to described clock generator;
Step e3, described clock generator, after receiving frequency modulation instruction, produce the clock signal of target frequency, and send to controller of synchronous dynamic random storage, and described controller of synchronous dynamic random storage is controlled synchronous DRAM and carried out frequency modulation operation.
Preferably, as a kind of embodiment.After described step e, also comprise following each step:
Step F, after frequency modulation EO, synchronous DRAM frequency modulation control unit sends exit instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM exit self-refresh state;
Step G, synchronous DRAM frequency modulation control unit send and recover instruction to controller of synchronous dynamic random storage, and control controller of synchronous dynamic random storage recovers all synchronous DRAM read-write requests is responded;
The self-refresh control operation of step H, end synchronous DRAM.
Preferably, as a kind of embodiment.At frequency modulated clock, in the cycle, described a plurality of Real time capable modules a plurality of the 3rd buffer registers corresponding thereto carry out reading and writing data.
Preferably, as a kind of embodiment.In described step B, described synchronous DRAM frequency modulation control unit inquiry judges the concrete operation step of the state of all Real time capable modules:
Step b1, judge whether that the data volume that all Real time capable modules read its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the data volume that the 3rd buffer register is stored; Or the data volume whether all Real time capable modules write its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the 3rd buffer register residual memory space;
Step b2, if so, judges that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond; If not, return to step b1 and wait for that next sequential carries out decision operation again.
Beneficial effect of the present invention comprises:
The self refresh control apparatus of a kind of synchronous DRAM provided by the invention and method, wherein method comprises the following steps: the steering order that synchronous DRAM frequency modulation control unit reception CPU sends by bus is also carried out start-up operation; The state of all Real time capable modules is judged in inquiry, after judging that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond, send pause instruction to controller of synchronous dynamic random storage, control described controller and suspend all to synchronous DRAM read-write requests; Send update instruction to controller, make controller control synchronous DRAM and enter self-refresh mode; Transmission is transferred instruction to clock control cell, transfers clock control cell internal object frequency frequency modulation information, and clock control cell sends to controller by the clock signal of target frequency, final, and controller is realized the frequency modulation operation to synchronous DRAM.Method provided by the invention can be realized synchronous DRAM self-refresh is controlled by hardware chip.
The self refresh control apparatus of synchronous DRAM provided by the invention, association's reconciliation process of all control operations Hardware all, reaches prestissimo and completes frequency modulation, does not need software intervention frequency-modulating process.Considering in frequency-modulating process, is to carry out data read-write operation to synchronous DRAM, therefore reduces the whole frequency modulation control time, is conducive to improving performance.
Accompanying drawing explanation
Fig. 1 is the structural representation of self refresh control apparatus one specific embodiment of synchronous DRAM of the present invention;
Fig. 2 is the schematic flow sheet of self-refresh control method one specific embodiment of synchronous DRAM of the present invention.
Embodiment
Below in conjunction with Figure of description, the embodiment of the self refresh control apparatus of synchronous DRAM of the present invention and method is described.
The embodiment of the present invention provides a kind of self refresh control apparatus of synchronous DRAM, as shown in Figure 1, comprise main control unit 10 and synchronous DRAM 20, described main control unit 10 comprises clock control cell 101, also comprises Real time capable module 102, synchronous DRAM frequency modulation control unit 103 and controller of synchronous dynamic random storage 104; Described clock control cell 101 comprises clock generator 1011, and described synchronous DRAM frequency modulation control unit 103 is electrically connected to described clock control cell 101, described Real time capable module 102 and described controller of synchronous dynamic random storage 104 respectively; Described controller of synchronous dynamic random storage 104 is connected by external interface with synchronous DRAM 20; Described Real time capable module can be one or more, wherein:
Described clock control cell 101 comprises clock generator 1011, wherein:
Described clock generator 1011, for after receiving frequency modulation instruction, produces the synchronous DRAM clock signal of target frequency, and sends to controller of synchronous dynamic random storage;
Described Real time capable module 102, for carrying out data interaction with synchronous DRAM;
Described synchronous DRAM frequency modulation control unit 103 comprises receiver module 1031, enquiry module 1032, suspends module 1033, update module 1034 and frequency modulation module 1035, wherein:
Described receiver module 1031, the steering order the execution startup execution subsequent operation that for receiving CPU, by bus, send;
Described enquiry module 1032, for inquiring about the state of judging all Real time capable modules, and after judging that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond, jumps to described time-out module and carries out corresponding operating;
Described time-out module 1033, for sending pause instruction to controller of synchronous dynamic random storage, controls controller of synchronous dynamic random storage and suspends all to synchronous DRAM read-write requests;
Described update module 1034, for sending update instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM and enters self-refresh mode;
Described frequency modulation module 1035, for sending, transfer instruction to clock control cell, transfer clock control cell internal object frequency frequency modulation information, clock control cell sends to controller of synchronous dynamic random storage by the clock signal of target frequency, and described controller of synchronous dynamic random storage is controlled synchronous DRAM and started frequency modulation operation;
Described controller of synchronous dynamic random storage 104, for directly carrying out frequency modulation operation to synchronous DRAM.
In embodiments of the present invention, self refresh control apparatus comprises main control unit and the outer SDRAM of sheet, and described synchronous DRAM frequency modulation control unit is electrically connected to described clock control cell, described Real time capable module and described controller of synchronous dynamic random storage respectively; Controller of synchronous dynamic random storage is directly controlled in described synchronous DRAM frequency modulation control unit, and controller of synchronous dynamic random storage is for the outer SDRAM of direct control strip.
Preferably, as a kind of embodiment.
Described clock control cell 101 also comprises that the first buffer register 1012, the first sends subelement 1013, the second buffer registers 1014, the second and sends subelement 1015, wherein:
Described the first buffer register 1012, after the target frequency frequency modulation information sending by bus at clock control cell reception CPU, preserves target frequency frequency modulation information;
Described first sends subelement 1013, for when the frequency modulation, the first buffer register internal object frequency frequency modulation information is sent in described the second buffer register;
Described the second buffer register 1014, for before frequency modulation not, keeps the frequency of former clock frequency control synchronous DRAM;
Described second sends subelement 1015, for when the frequency modulation, frequency modulation instruction is sent to described clock generator after receiving the target frequency frequency modulation information from the first buffer register.
Preferably, as a kind of embodiment.Described frequency modulation module 1035 specifically comprises transfers submodule, wherein:
The described submodule of transferring, transfers instruction to clock control cell for sending, and clock control cell starts presetting extract operation.
First, at self-refresh, control when initial and (now do not start to carry out frequency modulation operation), the first buffer register in clock control cell receives the target frequency frequency modulation information that CPU sends by bus and preserves; Meanwhile, the receiver module of synchronous DRAM frequency modulation control unit, receives steering order execution startup beamhouse operation that CPU sends by bus.At this moment self-refresh device, in frequency modulation incubation period, need to pass through preprocessing process, could carry out frequency modulation control operation.
Described preprocessing process comprises: the state of all Real time capable modules is judged in inquiry; Described time-out module, sends pause instruction to controller of synchronous dynamic random storage, and control controller of synchronous dynamic random storage time-out is all to be responded synchronous DRAM read-write requests; Described update module, sends update instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM and enters self-refresh mode.After preprocessing process finishes, at this moment ensured that self refresh control apparatus is under self-refresh mode time, the interference that the SDRAM outside sheet can not be read and write.Simultaneously, corresponding Buffer(the 3rd buffer register that is provided with a reasonable storage space in each Real time capable module), like this when ensureing that self refresh control apparatus is processed self-refresh mode, data in sheet are are normally read and write, avoided loss of data, both reduce the power consumption of system, do not affected again normal reading and writing data.
Then, self refresh control apparatus when carrying out frequency modulation operation, described in transfer submodule, first send and transfer instruction to clock control cell, clock control cell starts presetting extract operation.After presetting extract operation starts, because the target frequency frequency modulation information that CPU sends is in the first buffer register, described first sends subelement sends to the target frequency frequency modulation information in the first buffer register in described the second buffer register; After described the second transmission subelement receives the target frequency frequency modulation information from the first buffer register, frequency modulation instruction is sent to described clock generator; Described clock generator can be according to the clock frequency of the transmission change of the change target frequency of setting.Clock generator sends to controller of synchronous dynamic random storage by target frequency clock signal, and described controller of synchronous dynamic random storage is directly realized the frequency modulation operation to the outer SDRAM of sheet.Described clock signal comprises clock enable signal (CKE), row address signal (Row Address Strobe, RAS), column address signal (Column Address Strobe, CAS) etc., and transmits by said external interface.
Clock generator only needs technician's direct compilation program.Can complete the setting of input and output clock frequency.A control signal of sdram controller output is connected with the corresponding signal of SDRAM chip particle, realizes the logic control for SDRAM chip particle.
Preferably, as a kind of embodiment.Described synchronous DRAM unit 103 also comprises and exits module 1036, recovers module 1037 and finish module 1038, wherein:
The described module 1036 that exits, for after frequency modulation EO, sends exit instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM and exits self-refresh state;
Described recovery module 1037, recovers instruction to controller of synchronous dynamic random storage for sending, and control controller of synchronous dynamic random storage recovers all synchronous DRAM read-write requests is responded;
Described end module 1038, for finishing the self-refresh control operation of synchronous DRAM.
Finally, after frequency modulation EO, self-refresh device need to enter rejuvenation and finish self-refresh control operation.
Preferably, as a kind of embodiment.Described a plurality of Real time capable module also comprises corresponding a plurality of the 3rd buffer registers; Described Real time capable module is corresponding one by one with the 3rd buffer register; Described each Real time capable module 102 also comprises a 3rd corresponding buffer register 1021, wherein:
Described a plurality of the 3rd buffer register 1021, in the time, carrying out reading and writing data with a plurality of Real time capable modules 102 in frequency modulation control.
Preferably, as a kind of embodiment.Described enquiry module comprises judgement submodule and return to submodule, wherein:
Described judgement submodule, for judging whether that the data volume that all Real time capable modules read its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the data volume that the 3rd buffer register is stored; Or the data volume whether all Real time capable modules write its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the 3rd buffer register residual memory space; If so, suspend module described in redirect and carry out corresponding operating; If not, redirect is returned to submodule and is carried out corresponding operation;
The described submodule that returns, for returning to described judgement submodule and carrying out corresponding operating in next sequential.
Described judgement submodule is for judging the state of Real time capable module, illustrate, take certain Real time capable module carries out data to write the 3rd buffer register is example, the frequency modulation control time is that T(hardware chip calculates at the beginning of design), the 3rd buffer register storage space integrating is large (hardware chip configures at the beginning of design) enough, at this moment certain Real time capable module carries out data and prewrites fashionable, whether the described data volume that judges that submodule need to judge that this Real time capable module writes is in advance less than the 3rd buffer register (transfer rate of the 3rd buffer register is V) residual memory space (M).Whether the value of calculating V * T is less than residual memory space M, and all meets after V * T ﹤ M at all Real time capable modules, just judges that meeting all Real time capable modules can not carry out the condition of reading and writing data within the synchronous DRAM frequency modulation control time.The pre-read operation of described judgement Real time capable module and above-mentionedly write in advance similarly, the embodiment of the present invention repeats no longer one by one to this.
It will be understood by those skilled in the art that the self refresh control apparatus of the synchronous DRAM that the embodiment of the present invention provides is because significantly having reduced the frequency modulation control time, so can overcome insoluble three problems in prior art.One, in embodiments of the present invention, when carrying out frequency modulation operation, by hardware chip, realize the control to synchronous DRAM, so can not use CPU to process frequency modulation program, will ensure cpu performance like this.Two, same, in embodiments of the present invention, CPU may outage program, at this moment the SDRAM outside sheet can not be accessed, CPU will wait for reading of interrupt instruction, but without waiting for the very long frequency modulation control time, after self-refresh is controlled and finished, CPU will can read interrupt instruction by the SDRAM from sheet very soon.Three, same, in embodiments of the present invention, because hardware chip is controlled the frequency modulation control time that self-refresh control procedure has taken minute quantity, although the SDRAM outside sheet can not be accessed, but in self refresh control apparatus, a plurality of Real time capable modules, also without a large amount of buffer registers (Buffer), just can ensure the reading and writing data of Real time capable module.
As a kind of embodiment; the embodiment of the present invention is not only protected the self-refresh control procedure of Synchronous Dynamic Random Access Memory; be applicable to too the improvement version DDR SDRAM of SDRAM simultaneously; therefore for internal memory manufacturer; only need improve a little the synchronous DRAM self refresh control apparatus of the embodiment of the present invention, can realize the Production design of Double Data Rate synchronous DRAM self refresh control apparatus and implement.
The self refresh control apparatus of the synchronous DRAM that embodiments of the invention provide can be realized by computer program.Those skilled in the art should be understood that, described Module Division mode is only a kind of in numerous Module Division, if be divided into other modules or do not divide module, as long as device has above-mentioned functions, and all should be within the application's protection domain.
Based on same inventive concept, the embodiment of the present invention also provides a kind of self-refresh control method of synchronous DRAM, because the principle that the method is dealt with problems is similar to the various functions of the self refresh control apparatus of aforementioned a kind of synchronous DRAM, therefore, the enforcement of the method can realize by aforementioned means concrete function, repeats part and repeats no more.
Correspondingly, as a kind of embodiment.The self-refresh control method of the synchronous DRAM that the embodiment of the present invention provides, as shown in Figure 2, described method comprises the steps:
Steps A, synchronous DRAM frequency modulation control unit receive steering order the execution startup subsequent operation that CPU sends by bus;
The state of all Real time capable modules is judged in step B, the inquiry of synchronous DRAM frequency modulation control unit, and performs step C after judgement frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond;
Step C, synchronous DRAM frequency modulation control unit send pause instruction to controller of synchronous dynamic random storage, control controller of synchronous dynamic random storage and suspend all to synchronous DRAM read-write requests;
Step D, synchronous DRAM frequency modulation control unit send update instruction to controller of synchronous dynamic random storage, make controller of synchronous dynamic random storage control synchronous DRAM and enter self-refresh mode;
Step e, synchronous DRAM frequency modulation control unit send transfers instruction to clock control cell, transfer clock control cell internal object frequency frequency modulation information, clock control cell sends to controller of synchronous dynamic random storage by the clock signal of target frequency, and described controller of synchronous dynamic random storage is controlled synchronous DRAM and carried out frequency modulation operation.
Preferably, as a kind of embodiment.Described steps A comprises the steps:
Step a1, clock control cell receive the target frequency frequency modulation information that CPU sends by bus, are saved in the first buffer register in clock control cell;
Step a2, described the second buffer register keep the frequency of former clock frequency control synchronous DRAM.
Preferably, as a kind of embodiment.Described step e specifically comprises the steps:
Step e1, synchronous DRAM frequency modulation control unit send transfers instruction to clock control cell, and clock control cell starts presetting extract operation;
Step e2, after presetting extract operation starts, described first sends subelement sends to target frequency frequency modulation information in described the second buffer register; After described the second transmission subelement receives the target frequency frequency modulation information from the first buffer register, frequency modulation instruction is sent to described clock generator;
Step e3, described clock generator, after receiving frequency modulation instruction, produce the clock signal of target frequency, and send to controller of synchronous dynamic random storage, and described controller of synchronous dynamic random storage is controlled synchronous DRAM and carried out frequency modulation operation.
Preferably, as a kind of embodiment.After described step e, also comprise following each step:
Step F, after frequency modulation EO, synchronous DRAM frequency modulation control unit sends exit instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM exit self-refresh state;
Step G, synchronous DRAM frequency modulation control unit send and recover instruction to controller of synchronous dynamic random storage, and control controller of synchronous dynamic random storage recovers all synchronous DRAM read-write requests is responded;
The self-refresh control operation of step H, end synchronous DRAM.
Preferably, as a kind of embodiment.At frequency modulated clock, in the cycle, described a plurality of Real time capable modules a plurality of the 3rd buffer registers corresponding thereto carry out reading and writing data.
Preferably, as a kind of embodiment.In described step B, described synchronous DRAM frequency modulation control unit inquiry judges the concrete operation step of the state of all Real time capable modules:
Step b1, judge whether that the data volume that all Real time capable modules read its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the data volume that the 3rd buffer register is stored; Or the data volume whether all Real time capable modules write its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the 3rd buffer register residual memory space;
Step b2, if so, judges that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond; If not, return to step b1 and wait for that next sequential carries out decision operation again.
The self refresh control apparatus of a kind of synchronous DRAM that the embodiment of the present invention provides and method, wherein method comprises the following steps: the steering order that synchronous DRAM frequency modulation control unit reception CPU sends by bus is also carried out start-up operation; The state of all Real time capable modules is judged in inquiry, after judging that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond, send pause instruction to controller of synchronous dynamic random storage, control described controller and suspend all to synchronous DRAM read-write requests; Send update instruction to controller, make controller control synchronous DRAM and enter self-refresh mode; Transmission is transferred instruction to clock control cell, transfers clock control cell internal object frequency frequency modulation information, and clock control cell sends to controller by the clock signal of target frequency, final, and controller is realized the frequency modulation operation to synchronous DRAM.The method that the embodiment of the present invention provides can be realized synchronous DRAM self-refresh is controlled by hardware chip.
The self refresh control apparatus of the synchronous DRAM that the embodiment of the present invention provides, association's reconciliation process of all control operations Hardware all, reaches prestissimo and completes frequency modulation, does not need software intervention frequency-modulating process.Considering in frequency-modulating process, is to carry out data read-write operation to synchronous DRAM, therefore reduces the whole frequency modulation control time, is conducive to promote the performance of memory system.
The above embodiment has only expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (12)
1. the self refresh control apparatus of a synchronous DRAM, it is characterized in that, comprise main control unit and synchronous DRAM, described main control unit comprises clock control cell, one or more Real time capable module, synchronous DRAM frequency modulation control unit and controller of synchronous dynamic random storage; Described synchronous DRAM frequency modulation control unit is electrically connected to described clock control cell, described Real time capable module and described controller of synchronous dynamic random storage respectively; Described controller of synchronous dynamic random storage is connected by external interface with synchronous DRAM;
Described clock control cell comprises clock generator, wherein:
Described clock generator, for after receiving frequency modulation instruction, produces the synchronous DRAM clock signal of target frequency, and sends to controller of synchronous dynamic random storage;
Described Real time capable module, for carrying out data interaction with synchronous DRAM;
Described synchronous DRAM frequency modulation control unit comprises receiver module, enquiry module, time-out module, update module and frequency modulation module, wherein:
Described receiver module, the steering order the execution startup execution subsequent operation that for receiving CPU, by bus, send;
Described enquiry module, for inquiring about the state of judging all Real time capable modules, and after judging that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond, jumps to described time-out module and carries out corresponding operating;
Described time-out module, for sending pause instruction to controller of synchronous dynamic random storage, controls controller of synchronous dynamic random storage and suspends all to synchronous DRAM read-write requests;
Described update module, for sending update instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM and enters self-refresh mode;
Described frequency modulation module, for sending, transfer instruction to clock control cell, transfer clock control cell internal object frequency frequency modulation information, clock control cell sends to controller of synchronous dynamic random storage by the clock signal of target frequency, and described controller of synchronous dynamic random storage is controlled synchronous DRAM and started frequency modulation operation;
Described controller of synchronous dynamic random storage, for directly carrying out frequency modulation operation to synchronous DRAM.
2. the self refresh control apparatus of synchronous DRAM according to claim 1, is characterized in that, described clock control cell also comprises the first buffer register, and first sends subelement, the second buffer register, and second sends subelement, wherein:
Described the first buffer register, after the target frequency frequency modulation information sending by bus at clock control cell reception CPU, preserves target frequency frequency modulation information;
Described first sends subelement, for when the frequency modulation, the first buffer register internal object frequency frequency modulation information is sent in described the second buffer register;
Described the second buffer register, for before frequency modulation not, keeps the frequency of former clock frequency control synchronous DRAM;
Described second sends subelement, for when the frequency modulation, frequency modulation instruction is sent to described clock generator after receiving the target frequency frequency modulation information from the first buffer register.
3. the self refresh control apparatus of synchronous DRAM according to claim 1 and 2, is characterized in that, described frequency modulation module comprises transfers submodule, wherein:
The described submodule of transferring, transfers instruction to clock control cell for sending, and clock control cell starts presetting extract operation.
4. the self refresh control apparatus of synchronous DRAM according to claim 1, is characterized in that, described controller of synchronous dynamic random storage also comprises and exit module, recover module and finish module, wherein:
The described module that exits, for after frequency modulation EO, sends exit instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM and exits self-refresh state;
Described recovery module, recovers instruction to controller of synchronous dynamic random storage for sending, and control controller of synchronous dynamic random storage recovers all synchronous DRAM read-write requests is responded;
Described end module, for finishing the self-refresh control operation of synchronous DRAM.
5. the self refresh control apparatus of synchronous DRAM according to claim 1, is characterized in that, described a plurality of Real time capable modules also comprise corresponding a plurality of the 3rd buffer registers; Described Real time capable module is corresponding one by one with the 3rd buffer register;
Described a plurality of the 3rd buffer register, in the time, carrying out reading and writing data with a plurality of Real time capable modules in frequency modulation control.
6. the self-refresh control method of synchronous DRAM according to claim 1 or 5, is characterized in that, described enquiry module comprises judgement submodule and return to submodule, wherein:
Described judgement submodule, for judging whether that the data volume that all Real time capable modules read its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the data volume that the 3rd buffer register is stored; Or the data volume whether all Real time capable modules write its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the 3rd buffer register residual memory space; If so, suspend module described in redirect and carry out corresponding operating; If not, redirect is returned to submodule and is carried out corresponding operation;
The described submodule that returns, for returning to described judgement submodule and carrying out corresponding operating in next sequential.
7. a self-refresh control method for synchronous DRAM, is characterized in that, comprises the steps:
Steps A, synchronous DRAM frequency modulation control unit receive steering order the execution startup subsequent operation that CPU sends by bus;
The state of all Real time capable modules is judged in step B, the inquiry of synchronous DRAM frequency modulation control unit, and performs step C after judgement frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond;
Step C, synchronous DRAM frequency modulation control unit send pause instruction to controller of synchronous dynamic random storage, control controller of synchronous dynamic random storage and suspend all to synchronous DRAM read-write requests;
Step D, synchronous DRAM frequency modulation control unit send update instruction to controller of synchronous dynamic random storage, make controller of synchronous dynamic random storage control synchronous DRAM and enter self-refresh mode;
Step e, synchronous DRAM frequency modulation control unit send transfers instruction to clock control cell, transfer clock control cell internal object frequency frequency modulation information, clock control cell sends to controller of synchronous dynamic random storage by the clock signal of target frequency, and described controller of synchronous dynamic random storage is controlled synchronous DRAM and carried out frequency modulation operation.
8. the self-refresh control method of synchronous DRAM according to claim 7, is characterized in that, described steps A comprises the steps:
Step a1, clock control cell receive the target frequency frequency modulation information that CPU sends by bus, are saved in the first buffer register in clock control cell;
Step a2, described the second buffer register keep the frequency of former clock frequency control synchronous DRAM.
9. according to the self-refresh control method of the synchronous DRAM described in claim 7 or 8, it is characterized in that, described step e specifically comprises the steps:
Step e1, synchronous DRAM frequency modulation control unit send transfers instruction to clock control cell, and clock control cell starts presetting extract operation;
Step e2, after presetting extract operation starts, described first sends subelement sends to target frequency frequency modulation information in described the second buffer register; After described the second transmission subelement receives the target frequency frequency modulation information from the first buffer register, frequency modulation instruction is sent to described clock generator;
Step e3, described clock generator, after receiving frequency modulation instruction, produce the clock signal of target frequency, and send to controller of synchronous dynamic random storage, and described controller of synchronous dynamic random storage is controlled synchronous DRAM and carried out frequency modulation operation.
10. the self-refresh control method of synchronous DRAM according to claim 7, is characterized in that, also comprises following each step after described step e:
Step F, after frequency modulation EO, synchronous DRAM frequency modulation control unit sends exit instruction to controller of synchronous dynamic random storage, makes controller of synchronous dynamic random storage control synchronous DRAM exit self-refresh state;
Step G, synchronous DRAM frequency modulation control unit send and recover instruction to controller of synchronous dynamic random storage, and control controller of synchronous dynamic random storage recovers all synchronous DRAM read-write requests is responded;
The self-refresh control operation of step H, end synchronous DRAM.
The self-refresh control method of 11. synchronous DRAMs according to claim 7, is characterized in that, in frequency modulation control, in the time, also comprises the steps:
Described a plurality of Real time capable module carries out reading and writing data to a plurality of the 3rd buffer registers corresponding thereto.
12. according to the self-refresh control method of the synchronous DRAM described in claim 7 or 11, it is characterized in that, in described step B, the state of all Real time capable modules is judged in the inquiry of described synchronous DRAM frequency modulation control unit, comprises the steps:
Step b1, judge whether that the data volume that all Real time capable modules read its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the data volume that the 3rd buffer register is stored; Or the data volume whether all Real time capable modules write its corresponding the 3rd buffer register in the time in advance in frequency modulation control is all less than the 3rd buffer register residual memory space;
Step b2, if so, judges that frequency modulation control time inter-sync dynamic RAM allows the read-write requests of all Real time capable modules not respond; If not, return to step b1 and wait for that next sequential carries out decision operation again.
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