CN111158633A - DDR3 multichannel read-write controller based on FPGA and control method - Google Patents
DDR3 multichannel read-write controller based on FPGA and control method Download PDFInfo
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- CN111158633A CN111158633A CN201911373430.7A CN201911373430A CN111158633A CN 111158633 A CN111158633 A CN 111158633A CN 201911373430 A CN201911373430 A CN 201911373430A CN 111158633 A CN111158633 A CN 111158633A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Abstract
The invention discloses a DDR3 multichannel read-write controller and a control method based on an FPGA, wherein the multichannel read-write of a DDR3 is realized by the FPGA, and the controller comprises a plurality of groups of data write channels, a plurality of groups of data read channels, a read-write control state machine and a DDR3 chip controller. The writing channel and the reading channel of the multiple groups of data are respectively composed of asynchronous writing address FIFO, reading address FIFO and data FIFO; the read-write control module processes the read-write requests of each channel in a polling mode, dynamically changes the number of address requests processed each time according to the state of each channel, and performs data read and write operations on the DDR3 chip through the DDR3 chip controller according to the priority of each channel. The DDR3 read-write controller adopting the control method can realize multi-channel real-time access to the DDR3 chip.
Description
Technical Field
The invention relates to the field of DDR3 read-write controllers based on an FPGA, and relates to multi-channel data read-write of a memory.
Background
The DDR3 SDRAM memory, i.e. the third generation double-rate synchronous dynamic random access memory, hereinafter referred to as DDR3, has the advantages of large capacity, fast speed, low power consumption, etc., and is widely used in the fields of computers, electronic communications, etc. An FPGA (field programmable gate array), namely a field programmable gate array, has a large number of applications in the fields of signal processing and image processing due to its high-speed parallel capability, and when a large amount of data needs to be processed, a DDR3 chip is often used for extended storage due to the limited on-chip Block Ram capacity of the FPGA.
In a system including FPGA and DDR3, DDR3 acts as mass storage, typically as system data buffers, and mediates data exchange between modules. No matter the DDR3 chip is directly controlled or the DDR3 chip is read and written by using an IP core, the DDR3 chip of a single data channel cannot meet the requirement of reading and writing a large amount of high-speed data of a system. Therefore, the read-write channel needs to be expanded, and multiple channels of simultaneous reading and writing are performed on the DDR3, wherein a multiple-channel controller and a corresponding control method are very important.
Disclosure of Invention
The invention discloses a DDR3 multi-channel read-write controller and a control method based on an FPGA, aiming at the requirement that a plurality of modules in an FPGA system need to simultaneously write in or read from a DDR3 chip at a high speed, and the technical scheme is as follows:
DDR 3's multichannel read-write control adopts FPGA to realize, and the controller includes: the system comprises a plurality of groups of data writing channels, a plurality of groups of data reading channels, a read-write control state machine and a DDR3 chip controller;
wherein the multiple groups of data writing channels comprise asynchronous writing address FIFO and asynchronous writing data FIFO; the multiple groups of data reading channels comprise asynchronous reading address FIFO and asynchronous reading data FIFO;
the read-write control state machine and the DDR3 chip controller form a read-write control module, and the read-write control module and the data read-write channel are connected with the DDR3 chip controller; the asynchronous write address FIFO and the asynchronous write data FIFO are address and data caches of a data write channel, the write clock is a user operation clock, and the read clock is a read/write controller working clock; the asynchronous read address FIFO is an address cache of a data read channel, the write clock is a user operation clock, and the read clock is a read/write controller working clock; the asynchronous read data FIFO is a data cache of a data read channel, the write clock is a work clock of a read-write controller, the read clock is a user operation clock, and a program control write-full mark is configured;
the bit width of the asynchronous write address FIFO and the asynchronous read address FIFO is the same as that of the DDR3 chip controller address, and the bit width of the asynchronous write data FIFO and the asynchronous read data FIFO is the same as that of the DDR3 chip controller data.
The read-write control module takes a write address FIFO empty reading signal of the write channel as a low write request, takes a read address FIFO empty reading signal of the read channel as a low read request and a read data FIFO program control full writing mark as a low read request, and performs data read and write operations on a DDR3 chip through a DDR3 chip controller according to the priority of the channel;
the read-write control state machine in the read-write control module comprises A, B, C, D, E states, and the meaning, execution operation and transfer flow of each state are as follows:
and a state A: the state A is an initial state, and the executed operation comprises the following steps: resetting the FIFO of each channel, initializing the processing marks of each channel and the maximum number of transferred data of each channel, setting a priority for each channel, initializing a DDR3 chip through a DDR3 chip controller, waiting for the completion of the initialization of the DDR3 chip, and then transferring to a state B;
and a state B: state B is an idle state, and the operations performed include: checking whether each unprocessed channel has a request, and if each channel has no request, resetting a channel processing mark; otherwise, selecting a channel with the highest priority from the unprocessed request channels as a data channel to be processed; if the gated data channel to be processed is a write channel, transferring to a state C; if the gated data channel to be processed is a read channel, transferring to a state E;
and C, state C: state C is a write state, and the operations performed include: reading the cache address in the write address FIFO of the write channel gated in the state B, simultaneously reading the cache data in the write data FIFO, and writing the data into a DDR3 chip through a DDR3 chip controller; when the write address FIFO is empty or the number of the write data is equal to the maximum number of the transfer data of the current channel, stopping writing, setting the channel mark as processed, and transferring to the state D;
and a state D: the state D is a data updating state, and the executed operation comprises the following steps: checking whether the channel has a read-write request, and if so, increasing the maximum number of transfer data of the channel; otherwise, reducing the maximum transfer data number of the channel; transitioning to state B;
and a state E: state E is a read state and the operations performed include: reading a cache address in a read address FIFO of the read channel gated by the state B, reading data corresponding to the address from a DDR3 chip through a DDR3 chip controller, and writing the data into the read data FIFO; when the read address FIFO is empty, or the read data FIFO is full or the number of read data is equal to the maximum number of transfer data of the current channel, stopping reading, setting the channel mark as processed, and transferring to the state D.
The DDR3 multichannel read-write controller and the control method based on the FPGA simplify the write operation of the DDR3 chip into writing data and addresses into the FIFO, simplify the read operation of the DDR3 chip into writing the addresses into the FIFO and reading the data from the FIFO, reduce the operation difficulty of the DDR3 chip, and improve the flexibility of reading and writing the DDR3 chip.
Drawings
FIG. 1 is a block diagram of an embodiment of a DDR3 multi-channel read-write controller of the invention
FIG. 2 is a state transition diagram of the DDR3 multi-channel read-write control method of the invention.
Claims (2)
1. A DDR3 multi-channel read-write controller and a control method based on FPGA are characterized in that the multi-channel read-write control of DDR3 is realized by adopting FPGA, and the controller comprises: the system comprises a plurality of groups of data writing channels, a plurality of groups of data reading channels, a read-write control state machine and a DDR3 chip controller; wherein the multiple groups of data writing channels comprise asynchronous writing address FIFO and asynchronous writing data FIFO; the multiple groups of data reading channels comprise asynchronous reading address FIFO and asynchronous reading data FIFO; the read-write control state machine and the DDR3 chip controller form a read-write control module, and the read-write control module and the data read-write channel are connected with the DDR3 chip controller; the asynchronous write address FIFO and the asynchronous write data FIFO are address and data caches of a data write channel, the write clock is a user operation clock, and the read clock is a read/write controller working clock; the asynchronous read address FIFO is an address cache of a data read channel, the write clock is a user operation clock, and the read clock is a read/write controller working clock; the asynchronous read data FIFO is a data cache of a data read channel, the write clock is a work clock of a read-write controller, the read clock is a user operation clock, and a program control write-full mark is configured; the bit width of the asynchronous write address FIFO and the asynchronous read address FIFO is the same as that of the DDR3 chip controller address, and the bit width of the asynchronous write data FIFO and the asynchronous read data FIFO is the same as that of the DDR3 chip controller data.
2. The FPGA-based DDR3 multichannel read-write controller and control method as claimed in claim 1, wherein the read-write control module uses the write address FIFO empty read signal of the write channel as low as a write request, uses the read address FIFO empty read signal of the read channel as low and the read data FIFO program control full flag as low as a read request, and performs data read and write operations on the DDR3 chip through the DDR3 chip controller according to the priority of the channel; the read-write control state machine in the read-write control module comprises A, B, C, D, E states, and the meaning, execution operation and transfer flow of each state are as follows:
and a state A: the state A is an initial state, and the executed operation comprises the following steps: resetting the FIFO of each channel, initializing the processing marks of each channel and the maximum number of transferred data of each channel, setting a priority for each channel, initializing a DDR3 chip through a DDR3 chip controller, waiting for the completion of the initialization of the DDR3 chip, and then transferring to a state B;
and a state B: state B is an idle state, and the operations performed include: checking whether each unprocessed channel has a request, and if each channel has no request, resetting a channel processing mark; otherwise, selecting a channel with the highest priority from the unprocessed request channels as a data channel to be processed; if the gated data channel to be processed is a write channel, transferring to a state C; if the gated data channel to be processed is a read channel, transferring to a state E;
and C, state C: state C is a write state, and the operations performed include: reading the cache address in the write address FIFO of the write channel gated in the state B, simultaneously reading the cache data in the write data FIFO, and writing the data into a DDR3 chip through a DDR3 chip controller; when the write address FIFO is empty or the number of the write data is equal to the maximum number of the transfer data of the current channel, stopping writing, setting the channel mark as processed, and transferring to the state D;
and a state D: the state D is a data updating state, and the executed operation comprises the following steps: checking whether the channel has a read-write request, and if so, increasing the maximum number of transfer data of the channel; otherwise, reducing the maximum transfer data number of the channel; transitioning to state B;
and a state E: state E is a read state and the operations performed include: reading a cache address in a read address FIFO of the read channel gated by the state B, reading data corresponding to the address from a DDR3 chip through a DDR3 chip controller, and writing the data into the read data FIFO; when the read address FIFO is empty, or the read data FIFO is full or the number of read data is equal to the maximum number of transfer data of the current channel, stopping reading, setting the channel mark as processed, and transferring to the state D.
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| CN111694775A (en) * | 2020-06-09 | 2020-09-22 | 电子科技大学 | Device for performing read-write control based on time division multiplexing in DDR3 |
| CN112073650A (en) * | 2020-09-16 | 2020-12-11 | 中航华东光电有限公司 | DDR3 video cache control method based on FPGA |
| CN112148667A (en) * | 2020-09-04 | 2020-12-29 | 南京信息工程大学 | Cache system and method based on FPGA soft core |
| CN114036085A (en) * | 2021-09-24 | 2022-02-11 | 北京无线电测量研究所 | Multitask read-write scheduling method based on DDR4, computer equipment and storage medium |
| CN116719485A (en) * | 2023-08-09 | 2023-09-08 | 苏州浪潮智能科技有限公司 | FPGA-based data reading and writing method, reading and writing unit and FPGA |
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| CN114036085A (en) * | 2021-09-24 | 2022-02-11 | 北京无线电测量研究所 | Multitask read-write scheduling method based on DDR4, computer equipment and storage medium |
| CN114036085B (en) * | 2021-09-24 | 2024-04-12 | 北京无线电测量研究所 | DDR 4-based multitasking read-write scheduling method, computer equipment and storage medium |
| CN116719485A (en) * | 2023-08-09 | 2023-09-08 | 苏州浪潮智能科技有限公司 | FPGA-based data reading and writing method, reading and writing unit and FPGA |
| CN116719485B (en) * | 2023-08-09 | 2023-11-03 | 苏州浪潮智能科技有限公司 | FPGA-based data reading and writing method, reading and writing unit and FPGA |
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