CN112073650A - DDR3 video cache control method based on FPGA - Google Patents
DDR3 video cache control method based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
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- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The invention provides a DDR3 multi-channel video cache control method based on an FPGA, and belongs to the field of display. The video cache control method comprises the following steps: s1, acquiring multiple paths of input videos, wherein the memory value of each path of input video in the multiple paths of input videos is distributed according to the video frame number of the path of video; s2, generating a corresponding request signal group according to the multi-channel input video data; and S3, processing the request signal group according to priority arbitration logic, and correspondingly reading or storing one or more paths of video data of the paths of video data corresponding to the request signal group according to the memory value. The method can be easily designed into a selectable frame buffer mode, the buffer of each path of input video is independent, the resolution of the input video can be the same or different, and the user can conveniently solve the problems under different application requirements.
Description
Technical Field
The invention relates to the field of display, in particular to a DDR3 video cache control method based on an FPGA.
Background
In the display field, a display terminal of some monitoring systems or large-scale multi-task processing systems needs to display multiple paths of external video signals at the same time, and the display processing system can perform operations such as scaling, clipping or graphic processing on the external video signals through a memory cache. The display or the display processing system usually uses the FPGA as a signal processor, uses the DDR3 as a cache memory, and based on the consideration of hardware cost and appearance size, the operation of the multi-channel video cache is realized by controlling a group of DDR3 to read and write through the FPGA. For different application requirements, some display processing systems need low video transmission delay, and only need to buffer 1 frame of video signals, some display processing systems need stable video transmission without frame loss, and some display processing systems need to buffer 3 frames or more of video signals.
How to control the caching mode of the memory according to the caching requirements of different video signals is a technical problem to be solved by the application.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a DDR3 video cache control method based on an FPGA, so as to at least solve the above-mentioned video signal cache problem.
In order to achieve the above object, the present invention provides a DDR3 multi-channel video cache control method based on an FPGA, which includes:
s1, acquiring multiple paths of input videos, wherein the memory value of each path of input video in the multiple paths of input videos is distributed according to the video frame number of the path of video;
s2, generating a corresponding request signal group according to the multi-channel input video data;
and S3, processing the request signal group according to priority arbitration logic, and correspondingly reading or storing one or more paths of video data of the paths of video data corresponding to the request signal group according to the memory value.
Preferably, the generating a corresponding request signal group according to the multiple input video data includes:
caching the multi-channel input video data according to the corresponding video frame number corresponding to the input demand information; the writing depth of the cache is at least a preset multiple of the resolution line number of the video data corresponding to the cache.
Preferably, the generating of the corresponding request signal group according to the multiple input video data may further be selected as:
the multi-path input video data is cached through a write FIFO, and then read out and written into a DDR3 memory to generate a corresponding write request signal group;
reading out and writing the multi-channel video data from a DDR3 memory into a read FIFO cache, reading out the data from the read FIFO and outputting the data to generate a corresponding read request signal group;
the data writing depth of the writing FIFO and the reading FIFO is at least a preset multiple of the resolution line number of the corresponding cache video data.
Preferably, the priority arbitration logic comprises a plurality of levels of processing logic; and in the processing logic of each level, when a second condition is met, returning to an idle state, and ending the execution of the processing logic of the level.
Preferably, the request signal group comprises a write request signal group and a read request signal group; the generating a corresponding request signal group according to the multi-channel input video data comprises:
buffering the multi-path input video data: generating a corresponding write request signal group when the readable video data count value corresponding to the video data of the channel is confirmed to meet a first preset condition;
reading multiple input video data: and generating a corresponding read request signal group when the written video data count value corresponding to the video data of the channel is confirmed to meet a second preset condition.
Preferably, the memory value includes a write control address and a read control address; the write control address and the read control address both comprise a base address and an incremental address; the base address and the increment address are associated with each other, and the operand value of each writing or reading of the increment address is cleared after the operation of reading or writing a frame of video data.
Preferably, the memory value of each input video in the multiple input videos is allocated according to the video frame number of the video, and the allocating includes:
dividing an n +1 block memory space in a memory according to the number n of video frames of an input video needing to be cached, wherein the memory space in each block is more than or equal to the memory space required by caching one frame data of the video.
Preferably, the boundary value of each block memory space except the end is used as a base address, and the base address comprises a writing base address and a reading base address;
the writing base address is switched to the next adjacent boundary value after the video data finishes writing a frame, and the reading base address is switched to the next adjacent boundary value after the video data finishes reading a frame; the start value of the read base address is a next adjacent boundary value of the start value of the write base address.
Preferably, the second condition is satisfied: the video data count value can be read from the write FIFO or the video data count value written by the read FIFO is greater than or equal to 1/8 of the video data resolution line value.
Preferably, the first preset condition is satisfied: the count value of video data read from the write FIFO is greater than or equal to 1/8 of the resolution line value of the video data.
Preferably, the second preset condition is satisfied: the path of video data is read out from the memory cache, and the count value of the written video data correspondingly written in the write-read FIFO is less than or equal to 2 times of the resolution line value of the video data.
Through the technical scheme, the read address and the write address are subjected to hierarchical management through the preset processing priority, and the finished judgment condition is set in each level, so that the caching requirements (caching control of 1 frame, 2 frames and 3-multiframe) of different video signals of the input video can be realized, the method for changing the caching of different frame numbers is simple and convenient, the frame caching mode can be easily designed to be selectable, and the user can conveniently solve the problems under different application requirements.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a general hardware block diagram of an application of a DDR3 video cache control method based on an FPGA according to an embodiment of the present invention;
fig. 2 is a system schematic block diagram of a DDR3 video cache control method based on an FPGA according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating read-write logic control of a DDR3 video cache control method based on an FPGA according to an embodiment of the present invention;
fig. 4 is a schematic base address partition diagram of a DDR3 video cache control method based on an FPGA according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
The embodiment provides a DDR3 video cache control method based on an FPGA, which comprises the following steps:
s1, acquiring multiple paths of input videos, wherein the memory value of each path of input video in the multiple paths of input videos is distributed according to the video frame number of the path of video;
s2, generating a corresponding request signal group according to the multi-channel input video data;
and S3, processing the request signal group according to priority arbitration logic, and correspondingly reading or storing one or more paths of video data of the paths of video data corresponding to the request signal group according to the memory value.
Preferably, the corresponding request signal group is generated according to the multiple paths of input video data, and the multiple paths of input video data are cached according to the corresponding video frame numbers corresponding to the input demand information; the writing depth of the cache is at least a preset multiple of the resolution line number of the video data corresponding to the cache.
Preferably, the generating the corresponding request signal group according to the multiple input video data may further include:
the multi-path input video data is cached through a write FIFO, and then read out and written into a DDR3 memory to generate a corresponding write request signal group;
the write FIFO has a write data bit width of 32 bits and a read data bit width of 256 bits;
reading out and writing the multi-channel video data from a DDR3 memory into a read FIFO cache, reading out the data from the read FIFO and outputting the data to generate a corresponding read request signal group; the bit width of the write-in data of the read FIFO is 256 bits, and the bit width of the read-out data is 32 bits;
the data writing depth of the writing FIFO and the reading FIFO is at least a preset multiple of the resolution line number of the corresponding cache video data.
Preferably, the priority arbitration logic comprises a plurality of levels of processing logic; and in the processing logic of each level, when a second condition is met, returning to an idle state, and ending the execution of the processing logic of the level.
Preferably, the request signal group comprises a write request signal group and a read request signal group; the generating a corresponding request signal group according to the multi-channel input video data comprises:
buffering the multi-path input video data: generating a corresponding write request signal group when the readable video data count value corresponding to the video data of the channel is confirmed to meet a first preset condition;
reading multiple input video data: and generating a corresponding read request signal group when the written video data count value corresponding to the video data of the channel is confirmed to meet a second preset condition.
Preferably, the second condition is satisfied: the video data count value can be read from the write FIFO or the video data count value written by the read FIFO is greater than or equal to 1/8 of the video data resolution line value. The DDR3 is read and written in the memory operation, which is based on the number of lines of video resolution, i.e. one line of data at video resolution is written into the DDR3 for each write operation, and one line of data at video resolution is read for each read out of the DDR 3. The burst length of the DDR3 is 8, that is, the DDR3 address will automatically and continuously increment by 8 bits in length in each read and write operation, so that the data of one line of the read and write video resolution only needs to read and write 1/8 of the line value of the resolution in the DDR 3.
Preferably, the first preset condition is satisfied: the count value of video data read from the write FIFO is greater than or equal to 1/8 of the resolution line value of the video data. When the bit width of the write FIFO data port is 32 bits, the bit width of the read data is 256 bits, and the count value of the readable data in the write FIFO is 1/8 of the video resolution, it indicates that video data of one line of the video resolution has been written in the FIFO.
Preferably, the second preset condition is satisfied: the path of video data is read out from the memory cache, and the count value of the written video data correspondingly written in the write-read FIFO is less than or equal to 2 times of the resolution line value of the video data. Setting to 2 guarantees that the read video data stream is not interrupted.
As shown in fig. 1 and fig. 2, the method is preferably implemented by using an FPGA-based DDR3 video cache control system, where the FPGA-based DDR3 video cache control system includes: FIFO memory, read-write controller and memory device;
further, the FIFO memory and the read-write controller are preferably realized by PGA; the memory is preferably selected from two external DDR3 memories, the data bit width of the single DDR3 is 16bit, the two DDR3 form 32bit data bit width, and the storage capacity of the DDR3 is suitable for selecting the size of the video needing to be cached. The FPGA input 3 video signals conform to the Vesa standard, which includes Hsync (row signal), Vsync (field signal), DE (enable signal), RGB (three component data signals of red, green, and blue). The 3 output video signals have the same format as the corresponding input video signals, and 3 input video signals can use different resolution formats.
The FPGA is based on a 7-series FPGA of Xilinx company, at least can be externally connected with two DDR3 with the bit width of 16 bits, and the read-write control of the DDR3 is based on an MIG IP core provided by the Xilinx company.
As shown in fig. 2, the read/write controller includes a logic control unit and a MIG IP unit, and the FIFO memory includes a write FIFO unit and a read FIFO unit; the Write FIFO unit comprises a Write _ FIFO _1, a Write _ FIFO _2 and a Write _ FIFO _3, and the FIFO is asynchronous in reading and writing; the Read FIFO elements include Read _ FIFO _1, Read _ FIFO _2, and Read _ FIFO _3, which are Read-write asynchronous FIFOs. The input Video data includes Video _ In1, Video _ In2, and Video _ In3, which are written into 3 write FIFOs when their DE signals are high, respectively; the output Video data includes Video _ out1, Video _ out2, and Video _ out3 reading data from the 3 read FIFOs at DE high level under the same driving signal as the input Video resolution; the write depth of the FIFO is at least set to be 2 times of the line number of the write video resolution, the data bit width is 32 bits, the write FIFO is enabled to be an rd _ data _ count port, and the read FIFO is enabled to be a wr _ data _ count port. Preferably, a storage space in the memory corresponding to the memory write control address and the memory read control address is greater than or equal to a storage space corresponding to one frame of data of the video data.
Further, the FIFO memory is configured to buffer Video data, and specifically, after the three paths of Video data are written into the FIFO memory, when the readable Video data count value of the write FIFO port rd _ data _ count is greater than or equal to 1/8 of the resolution line value of the write Video _ In1, the write FIFO unit generates a write request signal group, where the write request signal group includes a W _ RQ1 write request signal, a W _ RQ2 write request signal, and a W _ RQ3 write request signal; wherein the W _ RQ1, W _ RQ2, and W _ RQ3 write request signals are active high and inactive low otherwise.
When reading and writing the read FIFO from the DDR3 memory, when the written video data count value of the read FIFO port wr _ data _ count is less than or equal to 2 times of the read video resolution line value, generating a read request signal group, an R _ RQ1 read request signal, an R _ RQ2 read request signal and an R _ RQ3 read request signal; wherein, the R _ RQ1 read request signal, the R _ RQ2 read request signal and the R _ RQ3 read request signal are active high, otherwise, the R _ RQ1 read request signal is inactive low.
Specifically, the preset processing priority includes: write priority levels (W _ RQ1 write request signal, W _ RQ2 write request signal, and W _ RQ3 write request signal) and read priority levels (R _ RQ1 read request signal, R _ RQ2 read request signal, and R _ RQ3 read request signal); the write priority level is higher than the read priority level (priority ordered from high to low: W _ RQ1> W _ RQ2> W _ RQ3> R _ RQ1> R _ RQ2> R _ RQ 3). The read-write request arbitration module in the logic control unit carries out priority arbitration on the input W _ RQ1 write request signal, W _ RQ2 write request signal, W _ RQ3 write request signal, R _ RQ1 read request signal, R _ RQ2 read request signal and R _ RQ3 read request signal, thereby judging whether the next read operation or the next write operation is carried out on the DDR 3. The address bus outputting to the MIG IP is switched to the read address Rd _ Addr or the write address Wr _ Addr according to the currently in read or write state. During Write operation, enabling a data read enabling port of the corresponding Write _ FIFO _1-3 in the Write FIFO unit, outputting external input video data buffered in the FIFO to a MIG IP core, and then storing the external input video data into DDR3 according to the address; and during reading operation, enabling the data write enable port of the corresponding Read _ FIFO _1-3 in the Read FIFO unit, transmitting the data of the corresponding address in the DDR3 to the MIG IP core, and then reading the data into the FIFO unit to output video data.
As shown in fig. 3, the three-way video data independent judgment includes 3 Read state control logics Read1, Read2, Read3, and the Write control includes 3 Write state control logics Write1, Write2, Write 3. And respectively entering corresponding read and write control states according to the results of the read and write request conditions. After the DDR3 is initialized (flag bit DDR-init-done is 1), the MIG IP output signal DDR _ init _ done is at a high level, whether W _ RQ1, W _ RQ2, and W _ RQ3 are at a high level (for example, W _ RQ1 is 1) is determined in sequence from high to low according to the priority of Read and Write requests, and if the requirements are met by corresponding W _ RQ1-3(W _ RQ1, W _ RQ2, W _ RQ3) or R _ RQ1-3(R _ RQ1, R _ RQ2, and R _ RQ3), the MIG status is respectively entered into corresponding Read status (Read1, Read2, Read3) or Write status (Write1, Write2, Write 3). 1/8 if the video data read count or the video data written count in the buffer is greater than or equal to the video data resolution line value; and returning to the idle state, and finishing the execution of the processing logic of the level. Specifically, when the Video data is In the write state (Read1, Read2, Read3), if the written Video data count value, such as the number of operations (Wr _ cnt1, Wr _ cnt2, Wr _ cnt3) for writing the DDR3, satisfies 1/8 that is greater than or equal to the resolution line value (W-len1, W-len2, W-len3) of the written Video (Video _ In1, Video _ In2, Video _ In3), the write state ends and returns to the Idle state;
when in the Read state (Read1, Read2, Read3), if the readable Video data count value, such as the number of operations Read from DDR3 (Rd _ cnt1, Rd _ cnt2, Rd _ cnt3), satisfies 1/8 that is greater than or equal to the resolution line value (R-len1, R-len2, R-len3) of the output Video (Video _ Out1, Video _ Out2, Video _ Out3), the Read state ends. When not satisfied, the Idle state Idle is returned. It should be noted that, as shown in fig. 3 and fig. 1, the explanations in parentheses are provided to avoid repetitive writing of the same logic.
As shown in fig. 4, preferably, the memory value includes a write control address and a read control address; the write control address and the read control address both comprise a base address and an incremental address; the base address and the increment address are associated with each other, and the operand value of each writing or reading of the increment address is cleared after the operation of reading or writing a frame of video data. The memory value of each path of input video in the multi-path input video is distributed according to the video frame number of the path of video, and the method comprises the following steps: dividing an n +1 block memory space in a memory according to the number n of video frames of an input video needing to be cached, wherein the memory space in each block is more than or equal to the memory space required by caching one frame data of the video. Taking the boundary value of each block memory space except the end as a base address, wherein the base address comprises a writing base address and a reading base address; the writing base address is switched to the next adjacent boundary value after the video data finishes writing a frame, and the reading base address is switched to the next adjacent boundary value after the video data finishes reading a frame; the start value of the read base address is a next adjacent boundary value of the start value of the write base address.
Specifically, after the read or write state is performed, the read address generation module or the write address generation module generates a memory read control address Rd _ Addr or a memory write control address Wr _ Addr of the DDR3, respectively. The memory write control address Wr _ Addr includes two parts, namely a write base address (Wr _ base _ Addr) and a write increment address (Wr _ Incr _ Addr), and the memory read control address Rd _ Addr includes two parts, namely a read base address (Rd _ base _ Addr) and a write increment address (Rd _ Incr _ Addr). The write increment address is subjected to the write operation value accumulation 8 each time, the read increment address is subjected to the read operation value accumulation 8 each time, the Wr _ Incr _ Addr is cleared after one frame of video operation is written, and the Rd _ Incr _ Addr is cleared after one frame of video operation is read. As shown in fig. 4, each path of video in the DDR3 memory is divided into 3 block addresses as base addresses for read and write operations; the three paths of Video _ In1, Video _ In2 and Video _ In3 have the same memory space. Taking the input Video _ In1 as an example, the memory space starts with V _ Start _ Addr, and divides into 4 block address spaces with V1_ B0_ Addr, V1_ B1_ Addr, and V1_ B2_ Addr as boundary values, the storage spaces between two adjacent boundary values have the same size, and the minimum value of the address spaces is the data size required for buffering one frame of the input Video _ In 1. The three paths of Video data are Video _ In1, Video _ In2 and Video _ In3 which respectively correspond to 3-frame, 2-frame or 1-frame cache of Video; and independently switching the read and write operation base addresses when the video is input and output. Taking 3-frame cache as an example, the base address Rd _ base _ Addr value is controlled to switch from the sequence of V1_ B0_ Addr, V1_ B1_ Addr and V1_ B2_ Addr to V _ Start _ Addr during read operation; and controlling the sequential switching of the base address Wr _ base _ Addr from V _ Start _ Addr, V1_ B0_ Addr, V1_ B1_ Addr to V1_ B2_ Addr in write operation. Controlling the base address of the read operation to be permanently far at the next adjacent boundary value of the address of the write operation, and if the Rd _ base _ Addr is V1_ B0_ Addr, the Wr _ base _ Addr is V _ Start _ Addr; and when the Rd _ base _ Addr is V _ Start _ Addr, the Wr _ base _ Addr is V1_ B2_ Addr. If the two memory addresses are divided by the cache 1 frame, the control mode of the memory addresses in the cache 2 frame divided 3 blocks is similar to that of the cache control method of the 3 frames, and the details are not repeated here.
Furthermore, the method can be applied to the caching of three paths of videos with different resolutions, the resolutions of the three paths of Video _ In1, Video _ In2 and Video _ In3 are 1920 × 1080, 1024 × 768 and 1280 × 1024 respectively, and then the 1 st Video write request W _ RQ1 is set to be high when the count value rd _ data _ count1 of the readable data In the write FIFO _1 is more than or equal to 240; when the count value rd _ data _ count2 of the readable data in the write FIFO _2 is more than or equal to 128, the 2 nd video write request W _ RQ2 is set to be high level; when the count value rd _ data _ count3 of the data readable in the write FIFO _3 is greater than or equal to 160, the 3 rd video write request W _ RQ3 is set to high level. After the system is powered on to work, the read requests R _ RQ1, R _ RQ2 and R _ RQ3 simultaneously meet the requirement of setting high level, and the read-write arbitration module firstly reads the 1 st path of video and then reads the 2 nd path of video and the 3 rd path of video according to the priority. And after the write request is satisfied, performing write operation control according to the flow chart of fig. 3. In order to ensure the read-write bandwidth of DDR3, the DDR3 working rate of MIG IP is set to 800MHz, so that the common Vesa time sequence resolution can be suitable for the method to realize data caching.
Furthermore, the reading and writing operations all use the line number of the video resolution as a basic unit, at least 1 line of data is written in each writing operation, 1 line of data is read in the reading operation, the reading and writing addresses of each path of video are divided in the DDR3 memory according to the frame number, the independence of the reading and writing operations of each path of video is ensured, and the independence is not influenced. The read-write address is divided into a base address and an incremental address, and the base address is switched into different memory address areas during read-write operation, so that multi-frame selectable caching of the video is realized.
The invention realizes the caching of at least 3 paths of videos with different resolutions, is suitable for the relationship between the input video clock rate and the DDR3 operation rate, and can be expanded into more than 3 paths of video caching on the basis.
Those skilled in the art will appreciate that all or part of the steps in the method for implementing the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention. It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as disclosed in the embodiments of the present invention as long as it does not depart from the spirit of the embodiments of the present invention.
Claims (11)
1. A DDR3 multi-path video cache control method based on an FPGA is characterized by comprising the following steps:
s1, acquiring multiple paths of input videos, wherein the memory value of each path of input video in the multiple paths of input videos is distributed according to the video frame number of the path of video;
s2, generating a corresponding request signal group according to the multi-channel input video data;
and S3, processing the request signal group according to priority arbitration logic, and correspondingly reading or storing one or more paths of video data of the paths of video data corresponding to the request signal group according to the memory value.
2. The multi-channel video buffer control method according to claim 1, wherein said generating a corresponding set of request signals according to the multi-channel input video data comprises:
caching the multi-channel input video data according to the corresponding video frame number corresponding to the input demand information; the writing depth of the cache is at least a preset multiple of the resolution line number of the video data corresponding to the cache.
3. The multi-channel video buffer control method according to claim 1, wherein said generating a corresponding set of request signals according to the multi-channel input video data comprises:
the multi-path input video data is cached through a write FIFO, and then read out and written into a DDR3 memory to generate a corresponding write request signal group;
reading out and writing the multi-channel video data from a DDR3 memory into a read FIFO cache, reading out the data from the read FIFO and outputting the data to generate a corresponding read request signal group;
the data writing depth of the writing FIFO and the reading FIFO is at least a preset multiple of the resolution line number of the corresponding cache video data.
4. The multi-channel video cache control method according to claim 2 or 3, wherein the priority arbitration logic comprises a plurality of levels of processing logic; and in the processing logic of each level, when a second condition is met, returning to an idle state, and ending the execution of the processing logic of the level.
5. The multi-channel video cache control method according to claim 2, wherein the request signal group comprises a write request signal group and a read request signal group; the generating a corresponding request signal group according to the multi-channel input video data comprises:
buffering the multi-path input video data: generating a corresponding write request signal group when the readable video data count value corresponding to the video data of the channel is confirmed to meet a first preset condition;
reading multiple input video data: and generating a corresponding read request signal group when the written video data count value corresponding to the video data of the channel is confirmed to meet a second preset condition.
6. The multi-channel video cache control method according to claim 2, wherein the memory value comprises a write control address and a read control address; the write control address and the read control address both comprise a base address and an incremental address; the base address and the increment address are associated with each other, and the operand value of each writing or reading of the increment address is cleared after the operation of reading or writing a frame of video data.
7. The method as claimed in claim 5, wherein the step of allocating the memory value of each input video in the multiple input videos according to the video frame number of the input video comprises:
dividing an n +1 block memory space in a memory according to the number n of video frames of an input video needing to be cached, wherein the memory space in each block is more than or equal to the memory space required by caching one frame data of the video.
8. The multi-channel video buffering control method according to claim 6,
taking the boundary value of each block memory space except the end as a base address, wherein the base address comprises a writing base address and a reading base address;
the writing base address is switched to the next adjacent boundary value after the video data finishes writing a frame, and the reading base address is switched to the next adjacent boundary value after the video data finishes reading a frame; the start value of the read base address is a next adjacent boundary value of the start value of the write base address.
9. The multi-channel video buffering control method according to claim 3, wherein the second condition is satisfied: the video data count value can be read from the write FIFO or the video data count value written by the read FIFO is greater than or equal to 1/8 of the video data resolution line value.
10. The method according to claim 4, wherein the first preset condition is satisfied: the count value of video data read from the write FIFO is greater than or equal to 1/8 of the resolution line value of the video data.
11. The method according to claim 4, wherein the second predetermined condition is satisfied: the path of video data is read out from the memory cache, and the count value of the written video data correspondingly written in the write-read FIFO is less than or equal to 2 times of the resolution line value of the video data.
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