CN116132666B - FPGA-based video image processing method and system - Google Patents
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- H04N7/0105—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level using a storage device with different write and read speed
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- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0125—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level one of the standards being a high definition standard
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- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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Abstract
The invention discloses a video image processing method and a system based on an FPGA, which are realized by a video image processing component based on the FPGA, wherein the video image processing component comprises: the system comprises an FPGA, and a DSP module, a multimode optical module, an external interface module and a storage module which are connected with the FPGA; the invention mainly realizes the acquisition processing function of video images, carries out data link test before starting to acquire image data, and starts data acquisition after the data link meets the conditions, so as to avoid abrupt error reporting and stopping due to data link interruption in the data acquisition processing process, improve the read-write efficiency through the plug-in storage module, provide enough space for complex data processing process through the plug-in storage module under the scene of needing high-performance image processing, and reduce the error reporting and stopping probability of the system.
Description
Technical Field
The invention relates to the technical field of picture processing, in particular to a video image processing method and system based on an FPGA.
Background
Particulate matters or floaters such as tiny water drops in the air or under the liquid level absorb or scatter visible light, so that an image or an image acquired by a video acquisition device is unclear, and subsequent image processing and application scenes are difficult; at this time, fog penetration treatment is required for the image so that the image becomes clear.
In particular, the video or image data collected under the liquid level needs further processing operations such as high-performance defogging conversion to ensure that the definition of the image is convenient for later application, for example, the image collected under water by a submarine or a ship needs to be subjected to corresponding defogging processing by combining with an actual scene, however, if a certain transmission link is wrong in the processing process of collecting defogging of the image, the whole collecting defogging processing process is wrongly stopped, the efficiency and the data quality of the data collecting processing are affected, and in the scene needing high-performance image processing, the system is easy to be wrongly stopped due to the complex data processing process, the occupation of larger space and broadband.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: in the processing processes of image acquisition defogging and the like, if a certain transmission link is wrong, the whole acquisition defogging processing process is wrongly stopped, the efficiency and the data quality of data acquisition processing are affected, and in a scene needing high-performance image processing, the image processing system is easy to wrongly stop due to the fact that the data processing process is complex, and larger space and broadband are occupied; the invention aims to provide a video image processing method and a system based on an FPGA, which are based on the FPGA to set a test process, and carry out a data link test before starting to collect image data, and the data collection is started after the data link meets the conditions, so that the sudden error reporting and stopping caused by the data link interruption in the data collection processing process are avoided, the data collection processing efficiency and the data quality are ensured, and the technical problems are solved.
The invention is realized by the following technical scheme:
the invention provides a video image processing method based on an FPGA, which is realized by a video image processing component based on the FPGA, and the video image processing component comprises: the system comprises an FPGA, and a DSP module, a multimode optical module, an external interface module and a storage module which are connected with the FPGA; the method comprises the following steps:
the FPGA acquires image data acquired by a front-end camera through a multimode optical module, the FPGA processes the image data through a fog penetration algorithm and then sends the processed image data to the DSP module, the DSP module processes the image data through a target recognition and tracking algorithm and then sends the processed result to the FPGA, and the FPGA converts the processed image data into a format or a frame rate and then outputs and displays the processed image data through an external interface module;
carrying out data link test before the FPGA starts to collect image data: and performing verification test on the data link between the DSP module and the FPGA, performing read-write test on the storage module, and performing verification test on the data link between the external interface module and the FPGA.
The FPGA comprises a test unit, wherein the test unit comprises: the system comprises a DSP link test unit for verifying and testing a data link between a DSP module and an FPGA, a storage test unit for performing read-write test on a storage module, and an external interface test unit for verifying and testing a data link between an external interface module and the FPGA.
The working principle of the scheme is as follows: in the existing image processing system, in the high-performance processing process such as image acquisition defogging, when a certain transmission link is wrong, error reporting and stopping can be caused in the whole acquisition defogging processing process, the efficiency and data quality of data acquisition processing are affected, the data processing process is complex in a scene requiring high-performance image processing, and larger space and bandwidth are required to occupy, so that error reporting and stopping can easily occur in the system.
For example, a submarine or a ship needs to perform corresponding fog penetrating processing by combining an actual scene, resolution 1024 x 1024 is required in an image receiving and transmitting process, frame frequency is 25fps, in the image collecting and processing process, due to low definition of images under liquid level, fog penetrating processing is required in real time after video images are collected, a series of operations such as video image collection, image defogging processing and image transmission need to be sequentially and circularly operated, when an image processing system is suddenly terminated, the whole process is stopped, the process is stopped under emergency conditions, a large amount of data can be missed, and meanwhile image processing efficiency and image quality are influenced.
The video image processing component mainly realizes the processing function of an image, and needs to ensure clear output of the image and enough information processing capability, so that the processing part of a digital image target recognition and tracking algorithm is realized by a high-performance DSP, a high-performance multi-core floating point DSP chip is widely applied by virtue of the high-performance multi-core floating point DSP chip in the aspect of digital signal processing, and the application fields of radar signal processing, accurate guidance, electronic countermeasure, sonar detection, secret communication, flight control and the like are related in scope; the logic processing part is processed by the FPGA based on Xilinx, so that errors are not easy to occur in the processing process, and the efficiency and the data quality of data acquisition and processing are improved. In the information equipment, high-speed real-time intelligent processing of information such as electromagnetic waves, images, sound waves and the like is required.
The video image processing assembly based on the FPGA further comprises an EMIF bus and an SRIO channel, command data are transmitted between the FPGA and the DSP module through the EMIF bus, and image data are transmitted between the FPGA and the DSP module through the SRIO channel.
The further optimization scheme is that the DSP link test unit comprises an SRIO test module and an EMIF bus test module to realize verification test of a data link between the DSP module and the FPGA;
in SRIO test mode: the DSP module sends a packet of data to the FPGA through an SRIO channel, the packet of data is ended by the DOORBELL DOORBELL, the FPGA uses the FIFO to buffer the received data, after detecting that the single packet of data is ended by the DOORBELL DOORBELL, the SRIO test module returns the FIFO buffered data to the DSP module in a primary way, the sending of the packet of data is completed by the DOORBELL DOORBELL, and the DSP module performs data verification work after receiving the data;
the EMIF bus function comprises the steps of issuing an FPGA test instruction, and uploading state information by the FPGA;
in EMIF bus test mode: and configuring a plurality of test registers in a special register address space of the FPGA, writing register values by the DSP module through an EMIF bus, performing a read-back function on all the written test registers by the EMIF bus test module, and performing data verification and link accuracy verification by reading corresponding registers through the written registers by the DSP module.
The further optimization scheme is that the external interface module comprises an HDMI output interface, a GPIO interface and a USB3.0 interface, wherein the HDMI output interface supports resolution 1920x1080 and frame rate 60fps.
And after the image data processed by the FPGA is converted into an HDMI format by adopting a special HDMI video interface chip ADV7511, the image data is output by adopting a standard HDMI socket through the special video interface chip.
The further optimization scheme is that the storage module is a double read-write channel DDR3, and the double read-write channel DDR3 comprises an interface module and a control module; the control module includes: multiplexing circuit module, DDR3 controller and DDR3 chip.
The interface module is used as an interface facing the FPGA, and is connected with the multiplexing circuit module to realize interaction of data information and configuration information; the multiplexing circuit module realizes conversion from a double read-write port to a single read-write port, and the DDR3 controller is used for writing data into and reading data from the DDR3 chip.
In the image processing method, besides image acquisition processing, a transmission link of image data is required to be tested, and the load of a suitcase processing hardware system is increased by the operation, so that the double read-write channel DDR3 is hung outside the FPGA to serve as an image cache, the double read-write channel DDR3 is convenient for caching high-speed image data, when the DSP module completes tracking processing functions such as cursor increasing, scribing, time and the like of images, the double read-write channel DDR3 is not required, and when the functions such as fog penetrating and the like are completed by the FPGA, the double read-write channel DDR3 is required to be used.
Along with the rapid development of high-speed image processing technology, in the process of realizing an image algorithm, a large amount of data is often required to be processed in real time to prevent an image processing system from suddenly reporting errors, so that a high-speed data buffer DDR3 is adopted as a real-time data buffer tool, and due to the characteristics of DDR3, an IP core for controlling the reading and writing of DDR3 can only support a set of reading and writing interfaces, and cannot simultaneously read and write. In order to make up for the defect, the double read-write channel DDR3 designed by the scheme fully improves the read-write efficiency of DDR 3; meanwhile, read-write operation on DDR3 can be realized by combining an external buffer FIFO, and under the scene of needing high-performance image processing, the double read-write channel DDR3 can provide enough space for a complex data processing process, so that the error reporting stop probability of a system is reduced.
The multiplexing circuit module comprises a data switcher and two independent read-write interfaces, wherein the data switcher enables the two independent read-write interfaces to be connected with the DDR3 controller in a time-sharing mode, and each set of read-write interface is responsible for reading and writing two tasks. Correspondingly, the interface module also comprises two independent read-write interfaces, each set of read-write interface is provided with a configuration port and a data port for realizing the connection of the interface module and the multiplexing circuit module to realize the interaction of data information and configuration information, and the interface module is a source for initiating read-write operation; the multiplexing circuit module comprises 4 FIFOs and is used for temporarily caching data of the double read-write channel DDR3.
The further optimization scheme is that the task states of the defined read-write interface are respectively as follows: port10 writes data tasks, port11 reads data tasks, port20 writes data tasks, port21 reads data tasks; the configuration information comprises execution instructions corresponding to the states of the read-write interfaces one by one. The instructions configured by the interface module determine which instructions are executed, a plurality of instruction tasks can be issued at the same time, and the tasks are executed in turn by a time division multiplexing round robin mechanism so as to achieve the effect of simultaneous reading and writing.
The further optimization scheme is that the system further comprises an idle state and an end state, the idle state determines the task state of the read-write interface according to the configuration information, after the task state is entered, task execution timing is started, after the task execution timing is completed, no matter whether the task state is completed or not, the system jumps to the idle state through an additional end state to complete circulation, so that the 4 task states are prevented from being mutually independent due to establishment of conflicts when being executed.
The further optimization scheme is that the multimode optical module is at least 8 paths, at least 1/4 paths of multimode optical modules are used for receiving and transmitting images, the resolution of the multimode optical modules is 1024 x 1024, and the frame frequency is 25fps.
The scheme also provides a ship-expelling video image processing system which comprises the video image processing assembly based on the FPGA.
The urgent requirements of users on video processing are improved, and a great amount of manpower and material resources are saved for the users; meanwhile, technology accumulation is improved for the Saidi company in the aspect of large-batch image processing.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the video image processing method and the video image processing system based on the FPGA mainly realize the acquisition processing function of video images, carry out data link test before the acquisition of image data is started, and start data acquisition after the data link meets the conditions, so as to avoid abrupt error reporting and stopping due to data link interruption in the data acquisition processing process, improve the read-write efficiency through the plug-in storage module, provide enough space for the complex data processing process through the plug-in storage module under the scene of needing high-performance image processing, and reduce the probability of error reporting and stopping operation of the image processing system.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a schematic diagram of an FPGA-based video image processing assembly;
fig. 2 is a schematic diagram of a dual read/write channel DDR3 structure.
Description of the embodiments
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
The submarine or ship needs to be subjected to corresponding fog penetrating treatment by combining an actual scene, the resolution is 1024 x 1024 in the image receiving and transmitting process, the frame frequency is 25fps, in the image collecting and processing process, due to low definition of the subsurface image, the fog penetrating treatment is required to be performed in real time after the video image is collected, a series of operations such as video image collection, image defogging treatment and image transmission need to be sequentially and circularly operated, when an image processing system is suddenly terminated, the whole process can be stopped, the process is terminated under emergency conditions, a large amount of data can be missed, and meanwhile, the image processing efficiency and the image quality are influenced.
Example 1
The present embodiment provides a video image processing method based on FPGA, which is implemented by a video image processing component based on FPGA, as shown in fig. 1, where the video image processing component based on FPGA includes: the system comprises an FPGA, and a DSP module, a multimode optical module, an external interface module and a storage module which are connected with the FPGA; the FPGA acquires image data acquired by a front-end camera through a multimode optical module, the FPGA firstly converts the received image data into image data such as SCALER, then processes the image data through a fog penetration algorithm and sends the image data to the DSP module, the DSP module processes the image data through a target recognition and tracking algorithm and then sends the processing result to the FPGA, and the FPGA then converts the image data processed through the target recognition and tracking algorithm into format conversion or frame rate conversion and then outputs and displays the image data through an external interface module;
the FPGA comprises a test unit, the test unit performs data link test before the FPGA starts to collect image data, and the test unit comprises: the system comprises a DSP link test unit for verifying and testing a data link between a DSP module and an FPGA, a storage test unit for performing read-write test on a storage module, and an external interface test unit for verifying and testing a data link between an external interface module and the FPGA.
In the embodiment, the data acquisition is started after the data link meets the condition, so that the sudden error reporting stop caused by the data link interruption in the data acquisition processing process is avoided, and the probability of error reporting stop is reduced.
The system also comprises an EMIF bus and an SRIO channel, command data are transmitted between the FPGA and the DSP module through the EMIF bus, and image data are transmitted through the SRIO channel.
The DSP link test unit comprises an SRIO test module and an EMIF bus test module;
in an SRIO test mode, a DSP module sends a packet of data to an FPGA through an SRIO channel, the packet of data is ended by a DOORBELL DOORBELL, the FPGA uses FIFO to buffer the received data, after the SRIO test module detects that the single packet of data ends the DOORBELL DOORBELL, the SRIO test module returns the FIFO buffered data to the DSP module in a primary way, the sending of the packet of data is finished by the DOORBELL DOORBELL, and the DSP module performs data verification after receiving the data;
the external interface module comprises an HDMI output interface, a GPIO interface and a USB3.0 interface, wherein the HDMI output interface supports resolution 1920x1080 and frame rate 60fps. The external interface module further comprises an external serial port, and the corresponding external interface test unit comprises: the HDMI test unit, the GPIO test unit, the serial port test unit and the USB3.0 test unit respectively carry out link test on each external interface.
In the GPIO test mode, the top layer defines GPIO signals as inout, the DSP module issues GPIO test instructions through the EMIF bus, when the test instructions are effective, the GPIO test unit shorts the high-low five-bit GPIO signals, and the DSP module tests the physical link state of the GPIO by checking GPIO receiving and transmitting signals.
The memory module is a double read-write channel DDR3, and as shown in FIG. 2, the double read-write channel DDR3 comprises an interface module and a control module; the control module includes: multiplexing circuit module, DDR3 controller and DDR3 chip;
the interface module is used as an interface facing the FPGA, and is connected with the multiplexing circuit module to realize interaction of data information and configuration information; the multiplexing circuit module realizes conversion from a double read-write port to a single read-write port, and the DDR3 controller is used for writing data into and reading data from the DDR3 chip.
The multiplexing circuit module comprises a data switcher and two independent read-write interfaces, wherein the data switcher enables the two independent read-write interfaces to be connected with the DDR3 controller in a time sharing way, and each set of read-write interface is responsible for reading and writing two tasks.
The task states defining the read-write interface are respectively: port10 writes data tasks, port11 reads data tasks, port20 writes data tasks, port21 reads data tasks; the configuration information comprises execution instructions corresponding to the states of the read-write interfaces one by one.
The system also comprises an idle state and an ending state, wherein the idle state determines the task state of the read-write interface according to the configuration information, after entering the task state, the task execution timing is started, and after the task is timed up, no matter whether the task state is executed or not, the system jumps to the idle state through an additional ending state to complete the circulation.
Besides image acquisition processing, the transmission link of the image data is required to be tested, and the load of the system is increased by the operation, so that the DDR3 of the double read-write channels is convenient for caching high-speed image data when the DSP module finishes tracking processing functions such as adding cursors, scribing and time to the image, the DDR3 of the double read-write channels is not required, and the DDR3 of the double read-write channels is required to be used when the FPGA finishes functions such as fog penetration and the like.
The double read-write channel DDR3 designed by the embodiment fully improves the read-write efficiency of DDR 3; meanwhile, read-write operation on DDR3 can be realized by combining an external buffer FIFO, and under the scene of needing high-performance image processing, the double read-write channel DDR3 can provide enough space for a complex data processing process, so that the error reporting stop probability of a system is reduced.
The multimode optical module is at least 8 paths, at least 1/4 paths of multimode optical modules are used for receiving and transmitting images, the resolution of the multimode optical modules is 1024 x 1024, and the frame frequency is 25fps.
Example 2
The embodiment provides a video image processing system, which comprises the FPGA-based video image processing component in the previous embodiment, wherein the FPGA-based video image processing component mainly realizes an acquisition processing function, the FPGA-based video image processing component runs on FT-M6678 hardware, 2 DSP modules are arranged on the FPGA-based video image processing component, the 2 DSPs adopt the same software, and the DSP chips are externally connected with 2 groups of double read-write channels DDR3. In this embodiment, the dual read/write channel DDR3 is responsible for storing data, so that the accuracy of DDR3 reading/writing is very important.
The SPI (Serial Peripheral Interface ) interface component in the FPGA-based video image processing assembly is a synchronous input-output serial interface module. The component is used for communicating between the processing component and external SPI equipment; the EMIF bus is an interface between an external memory and other units in the chip, and supports two modes of synchronous and asynchronous; the memory space accessed by the EMIF bus is divided into 4 subspaces, which are called CE 0-CE 3 spaces respectively, and the CE0 external NOR FLASH is configured into an asynchronous mode. In addition, one selected from the remaining chip choices communicates with the FPGA, and is also configured in an asynchronous mode.
The GPIO interface is a general IO interface, and a GPIO interface is configured in the project to receive interrupt information from the FPGA as input. When the FPGA transmits data through the EMIF bus and starts to interrupt, the DSP module receives the interrupt and carries out corresponding processing, and the rest GPIO interface between the FPGA and the DSP module is reserved pin and is configured by default.
The double read-write channel DDR3 of the DSP module needs to test the full address space of DDR3, and the increment number and the write constant (0 x5a5a5a5a, 0xa5a5a5a 5) of the double read-write channel DDR3 are tested.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (4)
1. A method of FPGA-based video image processing, the method being implemented in dependence on an FPGA-based video image processing component comprising: the system comprises an FPGA, and a DSP module, a multimode optical module, an external interface module and a storage module which are connected with the FPGA; the method comprises the following steps:
the FPGA acquires image data acquired by a front-end camera through a multimode optical module, the FPGA processes the image data through a fog penetration algorithm and then sends the processed image data to the DSP module, the DSP module processes the image data through a target recognition and tracking algorithm and then sends the processed result to the FPGA, and the FPGA converts the processed image data into a format or a frame rate and then outputs and displays the processed image data through an external interface module;
carrying out data link test before the FPGA starts to collect image data: performing verification test on a data link between the DSP module and the FPGA, performing read-write test on the storage module, and performing verification test on a data link between the external interface module and the FPGA;
command data are transmitted between the FPGA and the DSP module through an EMIF bus, and image data are transmitted between the FPGA and the DSP module through an SRIO channel;
the method for verifying and testing the data link between the DSP module and the FPGA comprises the following steps:
in SRIO test mode: the DSP module sends a packet of data to the FPGA through the SRIO channel, the packet of data is ended by the DOORBELL DOORBELL, the FPGA uses the FIFO to buffer the received data, after detecting that the single packet of data is ended by the DOORBELL DOORBELL, the FIFO buffers the data to be sent to the DSP module in a primary way, the packet of data is sent to be ended by the DOORBELL DOORBELL, and the DSP module performs data verification after receiving the data;
in EMIF bus test mode: a plurality of test registers are configured in a special register address space of the FPGA, a DSP module writes register values through an EMIF bus, a read-back function is performed on all the written test registers, and the DSP module reads corresponding registers through the written registers to perform data verification and verify link accuracy;
the memory module is a double read-write channel DDR3, and the double read-write channel DDR3 comprises an interface module and a control module; the control module includes: multiplexing circuit module, DDR3 controller and DDR3 chip;
the interface module is used as an interface facing the FPGA, and is connected with the multiplexing circuit module to realize interaction of data information and configuration information; the multiplexing circuit module realizes the conversion from the double read-write ports to the single read-write ports, and the DDR3 controller is used for writing data into and reading data from the DDR3 chip;
the multiplexing circuit module comprises a data switcher and two independent read-write interfaces, the data switcher enables the read two independent read-write interfaces to be connected with the DDR3 controller in a time-sharing way, and each set of read-write interface is responsible for reading and writing two tasks;
the task states defining the read-write interface are respectively: port10 writes data tasks, port11 reads data tasks, port20 writes data tasks, port21 reads data tasks; the configuration information comprises execution instructions corresponding to the states of the read-write interfaces one by one;
the system also comprises an idle state and an ending state, wherein the idle state determines the task state of the read-write interface according to the configuration information, after entering the task state, the task execution timing is started, and after the task is timed up, no matter whether the task state is executed or not, the system jumps to the idle state through an additional ending state to complete the circulation.
2. The FPGA-based video image processing method of claim 1, wherein the external interface module comprises an HDMI output interface, a GPIO interface, and a USB3.0 interface, the HDMI output interface supporting a resolution of 1920x1080 and a frame rate of 60fps.
3. The method for processing video images based on an FPGA of claim 1, wherein the multimode optical module has at least 8 channels; at least 1/4 path multimode optical module is used for receiving and transmitting images, the resolution of the multimode optical module is 1024 x 1024, and the frame frequency is 25fps.
4. A FPGA-based video image processing system for implementing the video image processing method of any one of claims 1-3.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009187301A (en) * | 2008-02-06 | 2009-08-20 | Tokai Rika Co Ltd | Storage medium access apparatus and storage medium access method |
| CN106886177A (en) * | 2016-12-16 | 2017-06-23 | 北京华航无线电测量研究所 | A kind of Radar Signal Processing System |
| CN109815073A (en) * | 2019-01-21 | 2019-05-28 | 成都能通科技有限公司 | A kind of test method of the High Speed Serial SRIO based on PXI platform |
| CN112073650A (en) * | 2020-09-16 | 2020-12-11 | 中航华东光电有限公司 | DDR3 video cache control method based on FPGA |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101839974B (en) * | 2010-05-05 | 2012-11-14 | 北京航空航天大学 | Dual-interface radar data recorder |
| US8650437B2 (en) * | 2010-06-29 | 2014-02-11 | International Business Machines Corporation | Computer system and method of protection for the system's marking store |
| CN103279125B (en) * | 2013-05-27 | 2015-05-13 | 哈尔滨工业大学 | Response simulation and test equipment for CPCI (Compact Peripheral Component Interconnect) bus missile-borne components and implementation method of response simulation and test equipment |
| US9825842B2 (en) * | 2013-12-23 | 2017-11-21 | Bae Systems Information And Electronic Systems Integration Inc. | Network test system |
| CN108322706B (en) * | 2018-02-08 | 2019-02-05 | 广州波视信息科技股份有限公司 | A kind of high-definition signal processing unit and its method application |
| CN108848285A (en) * | 2018-02-08 | 2018-11-20 | 广州波视信息科技股份有限公司 | A kind of high-definition camera processing system for video and method |
| CN109167959B (en) * | 2018-09-07 | 2020-04-03 | 浙江大华技术股份有限公司 | Video acquisition equipment, system and video signal transmission method |
| CN109873998B (en) * | 2019-02-25 | 2022-06-28 | 苏州长风航空电子有限公司 | Infrared video enhancement system based on multi-level guide filtering |
| CN111929717A (en) * | 2020-07-24 | 2020-11-13 | 北京航空航天大学 | Satellite-borne image processor and processing method for remote sensing image target characteristic identification |
| CN112630631B (en) * | 2020-12-22 | 2023-04-18 | 北京时代民芯科技有限公司 | 1553B communication test method for digital signal processing micro system |
| CN113709399B (en) * | 2021-08-31 | 2024-03-08 | 中国电子科技集团公司第五十八研究所 | Visual target tracking system based on DSP+FPGA |
| CN114624564B (en) * | 2022-01-14 | 2024-09-10 | 中国人民解放军国防科技大学 | Portable chip testing method and device based on FPGA |
| CN115422048A (en) * | 2022-08-22 | 2022-12-02 | 曙光信息产业股份有限公司 | Link stability testing method and device, computer equipment and storage medium |
-
2023
- 2023-04-13 CN CN202310389037.7A patent/CN116132666B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009187301A (en) * | 2008-02-06 | 2009-08-20 | Tokai Rika Co Ltd | Storage medium access apparatus and storage medium access method |
| CN106886177A (en) * | 2016-12-16 | 2017-06-23 | 北京华航无线电测量研究所 | A kind of Radar Signal Processing System |
| CN109815073A (en) * | 2019-01-21 | 2019-05-28 | 成都能通科技有限公司 | A kind of test method of the High Speed Serial SRIO based on PXI platform |
| CN112073650A (en) * | 2020-09-16 | 2020-12-11 | 中航华东光电有限公司 | DDR3 video cache control method based on FPGA |
Non-Patent Citations (1)
| Title |
|---|
| 多处理器高速数据传输互联技术的设计与实现;高丽丽;张海滨;;仪器仪表用户(第02期) * |
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