CN107608654B - Transmission control device and method for multi-path asynchronous information - Google Patents
Transmission control device and method for multi-path asynchronous information Download PDFInfo
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Abstract
A transmission control device for multipath asynchronous information, comprising: the data integrator is connected with the memory module and the processor interface and comprises at least two ping-pong operation modules, the data integrator is used for receiving and integrating external output multi-path asynchronous information to obtain a path of integration information, the asynchronous information comprises asynchronous data and asynchronous control signals, and the integration information comprises integration data and synchronous control signals; the memory module is used for reading and/or writing the integrated data according to the synchronous control signal; and the processor interface is connected with the data integrator, the memory module and an external processor and is used for acquiring the integration information output by the data integrator and acquiring the integrated data written in the memory module. The invention also provides a corresponding method. The invention is suitable for a pipeline algorithm, realizes seamless buffering and processing of asynchronous information, can save buffering space and achieves the effect of processing high-speed data stream by a low-speed module.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a transmission control device and method for multiple paths of asynchronous information.
Background
With the advent of the big data era and the increasing demand of people for various information in life, data acquisition is more and more widely applied to the aspects of life, education, scientific research and the like. With the development of the technology, the fineness of the obtained data is gradually increased, and meanwhile, the amount of uncompressed data is also larger and larger, which puts forward a higher and higher requirement on the control speed and the transmission speed of a data interface.
In the prior art, data transmission and control thereof are generally performed in the following manner. Firstly, data at the upper computer end is written into an SRAM of the FPGA in a fixed byte mode by using the external clock frequency, and then the data is transmitted to a processor for processing by using the internal clock frequency of the system.
The method has the following disadvantages: when data are read into the processor in the system, the data can be read only after the upper computer end finishes writing the SRAM, so that a long waiting period exists, and the speed is slow; the incoming data are directly transmitted to the processor, so that the processor can only process the current incoming data, and the previous data are not stored; meanwhile, the system flow is too simple, and the requirement of a more complex system on data flow control is difficult to meet.
Disclosure of Invention
Technical problem to be solved
The present invention is directed to a transmission control apparatus and method for multiple paths of asynchronous information, so as to solve at least one of the above technical problems.
(II) technical scheme
The invention provides a transmission control device of multi-channel asynchronous information, which comprises a data integrator, a memory module and a processor interface, wherein,
the data integrator is connected with the memory module and the processor interface and comprises at least two ping-pong operation modules, the data integrator is used for receiving and integrating external output multi-path asynchronous information to obtain a path of integration information, the asynchronous information comprises asynchronous data and asynchronous control signals, the integration information comprises integration data and synchronous control signals, and the number of the ping-pong operation modules is consistent with that of the multi-path asynchronous information;
the memory module is used for reading and/or writing the integrated data according to the synchronous control signal;
and the processor interface is connected with the data integrator, the memory module and an external processor and is used for acquiring the integration information output by the data integrator and acquiring the integrated data written in the memory module.
In some embodiments of the invention, the ping-pong manipulation module comprises: the device comprises an input data selector, an output data selector and at least two first-in first-out arrays, wherein the input data selector is used for selecting one first-in first-out array to cache one path of asynchronous data in the multi-path asynchronous data; and the output data selector is used for selecting the other first-in first-out arrays except the first-in first-out array while caching a path of asynchronous data in the input data selector, reading the cached asynchronous data, and synchronously processing and splicing the read asynchronous data to obtain a path of integrated data.
In some embodiments of the invention, the data integrator further comprises: and the control signal synchronization unit comprises registers with the same number as the ping-pong operation modules, the registers record corresponding multi-channel asynchronous control signals, and when each register is in a recording state, a channel of synchronous control signals is output and the recording state in each register is deleted.
In some embodiments of the invention, the synchronization control signal comprises: a line synchronization signal, a start synchronization signal, a line count signal, a frame count signal, an end signal, a write control level signal, a write start signal, a write initial address, a write length, a read control level signal, a read start signal, a read initial address, and a read length.
In some embodiments of the invention, the memory module comprises: the signal controller is connected with the data integrator and is used for acquiring the integration information; and the read-write controller reads and/or writes the integrated data to the memory according to the synchronous control signal in the integrated information.
In some embodiments of the invention, further comprising: and the transmission module comprises a plurality of transmission units, the transmission module is used for receiving the multipath asynchronous information output by the outside, and the number of the transmission units is consistent with that of the multipath asynchronous information.
Based on the same inventive concept, the invention also provides a transmission control method of the multi-channel asynchronous information, which is suitable for the transmission control device of the multi-channel asynchronous information, and comprises the following steps:
receiving and integrating multi-channel asynchronous information output by the outside to obtain a channel of integrated information, wherein the asynchronous information comprises asynchronous data and asynchronous control signals, the integrated information comprises integrated data and synchronous control signals, and the number of ping-pong operation modules is consistent with that of the multi-channel asynchronous information;
reading and/or writing integration data according to the synchronous control signal;
acquiring the integration information output by the data integrator and acquiring the integrated data written in the memory module.
In some embodiments of the invention, the synchronization control signal comprises: a line synchronization signal, a start synchronization signal, a line count signal, a frame count signal, an end signal, a write control level signal, a write start signal, a write initial address, a write length, a read control level signal, a read start signal, a read initial address, and a read length.
In some embodiments of the present invention, acquiring the integration information output by the data integrator and the integration data written in the memory module specifically includes: when the write control level signal in the synchronous control signal is high, the read-write controller writes the integrated data into the memory according to the write start signal, the write initial address and the write length; when the read control level signal in the synchronous control signal is high, the read/write controller reads the integrated data from the memory according to the read start signal, the read initial address and the read length, and outputs the integrated data to the processor interface.
(III) advantageous effects
Compared with the prior art, the transmission control device and the method of the multipath asynchronous information at least have the following advantages:
1. the data integrator is provided with at least two ping-pong operation modules, when one path of asynchronous information in the multi-path asynchronous information is cached in one ping-pong operation module, other asynchronous information cached in the other ping-pong operation modules can be read at the same time without waiting time, the speed is higher, so that the continuous effect of caching data and reading data is achieved, the data integrator is suitable for a pipeline algorithm, the seamless buffering and processing of the asynchronous information are realized, the buffering space can be saved, and the effect of processing a high-speed data stream by a low-speed module is achieved.
2. Through a data synchronization unit and a control signal synchronization unit in the data integrator, the multi-channel asynchronous information is integrated to obtain one channel of integrated information, transmission of the multi-channel information is facilitated, and transmission errors can be reduced.
3. The processor interface can receive the current integration information output by the data integrator, and can read the previous integration information stored by the memory module from the memory module, so that the backup of the integration information in different periods is realized.
4. The device has the advantages of simple structure, low cost and high speed, can be widely applied to data transmission occasions which need high-speed multipath transmission and need to realize logic with certain complexity, and is particularly suitable for high-speed lossless image data compression application.
Drawings
Fig. 1 is a schematic structural diagram of a transmission control device for multiple paths of asynchronous information according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a transmission control apparatus for multiple paths of asynchronous information according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a ping-pong operation module according to an embodiment of the invention.
Fig. 4 is a schematic step diagram of a transmission control method for multiple paths of asynchronous information according to an embodiment of the present invention.
Detailed Description
In general, the prior art has the following technical drawbacks: the waiting period of the multi-path data transmission is longer and the speed is slow; the processor can only process the current data and does not store the previous data; the system flow is too simple to meet the control of a more complex system on the data flow.
In view of the above, the present invention provides a device and a method for controlling transmission of multiple paths of asynchronous information. The data integrator in the device of the invention has at least two ping-pong operation modules, when one path of asynchronous information in the multi-path asynchronous information is cached in one ping-pong operation module, other asynchronous information cached in the other ping-pong operation modules can be read at the same time so as to achieve the effect of continuously caching data and reading data, the device is suitable for a pipeline algorithm, realizes the seamless buffering and processing of the asynchronous information, can save the buffering space, and achieves the effect of processing high-speed data flow by a low-speed module. The multi-path information refers to at least two paths of information, and the multi-path asynchronous information refers to that data and control signals of each path of information are asynchronous.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
In an aspect of the embodiments of the present invention, a transmission control device for multiple paths of asynchronous information is provided, and fig. 1 is a schematic structural diagram of the transmission control device for multiple paths of asynchronous information according to the embodiments of the present invention, as shown in fig. 1, the device includes a data integrator 1, a memory module 2, and a processor interface 3.
The data integrator 1 is connected with the memory module 2 and the processor interface 3 and comprises at least two ping-pong operation modules. The data integrator 1 receives and integrates multi-channel asynchronous information output from the outside to obtain one-channel integrated information, so that the transmission of the multi-channel information is facilitated, and transmission errors can be reduced. The asynchronous information comprises asynchronous data and asynchronous control signals, the integrated information comprises integrated data and synchronous control signals, and the number of the ping-pong operation modules is consistent with that of the plurality of paths of asynchronous information.
The memory module 2 reads and/or writes the integrated data according to the synchronous control signal output by the data integration period.
And the processor interface 3 is connected with the data integrator 1, the memory module 2 and an external processor, and is used for acquiring the integration information output by the data integrator 1 and acquiring the integrated data written in the memory module 2. The processor interface may be a specific circuit connection inside the chip, or may be a pin used for communicating with the outside of the device, and generally includes a data transmission path and an auxiliary structure for performing a transmission operation.
It can be understood that the processor interface 3 not only can receive the current integration information output by the data integrator 1, but also can read the previous integration information stored in the memory module 2 from the memory module 2, thereby implementing backup of integration information at different periods.
Fig. 2 is a schematic structural diagram of a transmission control device for multiple paths of asynchronous information according to an embodiment of the present invention, and as shown in fig. 2, the device includes, in addition to a data integrator 1, a memory module 2 and a processor interface 3, a transmission module 4 for receiving multiple paths of asynchronous information output from the outside, where the transmission module 4 includes multiple transmission units. In order to facilitate the transmission of the multiple paths of information and avoid interference, the number of the transmission units is set to be consistent with the number of the multiple paths of asynchronous information, that is, each transmission unit transmits one path of asynchronous information. It is understood that the transmission unit includes, but is not limited to, an optical transmission unit.
The data integrator 1 comprises at least two ping-pong manipulation modules 11 and a control signal synchronization unit 12. Generally, the number of ping-pong operational modules 11 should be consistent with the number of multiple asynchronous messages to prevent interference during the transmission of the messages. And the control signal synchronization unit 12 comprises registers with the same number as the ping-pong operation modules 11, the registers record corresponding multiple paths of asynchronous control signals, and when each register is in a recording state, a path of synchronous control signal is output and the recording state in each register is deleted. That is, when each register receives all the multiple paths of asynchronous control signals, the registers are in a recording state, at this time, the latest received path of asynchronous control signal is selected and set as the only synchronous control signal of the multiple paths of integrated data, and then the recording state of the current register is deleted, so that preparation is made for synchronizing the multiple paths of asynchronous control signals at the next moment.
The memory module 2 includes a signal controller 21, a memory 22 and a read/write controller, and the memory module 2 may be a DDR3 memory module 2, or other memory modules 2 may be selected according to actual requirements. The signal controller 21 is connected with the data integrator 1, and acquires integration information: the integration signal output by the ping-pong operation module 11 and the synchronization control signal output by the control signal synchronization unit 12. And a read/write controller for reading and/or writing the integrated data from/to the memory 22 according to the synchronization control signal in the integrated information. Wherein the synchronization control signal includes: a line synchronization signal, a start synchronization signal, a line count signal, a frame count signal, an end signal, a write control level signal, a write start signal, a write initial address, a write length, a read control level signal, a read start signal, a read initial address, and a read length.
Fig. 3 is a schematic structural diagram of a ping-pong operation module according to an embodiment of the present invention, and as shown in fig. 3, the ping-pong operation module includes: an input data selector 111, an output data selector 113, and at least two fifo arrays 112. In the embodiment of the present invention, two fifo arrays 112 are selected in consideration of power consumption, and other numbers of fifo arrays may be selected.
The input data selector 111 selects a FIFO array 112 to buffer one asynchronous data in multiple asynchronous data.
The output data selector 113 selects another fifo 112 to read the asynchronous data buffered therein while buffering a path of asynchronous data in the input data selector 111. It should be noted that the fifo array 112 being read in the ping-pong operation modules adopts a synchronous clock, and can perform synchronous processing and bit splicing on the read asynchronous data, so that the output data of different ping-pong operation modules become a whole to obtain a path of integrated data, and the waiting time for reading and writing can be saved.
Next, a specific flow of data transmission in the ping-pong operation module is described with reference to fig. 3:
when the first path of data arrives, caching the first path of data into a number 1 first-in first-out array through an input data selector; when the second way of data arrives, because the first way of data is cached in the first-in first-out array No. 1 at the moment, the input data selector caches the second way of data into the first-in first-out array No. 2, and simultaneously the first way of data cached in the first-in first-out array No. 1 is output through the output data selector. When the third path of data arrives, the third path of data is cached in the first-in first-out array No. 1 through the input data selector, and meanwhile, the cached second path of data in the first-in first-out array No. 2 is output through the output data selector, and so on. When the output operation is carried out, the same clock is fed to each first-in first-out array, and output data obtained in parallel connection are combined together in a splicing mode, so that signals finally output by the output data selector are changed into single-path signals which are output simultaneously.
In another aspect of the embodiments of the present invention, a method for controlling transmission of multiple paths of asynchronous information is further provided, which is suitable for the apparatus for controlling transmission of multiple paths of asynchronous information, and fig. 4 is a schematic diagram of steps of the method for controlling transmission of multiple paths of asynchronous information according to the embodiments of the present invention, as shown in fig. 4, the method includes the following steps:
step S1, receiving and integrating multi-channel asynchronous information output from the outside to obtain a channel of integrated information, wherein the asynchronous information comprises asynchronous data and asynchronous control signals, the integrated information comprises integrated data and synchronous control signals, and the number of ping-pong operation modules is consistent with that of the multi-channel asynchronous information;
and step S2, reading and/or writing the integrated data according to the synchronous control signal. Wherein the synchronization control signal includes: a line synchronization signal, a start synchronization signal, a line count signal, a frame count signal, an end signal, a write control level signal, a write start signal, a write initial address, a write length, a read control level signal, a read start signal, a read initial address, and a read length.
Step S3, obtaining the integration information output by the data integrator, and obtaining the integrated data written in the memory module. The method comprises the following specific steps:
when the write control level signal in the synchronous control signal is high, the read-write controller writes the integrated data into the memory according to the write start signal, the write initial address and the write length: at this time, the read-write controller receives a write start signal, and starts to write data with the same length as the received write length from the write initial address, the data is written into the memory in the mode of writing at the initial address initially, and the write address is added by 1 when receiving one data, so that the integrated data output by the data integrator is copied and stored into the memory.
When the read control level signal in the synchronous control signal is high, the read/write controller reads the integrated data from the memory according to the read start signal, the read initial address and the read length, and outputs the integrated data to the processor interface: the read-write controller receives the read start signal, and starts to read the data equivalent to the received length signal from the read initial address in a manner of reading at the read initial address initially and adding 1 to the read address when receiving one data, so as to transmit the written data read from the memory to the processor interface.
The transmission control device and the method of the multi-channel asynchronous information have simple structure, low cost and high speed, can be widely applied to data transmission occasions which need high-speed multi-channel transmission and need to realize logic with certain complexity, and are particularly suitable for high-speed lossless image data compression application.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A transmission control device of multi-channel asynchronous information comprises a data integrator, a memory module and a processor interface, wherein,
the data integrator is connected with the memory module and the processor interface and comprises at least two ping-pong operation modules and a control signal synchronization unit, the data integrator is used for receiving and integrating multi-path asynchronous information output by the outside to obtain a path of integration information, the asynchronous information comprises asynchronous data and asynchronous control signals, and the integration information comprises integration data and synchronous control signals; the number of the ping-pong operation modules is consistent with the number of the multi-path asynchronous information;
the ping-pong operation module comprises: the device comprises an input data selector, an output data selector and at least two first-in first-out arrays; the input data selector is used for selecting a first-in first-out array to cache one path of asynchronous data in the multi-path asynchronous data;
the output data selector is used for selecting the other first-in first-out arrays except the first-in first-out array while caching a path of asynchronous data in the input data selector, reading the cached asynchronous data, and synchronously processing and splicing the read asynchronous data to obtain a path of integrated data;
the control signal synchronization unit comprises registers with the same number as the ping-pong operation modules, the registers record corresponding multi-channel asynchronous control signals, and when each register is in a recording state, one channel of synchronous control signals is output and the recording state in each register is deleted;
the memory module is used for reading and/or writing the integrated data according to the synchronous control signal;
and the processor interface is connected with the data integrator, the memory module and an external processor and is used for acquiring the integration information output by the data integrator and acquiring the integrated data written in the memory module.
2. The apparatus of claim 1, wherein the synchronization control signal comprises: a line synchronization signal, a start synchronization signal, a line count signal, a frame count signal, an end signal, a write control level signal, a write start signal, a write initial address, a write length, a read control level signal, a read start signal, a read initial address, and a read length.
3. The apparatus of claim 1, the memory module comprising:
the signal controller is connected with the data integrator and is used for acquiring the integration information;
and the read-write controller reads and/or writes the integrated data to the memory according to the synchronous control signal in the integrated information.
4. The apparatus of claim 1, further comprising:
and the transmission module comprises a plurality of transmission units, the transmission module is used for receiving the multipath asynchronous information output by the outside, and the number of the transmission units is consistent with that of the multipath asynchronous information.
5. A transmission control method of multiple asynchronous information, which is applied to the transmission control device of multiple asynchronous information according to any one of claims 1 to 4, comprising:
receiving and integrating multi-channel asynchronous information output by the outside to obtain a channel of integrated information, wherein the asynchronous information comprises asynchronous data and asynchronous control signals, the integrated information comprises integrated data and synchronous control signals, and the number of ping-pong operation modules is consistent with that of the multi-channel asynchronous information;
reading and/or writing integration data according to the synchronous control signal;
acquiring the integration information output by the data integrator and acquiring the integrated data written in the memory module.
6. The method of claim 5, wherein the synchronization control signal comprises: a line synchronization signal, a start synchronization signal, a line count signal, a frame count signal, an end signal, a write control level signal, a write start signal, a write initial address, a write length, a read control level signal, a read start signal, a read initial address, and a read length.
7. The method of claim 5, wherein obtaining the integration information output by the data integrator and the integration data written in the memory module comprises:
when the write control level signal in the synchronous control signal is high, the read-write controller writes the integrated data into the memory according to the write start signal, the write initial address and the write length;
when the read control level signal in the synchronous control signal is high, the read/write controller reads the integrated data from the memory according to the read start signal, the read initial address and the read length, and outputs the integrated data to the processor interface.
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