CN102520892A - Multifunctional solid state data storage playback instrument - Google Patents
Multifunctional solid state data storage playback instrument Download PDFInfo
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- CN102520892A CN102520892A CN2012100004268A CN201210000426A CN102520892A CN 102520892 A CN102520892 A CN 102520892A CN 2012100004268 A CN2012100004268 A CN 2012100004268A CN 201210000426 A CN201210000426 A CN 201210000426A CN 102520892 A CN102520892 A CN 102520892A
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Abstract
The invention discloses a multifunctional solid state data storage playback instrument based on FLASH and realized by using a field programmable gate array (FPGA). The multifunctional solid state data storage playback instrument mainly solves the problems that the traditional magnetic disc array redundant array of independent disks (RAID) has slow reading and writing speed and is unstable, and the power consumption is high. The multifunctional solid state data storage playback instrument mainly consists of five parts: an FPGA control module, a FLASH storage array module, a universal serial bus (USB) 2.0 interface, a data receiving interface and a data playback interface, wherein the FPGA control module is used as a control core to be respectively in two-way connection with the USB2.0 interface and the FLASH storage array module and in one-way connection with the data receiving interface and the data playback interface and is used for receiving commands sent by a host personnel computer (PC) through the USB2.0 interface and analyzing the commands, and then, the high-density and relative-low-speed reliable storage and playback of the FLASH storage array on external high-speed data are successfully realized according to the analyzed commands. The highest storage and playback speed can reach 320Mbytes/s, and the multifunctional solid state data storage playback instrument has the advantages that the reliability is good, the power consumption is low, the capacity is large, the size is small, and the expansion is easy. The multifunctional solid state data storage playback instrument can be widely applied to the fields of radar, voice identification, image processing and the like.
Description
Technical field
The invention belongs to digital signal processing technique field, particularly utilize FPGA to realize multifunctional solid data storage playback apparatus, can be widely used in fields such as radar, guided missile, electronic surveying based on FLASH.
Background technology
Along with information science technology development with rapid changepl. never-ending changes and improvements; Real time signal processing field in modern times; In order to obtain more accurately effectively information; Must obtain lot of data and handle, and preceding high-speed data acquistion system is used widely in fields such as radar, sonar, Flame Image Process, speech recognition, communication, transient signal tests.Its gordian technique is high-speed ADC technology, data conversion storage and playback technology and error correction, Anti-Jamming Technique.
In radar system; Application scenario such as radar imagery, phased array radar particularly, radar receiver receives a large amount of high-speed real-time information, after these information via analog to digital conversion; How the data in real time of these magnanimity is preserved so that do subsequent treatment, just seem extremely important.
Present most data-storage system all is traditional disk array RAID; Disk array RAID is since invention; Its memory capacity and reliability are all improving constantly; The development of magnanimity information memory technology also makes disk array RAID become important external data memory, yet itself also there are some shortcomings in this disk array RAID:
1) read or write speed is slow: traditional disk array RAID is owing to adopt the read mode of disc high speed rotating magnetic head as data; Therefore data read-write operation of every execution in disk array; All need cycle regular hour; This time cycle is divided into seek time, rotation waiting time and data transmission period three parts, and so each read-write operation is generally wanted more than the 0.7ms consuming time.
2) instability: the physical construction of traditional magnetic disk array RAID causes its head wear and cantilever distortion; And disk array can cause the instability of its serviceability when being given a shock; The ordinary magnetic disc array only can bear the impulsive force about hundred G under off working state at present; Therefore under complex state such as MOVING STRUCTURE or the big occasion of vibrations, the traditional magnetic disk array is all not too suitable.
3) power consumption is big: the radial motion of the mechanical rotation of disc and magnetic head all can cause the disk array power consumption to increase to a great extent among the traditional magnetic disk array RAID.In addition, improve constantly along with what the disk array access speed was required, the rotating speed of disk array is also constantly being accelerated, and this can further cause the disk array power consumption to increase.
Summary of the invention:
The objective of the invention is to overcome the deficiency of above-mentioned prior art, provide a kind of FPGA of utilization to realize multifunctional solid data storage playback apparatus,, reduce system power dissipation to improve reading and writing data speed and system stability reliability based on FLASH.
For realizing above-mentioned purpose, the present invention includes:
The FPGA control module is respectively with USB2.0 interface, the two-way connection of FLASH storage array module, with the Data Receiving interface, the data readback interface is unidirectional is connected; Be used to accomplish three functions: the one, receive the order that the USB2.0 interface sends, and do parsing; The 2nd, receive the external data that transmission comes from the Data Receiving interface, and after interior tissue is handled, deposit storage array to FLASH; The 3rd, control FLASH storage array will be stored data and carry out playback through the data readback interface;
FLASH storage array module comprises 144 FLASH chips, is divided into eight groups; Every group 18; And carry out interconnectedly between every FLASH chip and the FPGA with order, address and data sheet end line, be used to receive the data that storage FPGA sends, and the data that this inside modules of playback has been stored are to FPGA;
The USB2.0 interface is used to respond the order that host PC is sent, and is passed to FPGA, and receives the data of FPGA passback, transfers to host PC;
The Data Receiving interface is used to receive external data, and is sent to FPGA;
The data readback interface is used for receiving the storage data of the FLASH storage array module that FPGA sends, and plays back to outside receiver.
It is interconnected to adopt the USB interface of standard to carry out between the described USB2.0 interface, it and host PC, and adopts synchronous Slave fifo interface to carry out interconnected between the FPGA.
Described Data Receiving interface adopts 8 pairs of LVDS differential received data lines, the 1 pair of LVDS differential received clock line, 1 single-ended reception frame synchronizing signal line and 1 single-ended reception control line and FPGA to carry out interconnected.
Described data readback interface adopts 8 pairs of LVDS difference playback of data lines, the 1 pair of LVDS difference playback clock line, 1 single-ended playback frame synchronizing signal line and 1 single-ended playback controls line and FPGA to carry out interconnected.
The present invention has following advantage:
1) the present invention is the control core of storage array with FPGA because to adopt solid-state storage chip FLASH be storage medium, has good reliability, power consumption is little, capacity is big, volume is little and is prone to the advantage of expansion.
2) the present invention operates FLASH by group flowing water owing to be divided into eight groups to the FLASH storage array successively, has realized that the highest storage playback speed can reach 320Mbytes/s with the FLASH storer of high density, the relative low speed reliable memory to high-speed data.
3) the present invention has manageable advantage owing to the communication bridge that adopts the conduct of USB2.0 interface with host PC.
Description of drawings
Fig. 1 is a hardware configuration design entire block diagram of the present invention;
Fig. 2 is the single interconnected synoptic diagram of hardware of organizing FLASH array and FPGA among the present invention;
Fig. 3 is USB2.0 interface and the interconnected synoptic diagram of hardware of FPGA among the present invention;
Fig. 4 is that the Data Receiving interface among the present invention is connected synoptic diagram with the hardware of FPGA;
Fig. 5 is that the data readback interface among the present invention is connected synoptic diagram with the hardware of FPGA.
Embodiment:
With reference to Fig. 1, multifunctional solid data storage playback apparatus of the present invention mainly is made up of FPGA control module, FLASH storage array module, USB2.0 interface, Data Receiving interface and data readback interface five parts.Wherein, the FPGA control module respectively with USB2.0 interface, the two-way connection of FLASH storage array module, with the Data Receiving interface, the data readback interface is unidirectional is connected.Wherein:
Described FPGA control module is selected the Stratix II family chip EP2S90F1020I4 of ALTERA company for use, but is not limited to this chip, and it has abundant trigger and look-up table LUT; Be fit to very much the design of complex time sequence logic; And the built-in storage RAM of 4.3Mbit arranged, and can a certain amount of data of buffer memory, possess 759 common I/O that support various single-ended and difference standards simultaneously; Can supply the user to select according to different demands, this module comprises:
Order receives analyzing sub-module, is used to receive the order that the USB2.0 interface sends, and resolves and should order;
The Data Receiving sub module stored is used to receive the external data that transmission comes from the Data Receiving interface, and after interior tissue is handled, deposits the storage array to FLASH;
The data readback controlling sub is used to control the FLASH storage array and will stores data and carry out playback through the data readback interface.
Described FLASH storage array module is selected the NAND FLASH family chip K9WBG08U1M of SAMSUNG company for use, but is not limited to this chip, and its external interface speed is 40MHz, 8 of data bit widths; Every chip contains 16384 data blocks, and each data block is divided into 64 pages, and every page of size is (2K+64) Bytes, and wherein 2KBytes is the data storage area, and 64Bytes is the free area; Every K9WBG08U1M storage total volume is 4GBytes; With the page or leaf is that unit reads and writes, and is that unit is wiped with the piece, order, data, the same bus of address sharing, and have the hardware data defencive function; This FLASH storage array module comprises 144 FLASH chips, is divided into eight groups, 18 every group; Wherein 16 are used for data storage; 1 is specifically designed to redundancy check, other 1 subsequent use, to guarantee the complete reliability of storage data; And carry out interconnectedly between every group of FLASH array and the FPGA with order, address and data sheet end line, it is identical that each organizes between FLASH array and the FPGA connected mode.
Described USB2.0 interface; Select the CY7C68013 chip of Cypress company for use, it is interconnected to adopt synchronous Slave fifo interface to carry out between this chip and the FPGA, has applying flexible; The cost performance advantage of higher is the chip that carries out a function admirable of USB2.0 exploitation.
Described Data Receiving interface and data readback interface are all selected J63A2F2037AN standard aviation connector for use, and the impedance continuity of this connector is good, is well suited for as the high-speed data connecting interface.
More than detailed annexation such as Fig. 2, Fig. 3, Fig. 4 and shown in Figure 5 between each parts.
With reference to Fig. 2, order wire, the address wire of 18 FLASH among every group of FLASH is cascaded and is interconnected with FPGA, and data line is connected in parallel and is interconnected with FPGA; This order, address wire are R/B#, CLE, ALE, CE#, RE#, WE#, and this data line is IO [143:0], wherein; R/B# is that FLASH is ready to/busy signal; Represent during high level to be ready to and to operate on it, represent during low level to be not ready for, can not operate it; CLE is command latch enable control, and whether the command channel that is used to control the FLASH register is effective; ALE is that address latch enables control, and whether the address tunnel that is used to control the FLASH register is effective; CE# is the FLASH chip selection signal, and low level is effective; RE# enables for reading FLASH, and low level is effective; WE# enables for writing FLASH, and low level is effective; IO [143:0] is the parallel data bus line of every group of FLASH.
Said R/B#, CLE, ALE, CE#, RE#, WE# command address line and IO [143:0] data line, with single ended line respectively with FPGA in any 150 common I/O link to each other.
With reference to Fig. 3; Adopt synchronous Slave fifo interface to carry out interconnected between CY7C68013 chip and the FPGA; Described Slave fifo interface comprises IFCLK, FLAGA, FLAGB, FLAGC, SLCS#, SLOE, SLRD, PKTEND, FD [15:0] and FIFOADR [1:0] signal; Wherein, IFCLK is the interface clock signal; FLAGA is the programming phases mode bit; FLAGB is the full zone bit of input block, during high level, shows that the data buffer data are full; FLAGC is the empty zone bit of output buffer, during high level, shows that the data buffer data are empty; SLCS# is a chip selection signal, and low level is effective; SLOE is a data output enable signal; SLRD is for reading enable signal; SLWR is for writing enable signal; PKTEND is specific read-write control signal; FD [15:0] is a data bus; FIFOADR [1:0] is selection FD data bus, and the FIFO zone bit that is connected to.
Said IFCLK, FLAGA, FLAGB, FLAGC, SLCS#, SLOE, SLRD, PKTEND, FIFOADR [1:0] and FD [15:0], with single ended line respectively with FPGA in any 26 common I/O link to each other.
With reference to Fig. 4, it is interconnected to adopt 8 pairs of LVDS differential received data lines, the 1 pair of LVDS differential received clock line, 1 single-ended reception frame synchronizing signal line and 1 single-ended reception control line to carry out between Data Receiving interface and the FPGA, and wherein 8 pairs of LVDS differential received data lines are: DR0p; DR0n is to DR7p, DR7n, and 1 pair of LVDS differential received clock line is CRp; CRn, 1 single-ended reception frame synchronizing signal line is FR, 1 single-ended reception control line is SR; DR0p～DR7p and CRp are the positive signal that LVDS receives differential pair; DR0p～DR7n and CRn are the negative signal that LVDS receives differential pair, and FR is for receiving the data sync control signal, and SR is single-ended reception control signal.
Said 8 couples of LVDS differential received data line DR0p, DR0n are to DR7p, DR7n and receive clock differential pair CRp; CRn; With differential lines respectively with FPGA in any 9 couples of common I/O link to each other, synchronous signal line FR and control line SR, with single ended line respectively with FPGA in any 2 common I/O link to each other.
With reference to Fig. 5, it is interconnected to adopt 8 pairs of LVDS difference playback of data lines, the 1 pair of LVDS difference playback clock line, 1 single-ended playback frame synchronizing signal line and 1 single-ended playback controls line to carry out between data readback interface and the FPGA, and wherein 8 pairs of LVDS difference playback of data lines are: DT0p; DT0n is to DT7p, DT7n, and 1 pair of LVDS difference playback clock line is CTp; CTn, 1 single-ended playback frame synchronizing signal line is FT, 1 single-ended playback controls line is ST; DT0p～DT7p and CTp are the positive signal of LVDS playback differential pair; DT0p～DT7n and CTn are the negative signal of LVDS playback differential pair, and FT is the playback of data synchronous control signal, and ST is single-ended playback control signal.
Said 8 couples of LVDS difference playback of data line DT0p, DT0n are to DT7p, DT7n and playback clock differential pair CTp; CTn; With differential lines respectively with FPGA in any 9 couples of common I/O link to each other, synchronous signal line FT and control line ST, with single ended line respectively with FPGA in any 2 common I/O link to each other.
Principle of work of the present invention is following:
At first; This multifunctional solid data storage playback apparatus and main frame and external component are linked together; Wherein, With the USB standard lines it is linked together through USB2.0 interface and host PC, it is linked together through Data Receiving interface and external data transmitter, it is linked together through data readback interface and external data receiver with J63A2F2037AN standard connector line with J63A2F2037AN standard connector line.
Then, send order through host PC through the USB2.0 interface, the call instruction of FPGA control module receives analyzing sub-module; Receive this order and do parsing; If the order of the order storage operation after the parsing, the FPGA control module is then called the Data Receiving sub module stored, receives the external data that transmission comes from the Data Receiving interface; These data are added specific frame head; And carry out redundancy check, after the FIFO caching process, 8 groups of FLASH arrays in the FLASH storage array are stored according to multistage pipeline mode again; If the playback operation order, the FPGA control module is then called the data readback controlling sub, and 8 groups of FLASH arrays in the control FLASH storage array carry out data readback according to multistage pipeline mode, and play back to outside receiver through the data readback interface.
Claims (9)
1. multifunctional solid data storage playback apparatus comprises:
(1) FPGA control module is respectively with USB2.0 interface, the two-way connection of FLASH storage array module, with the Data Receiving interface, the data readback interface is unidirectional is connected; Be used to accomplish three functions: the one, receive the order that the USB2.0 interface sends, and do parsing; The 2nd, receive the external data that transmission comes from the Data Receiving interface, and after interior tissue is handled, deposit storage array to FLASH; The 3rd, control FLASH storage array will be stored data and carry out playback through the data readback interface;
(2) FLASH storage array module; Comprise 144 FLASH chips; Be divided into eight groups, 18 every group, and carry out interconnected with order, address and data sheet end line between every FLASH chip and the FPGA; Be used to receive the data that storage FPGA sends, and the data that this inside modules of playback has been stored are to FPGA;
(3) USB2.0 interface is used to respond the order that host PC is sent, and is passed to FPGA, and receives the data of FPGA passback, transfers to host PC;
(4) Data Receiving interface is used to receive external data, and is sent to FPGA;
(5) data readback interface is used for receiving the storage data of the FLASH storage array module that FPGA sends, and plays back to outside receiver.
2. multifunctional solid data storage playback apparatus according to claim 1, wherein said USB2.0 interface, it is interconnected to adopt the USB interface of standard to carry out between it and the host PC, and adopts synchronous Slave fifo interface to carry out interconnected between the FPGA.
3. multifunctional solid data storage playback apparatus according to claim 1; Wherein said Data Receiving interface adopts 8 pairs of LVDS differential received data lines, the 1 pair of LVDS differential received clock line, 1 single-ended reception frame synchronizing signal line and 1 single-ended reception control line and FPGA to carry out interconnected.
4. multifunctional solid data storage playback apparatus according to claim 1; Wherein said data readback interface adopts 8 pairs of LVDS difference playback of data lines, the 1 pair of LVDS difference playback clock line, 1 single-ended playback frame synchronizing signal line and 1 single-ended playback controls line and FPGA to carry out interconnected.
5. multifunctional solid data storage playback apparatus according to claim 1, wherein said FPGA control module is selected the Stratix II family chip of ALTERA company for use.
6. multifunctional solid data storage playback apparatus according to claim 1, wherein said FLASH storage array module is selected the NAND FLASH family chip of SAMSUNG company for use.
7. multifunctional solid data storage playback apparatus according to claim 1, wherein said USB2.0 interface is selected the CY7C68013 chip of Cypress company for use.
8. multifunctional solid data storage playback apparatus according to claim 1, wherein said Data Receiving interface is selected J63A2F2037AN standard aviation connector for use.
9. multifunctional solid data storage playback apparatus according to claim 1, wherein said data readback interface is selected J63A2F2037AN standard aviation connector for use.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103226976A (en) * | 2013-03-19 | 2013-07-31 | 中国科学院声学研究所 | Apparatus for realizing multi-chip Nandflash storage and read based on FPGA |
| CN103413422A (en) * | 2013-07-24 | 2013-11-27 | 中国科学院上海微系统与信息技术研究所 | Information acquisition, integration and development platform of sensor |
| CN104133798A (en) * | 2014-08-01 | 2014-11-05 | 西安电子科技大学 | Big data high-speed storage system and implementation method |
| CN104407817A (en) * | 2014-11-26 | 2015-03-11 | 西安电子科技大学 | Seeker data recorder based on SoC |
| CN104750437A (en) * | 2014-12-19 | 2015-07-01 | 中国航天科技集团公司第五研究院第五一三研究所 | Expandable capacity type satellite-borne large-capacity storage system |
| CN104834481A (en) * | 2015-04-30 | 2015-08-12 | 中国电子科技集团公司第四十一研究所 | Signal analysis system and signal analysis method for large-capacity rapid storage and playback |
| CN111258504A (en) * | 2020-01-15 | 2020-06-09 | 西安电子科技大学 | Storage control system based on SATA interface solid state hard drives |
| CN113051109A (en) * | 2021-03-29 | 2021-06-29 | 上海航天测控通信研究所 | Satellite-borne storage system with high reliability and low bit error rate |
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| CN101162398A (en) * | 2006-10-12 | 2008-04-16 | 东莞理工学院 | Arbitrarily signal generating device |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103226976A (en) * | 2013-03-19 | 2013-07-31 | 中国科学院声学研究所 | Apparatus for realizing multi-chip Nandflash storage and read based on FPGA |
| CN103413422A (en) * | 2013-07-24 | 2013-11-27 | 中国科学院上海微系统与信息技术研究所 | Information acquisition, integration and development platform of sensor |
| CN104133798A (en) * | 2014-08-01 | 2014-11-05 | 西安电子科技大学 | Big data high-speed storage system and implementation method |
| CN104133798B (en) * | 2014-08-01 | 2017-10-10 | 西安电子科技大学 | A kind of big data high-speed memory system and implementation method |
| CN104407817A (en) * | 2014-11-26 | 2015-03-11 | 西安电子科技大学 | Seeker data recorder based on SoC |
| CN104750437A (en) * | 2014-12-19 | 2015-07-01 | 中国航天科技集团公司第五研究院第五一三研究所 | Expandable capacity type satellite-borne large-capacity storage system |
| CN104750437B (en) * | 2014-12-19 | 2017-10-13 | 中国航天科技集团公司第五研究院第五一三研究所 | A kind of expansible spaceborne mass-storage system of capacity |
| CN104834481A (en) * | 2015-04-30 | 2015-08-12 | 中国电子科技集团公司第四十一研究所 | Signal analysis system and signal analysis method for large-capacity rapid storage and playback |
| CN104834481B (en) * | 2015-04-30 | 2018-05-29 | 中国电子科技集团公司第四十一研究所 | A kind of signal analysis device and method of the playback of large capacity quick storage |
| CN111258504A (en) * | 2020-01-15 | 2020-06-09 | 西安电子科技大学 | Storage control system based on SATA interface solid state hard drives |
| CN111258504B (en) * | 2020-01-15 | 2023-05-30 | 西安电子科技大学 | Storage control system based on SATA interface solid state disk |
| CN113051109A (en) * | 2021-03-29 | 2021-06-29 | 上海航天测控通信研究所 | Satellite-borne storage system with high reliability and low bit error rate |
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Application publication date: 20120627 |