CN206557767U - A kind of caching system based on ping-pong operation structure control data buffer storage - Google Patents
A kind of caching system based on ping-pong operation structure control data buffer storage Download PDFInfo
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Abstract
The utility model provides a kind of caching system based on ping-pong operation structure control data buffer storage, and the caching system includes：FPGA field programmable gate arrays and two groups of DDR3 SDRAM chipsets, wherein, the FPGA field programmable gate arrays include：It is arranged on the Data Input Interface on the FPGA, table tennis writing controller, table tennis Read Controller, DDR3 sdram controllers and data storage, the utility model is small or the problem of can not read while write based on the capacity that existing data buffer storage mode is present, the extension of ping-pong operation structure control DDR3 SDRAM chips is used to build Large Copacity asynchronous FIFO to carry out data buffer storage, include two groups of DDR3 SDRAM chips, while data are write in one group of DDR3 SDRAM chips realization, another group of DDR3 SDRAM chip, which is realized, reads data, user can carry out the read-write of data simultaneously, and build massive store space because DDR3 SDRAM chips are expansible, so that it is expansible go out larger spatial cache.
Description
Technical field
The utility model is related to big data quantity caching and processing technology field, more particularly to a kind of based on ping-pong operation structure
The caching system of control data caching.
Background technology
In the communication technology, data storage is the temporary file that data flow is produced in process or needed in process
The information to be searched, data are recorded in computer-internal or exterior storage medium in a certain format.Data flow reflects system
The data of middle flowing, show the feature of dynamic data；Static data, show static data in data storage reflection system
Feature.
At present for data buffer storage mode mainly using following two：FPGA(Field-Programmable Gate
Array, i.e. field programmable gate array) internal block RAM (Random Access Memory, random access memory) does
FIFO (First Input First Output, First Input First Output) or dual port RAM build spatial cache progress data and deposited
Storage；Or spatial cache progress data storage is built using plug-in storage chip.But use the block RAM inside FPGA to build caching
Space, the data volume that it is stored is limited, it is impossible to realize the caching of mass data；Although and plug-in storage chip can realize a large amount of numbers
According to caching, for example (DDR3 SDRAM are DDR3 full name, and DDR3 is the internal memory rule of computer for plug-in DDR3 SDRAM chips
Lattice), but due to the semiduplex mode of operation of DDR3 SDRAM chips, therefore, user is the same without image of Buddha FIFO or dual port RAM
Data read-write operation is carried out simultaneously.
Utility model content
The utility model provides a kind of caching system based on ping-pong operation structure control data buffer storage, existing to solve
The problem of capacity existed in technology based on existing data buffer storage mode is small or can not read while write.
To reach above-mentioned purpose, the utility model provides following technical scheme：
A kind of caching system based on ping-pong operation structure control data buffer storage, including：On-site programmable gate array FPGA
With two groups of DDR3 SDRAM chipsets, wherein, the FPGA includes：It is arranged on Data Input Interface, table tennis on the FPGA
Writing controller, table tennis Read Controller, DDR3 SDRAM controllers and data storage, wherein：
The Data Input Interface receive it is outside send it is data cached, and will the data cached transmission to the table tennis
Pang writing controller；
The table tennis writing controller is connected with the Data Input Interface, is sent for receiving the Data Input Interface
It is data cached and carry out the data cached write operation, and memory buffers control information；
The DDR3 sdram controllers are connected with the table tennis writing controller, for recording the table tennis writing controller
Cache control information, and the table tennis writing controller is controlled to the data cached progress caching processing, and to described
Cache control information is transmitted；
The table tennis Read Controller is connected with the DDR3 sdram controllers, for receiving the DDR3 SDRAM
The cache control information that controller is sent, and to the data cached carry out read operation；
The data storage is connected with the table tennis Read Controller, is read for receiving the table tennis Read Controller
It is data cached after operation, and data cached after the read operation is stored；
Two groups of DDR3 SDRAM chipsets are connected with the DDR3 sdram controllers respectively, for expanding caching
Space, to after the read operation it is data cached enter line asynchronous store.
Wherein, two groups of DDR3 SDRAM chipsets include the DDR3 SDRAM chips of identical quantity.
Wherein, data volume is read and write in two groups of DDR3 SDRAM chipsets identical.
Wherein, the Data Input Interface is PCIe interface.
Wherein, the model Virtex-7xc7vx690tffg1930-1 of the FPGA.
Wherein, the model MT41K256M16HA-125 of the DDR3 SDRAM.
From such scheme, compared with prior art, the utility model provides a kind of based on ping-pong operation structure control
The caching system of data buffer storage processed, the caching system includes：FPGA field programmable gate arrays and two groups of DDR3 SDRAM chips
Group, wherein, the FPGA field programmable gate arrays include：Data Input Interface, the table tennis being arranged on the FPGA write control
Device processed, table tennis Read Controller, DDR3 sdram controllers and data storage, the utility model are based on existing data buffer storage
The problem of capacity that mode is present is small or can not read while write, is extended using ping-pong operation structure control DDR3 SDRAM chips
Large Copacity asynchronous FIFO is built to carry out data buffer storage, comprising two groups of DDR3 SDRAM chips, one group of DDR3 SDRAM chip is real
While now writing data, another group of DDR3 SDRAM chip, which is realized, reads data, and user can carry out the read-write of data simultaneously, and due to
DDR3 SDRAM chips are expansible to build massive store space so that it is expansible go out larger spatial cache.
Brief description of the drawings
, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art
Or the accompanying drawing used required in description of the prior art is briefly described, it should be apparent that, drawings in the following description are only
It is some embodiments of the present utility model, for those of ordinary skill in the art, is not paying the premise of creative work
Under, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of traditional ping-pong buffer；
Fig. 2 is the operation example figure of ping-pong buffer；
A kind of caching system signal based on ping-pong operation structure control data buffer storage that Fig. 3 provides for the utility model
Figure；
Fig. 4 reads for a kind of caching system data based on ping-pong operation structure control data buffer storage that the utility model is provided
Write schematic flow sheet.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belongs to the scope of the utility model protection.
Ping-pong buffer (PingPong Buffer) mechanism is a kind of cache way of the more commonly used increase data bandwidth,
Any one, which can be used in, needs in the system that read operation and write operation are carried out simultaneously, such as in interchanger and route system
Data recombination is cached, or the batch data transmission in computer system.Ping-pong buffer is using two pieces of one-port memories, every
The individual clock cycle, only need to perform a kind of operation per block storage, for example：Read or write.The general structure of ping-pong buffer such as Fig. 1
Shown, it is assumed that the total capacity of ping-pong buffer is M, its unit is memory cell, and An is used in its input processing and output processing respectively
Represented with Dn.Ping-pong buffer includes two pieces of physically separate memory devices, and each capacity is M/2, two memories respectively
Interface is held together, externally visibly simply one caching, operable capacity is M/2.In ping-pong buffer, read operation and
Write operation can occur simultaneously, but alternating action is on different storage component parts respectively.Fig. 2 is that the operation of ping-pong buffer is shown
Illustration.As shown in Fig. 2 when the arrival of An data cells is inputted, if one of caching buffer1 is read, that
These data cells can be written on other one piece of caching buffer2；When caching 1 writes full, caching 2 is read after sky, and operation is just
It has exchanged, in An write-ins caching 2, and Dn always reads data from caching 1.From the point of view of An or Dn, operation be all
Between two cachings alternately, ping-pong buffer is caching mechanism the more commonly used at present, and its basic principle is wide by industry
It is general to receive.
The utility model provides a kind of caching system based on ping-pong operation structure control data buffer storage, specifically：
Refer to accompanying drawing 3, a kind of delaying based on ping-pong operation structure control data buffer storage that Fig. 3 provides for the utility model
Deposit system schematic diagram.As shown in figure 3, the utility model discloses a kind of caching based on ping-pong operation structure control data buffer storage
System, specific caching system includes：On-site programmable gate array FPGA 101 and two groups of DDR3 SDRAM chipsets 102, its
In, FPGA101 includes：It is arranged on Data Input Interface 103, table tennis writing controller 104, table tennis Read Controller on the FPGA
105th, DDR3 sdram controllers 106 and data storage 107, wherein：
Data Input Interface 103 receive it is outside send it is data cached, and data cached send to table tennis is write into control
Device 104；
Table tennis writing controller 104 is connected with Data Input Interface 103, the caching for receiving Data Input Interface transmission
Data simultaneously carry out data cached write operation, and memory buffers control information；
DDR3 sdram controllers 106 are connected with table tennis writing controller 104, the caching for recording table tennis writing controller
Control information, and table tennis writing controller 104 is controlled to data cached progress caching processing, and to the cache control information
It is transmitted；
Table tennis Read Controller 105 is connected with DDR3 sdram controllers 106, for receiving DDR3 sdram controllers
106 cache control informations sent, and to data cached carry out read operation；
Data storage 107 is connected with table tennis Read Controller 105, and reading behaviour is carried out for receiving table tennis Read Controller 105
It is data cached after work, and data cached after the read operation is stored；
Two groups of DDR3 SDRAM chipsets 102 are connected with DDR3 sdram controllers 106 respectively, empty for expanding caching
Between, to after the read operation it is data cached enter line asynchronous store.
Wherein, two groups of DDR3 SDRAM chipsets include the DDR3 SDRAM chips of identical quantity.
Fig. 4 reads for a kind of caching system data based on ping-pong operation structure control data buffer storage that the utility model is provided
Write schematic flow sheet.Specifically, as shown in figure 4, the reading and writing data of the caching system includes the control of user interface, user interface
Sending and receiving end respectively contain the asynchronous FIFO that FPGA internal blocks RAM is built, the settable dot of the FIFO space, it is only necessary to
Data are carried out with the conversion of clock zone, in the transmitting terminal of user interface, i.e.,：One end of equipment is sent close to user, FIFO's writes
The clock that clock and user send equipment is identical, and that reads clock and DDR3 SDRAM chips writes that clock is identical, in user interface
Receiving terminal, i.e.,：Close to one end of user receiving equipment, FIFO to write clock identical with the reading clock of DDR3 SDRAM chips,
DDR3 SDRAM chips to write clock identical with the clock of user receiving equipment, so as to match the clock of transceiver so that receive
Send out equipment need not clock it is homologous, the control of two groups of DDR3 SDRAM chips is specifically, the FIFO buffers include read-write two connects
Mouthful, operation can be written and read simultaneously, and due to the half-duplex mode of operation of DDR3 SDRAM chips, 1 group of DDR3 SDRAM can only
Write operation either read operation is carried out, and operation is written and read simultaneously like that without image of Buddha FIFO, in order to DDR3 SDRAM chips
Operation is written and read simultaneously, it is necessary to simultaneously using two groups of DDR3 SDRAM chips, during to one group of carry out write operation, another set
Chip carry out read operation, it is separate, do not interfere with each other, you can with as FIFO and meanwhile completion read-write operation, so two groups
DDR3 SDRAM chips, it is not necessary to more DDR3 SDRAM chips, wherein, although DDR3 SDRAM chips are only two
Group, but every group of DDR3 SDRAM number of chips can be extended as needed.DDR3 is increased by growth data bit wide
The memory space of SDRAM chips, address bit wide is constant.In order to ensure the operation to every group of DDR3 SDRAM chip can smoothly enter
OK, it is ensured that required time consistency, the data volume included in every group of DDR3 SDRAM chip must be identical.User sends and set
The data that preparation is brought are written in constructed FIFO and cached, and user receiving equipment can be read from the cushion space at any time
Access evidence.
As shown in figure 4, the plug-in two groups of DDR3 SDRAM chips of FPGA, in fpga logic, using ping pong scheme by user
The data data1 that transmission equipment is sended over is written in the asynchronous FIFO of user interface according to a certain amount, DDR3 SDRAM
Chipset 1 reads group DDR3 SDRAM chips of data, i.e., first from the FIFO, is cached, then exchanged, and next sends
Data data2 equivalent is written in the asynchronous FIFO of user interface again, specifically, toward writing in two groups of DDR3 SDRAM chips
The reason for equal amount of data：When being operated to two groups of DDR3 SDRAM chips simultaneously, such as：DDR3 SDRAM chipsets 1 are carried out
While write operation, DDR3 SDRAM chipsets 2 carry out read operation, while DDR3 SDRAM chipsets 1 write N number of several, obtain
Ensure that the data in DDR3 SDRAM chipsets 2 can be gone by complete reading, it is to avoid time length data spillings, and this process is
Interactive, if data inequality, it is possible that the data of DDR3 SDRAM chipsets 1 write, DDR3 SDRAM chipsets
2 data are not run through also, or the data of DDR3 SDRAM chipsets 2 write, and the data of DDR3 SDRAM chipsets 1 are not read
Complete, after reading and writing data time length, data are overflowed, so DDR3 SDRAM chipsets 1 and DDR3 SDRAM chipsets 2 must allow
Data equivalent；DDR3 SDRAM chipsets 2：I.e. second group DDR3 SDRAM chip, reading data are delayed from the FIFO
Deposit, in the data cached period of DDR3 SDRAM chipsets 2, user receiving equipment can be read from DDR3 SDRAM chipsets 1
Data, then exchange role and carry out, and the data that so transmission equipment is sended over can be with continual write-in DDR3 SDRAM cores
Cached in piece, and receiving device can also be independent of each other at any time from the read-only access evidence of DDR3 SDRAM chips.At present
The memory size wall scroll of DDR3 SDRAM chips can reach 8GB, so the model of the DDR3 SDRAM chips used according to user
Several GB data buffer storage can be realized using DDR3 SDRAM chips.
Specifically, above-mentioned Data Input Interface is PCIe interface；FPGA model can be Virtex-7
Xc7vx690tffg1930-1, but it is not limited only to the model；DDR3 SDRAM model can be MT41K256M16HA-
125, but it is not limited only to the model.
In the present embodiment, FPGA models can be Virtex-7xc7vx690tffg1930-1, and DDR3 SDRAM models can be
MT41K256M16HA-125, memory capacity 4Gbit, data/address bus is 16bit.4 DDR3 have been used in the present embodiment altogether
SDRAM chips, every group with two panels, by carrying out parallel work-flows, single growth data bit wide to this two groups of DDR3 SDRAM chips
For 32bit, memory capacity 8Gbit, therefore, two groups of memory capacity is 16Gbit, and the work of model DDR3 SDRAM chips
800MHz is can reach as speed, the bit wide of write-in data is 32bit, so theoretical bandwidth is 3.2GB, actual measurement speed can reach
3GB, meets high-speed demand.
The date storage method of the caching system based on ping-pong operation structure control data buffer storage is specially：
The system can be used in the playback function for realizing memory plane, and after electricity on memory plane, computer starts to write data
When, when EMMC data memory modules receive write order, EMMC chips have a startup time, now, the number that host computer writes
According to the capacity for having 1G or so, if computer writes data again after waiting chip writeable, efficiency can be influenceed, if computer is directly issued
Start to write after write order, now, meeting lost part data, so needing first to store data in DDR3 SDRAM chips.
When EMMC data memory modules writeable data, data are read from DDR3 SDRAM chips.DDR3 SDRAM cores
Piece needs to give EMMC memory modules by the data read-out of storage while the data for writing down computer are written in chip,
, can be readable writeable i.e. in the case where ensureing that memory capacity is enough, so as to ensure that the data that computer is write down are uninterrupted, improve
Efficiency.Therefore, employ ping-pong operation structure and realize this function, the first bag data of computer write-in is stored in DDR3
In SDRAM chipsets 1, now DDR3 SDRAM chipsets 2 do not carry out any operation, and DDR3 can be read in EMMC data memory modules
Data in SDRAM chipsets 2, and after computer writes the first bag data, the second bag data of write-in is stored in DDR3
In SDRAM chipsets 2, release DDR3 SDRAM chipsets 1, DDR3 SDRAM chipsets 1 can be read in EMMC data memory modules
In data, realize the continual read-write of data by carrying out alternate read-write operation to two groups of chip.
During actual use, in the case where used fpga chip interface resource is enough, DDR3 SDRAM
The memory capacity of chipset can be actual to meet by increasing the quantity of every group of chip come extension storage capacity and storage speed
Storage needs.DDR3 SDRAM chipsets read and write data by parallel data-interface, can be by extending DDR3 on hardware
The mode of SDRAM chip data bit wides adds DDR3 SDRAM chips, address invariant position, the address bits of all chips and FPGA's
Interface is identical, so, and data bit width is more, and under identical DDR3 SDRAM chip system clocks, the data being written in parallel to are got over
Many, speed is faster, and memory capacity is also bigger.
In summary, the utility model provides a kind of caching system based on ping-pong operation structure control data buffer storage, should
Caching system includes：FPGA field programmable gate arrays and two groups of DDR3 SDRAM chipsets, wherein, the FPGA scenes can be compiled
Journey gate array includes：It is arranged on Data Input Interface, table tennis writing controller, table tennis Read Controller, DDR3 on the FPGA
Sdram controller and data storage, the utility model is based on the capacity that existing data buffer storage mode is present is small or nothing
The problem of method is read while write, use ping-pong operation structure control DDR3 SDRAM chips extension build Large Copacity asynchronous FIFO with
Data buffer storage is carried out, it is another while data are write in one group of DDR3 SDRAM chips realization comprising two groups of DDR3 SDRAM chips
Group DDR3 SDRAM chips, which are realized, reads data, user can data simultaneously read-write, and due to the expansible structure of DDR3 SDRAM chips
Build massive store space so that it is expansible go out larger spatial cache..
The embodiment of each in this specification is described by the way of progressive, what each embodiment was stressed be with it is other
Between the difference of embodiment, each embodiment same or similar part mutually referring to.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or new using this practicality
Type.A variety of modifications to these embodiments will be apparent for those skilled in the art, determine herein
The General Principle of justice can in other embodiments be realized in the case where not departing from spirit or scope of the present utility model.Cause
This, the utility model is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The most wide scope consistent with features of novelty.
Claims (6)
1. a kind of caching system based on ping-pong operation structure control data buffer storage, it is characterised in that including：Field programmable gate
Array FPGA and two groups of DDR3SDRAM chipsets, wherein, the FPGA includes：The data input being arranged on the FPGA connects
Mouth, table tennis writing controller, table tennis Read Controller, DDR3SDRAM controllers and data storage, wherein：
It is data cached that the Data Input Interface reception outside is sent, and data cached send to the table tennis is write
Controller；
The table tennis writing controller is connected with the Data Input Interface, for receiving the slow of the Data Input Interface transmission
Deposit data simultaneously carries out the data cached write operation, and memory buffers control information；
The DDR3SDRAM controllers are connected with the table tennis writing controller, for recording the slow of the table tennis writing controller
Control information is deposited, and controls the table tennis writing controller to the data cached progress caching processing, and to the caching
Control information is transmitted；
The table tennis Read Controller is connected with the DDR3SDRAM controllers, for receiving the DDR3SDRAM controllers hair
The cache control information sent, and to the data cached carry out read operation；
The data storage is connected with the table tennis Read Controller, and read operation is carried out for receiving the table tennis Read Controller
Afterwards data cached, and data cached after the read operation is stored；
Two groups of DDR3SDRAM chipsets are connected with the DDR3SDRAM controllers respectively, for expanding spatial cache,
To after the read operation it is data cached enter line asynchronous storage.
2. caching system according to claim 1, it is characterised in that two groups of DDR3SDRAM chipsets are comprising identical
The DDR3SDRAM chips of quantity.
3. caching system according to claim 1, it is characterised in that read and write number in two groups of DDR3SDRAM chipsets
It is identical according to measuring.
4. caching system according to claim 1, it is characterised in that the Data Input Interface is PCIe interface.
5. caching system according to claim 1, it is characterised in that the model Virtex- of the FPGA
7xc7vx690tffg1930-1。
6. caching system according to claim 1, it is characterised in that the model of the DDR3SDRAM
MT41K256M16HA-125。
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| CN114121066A (en) * | 2021-09-09 | 2022-03-01 | 西安电子工程研究所 | DDR 3-based dynamic ping-pong stack type data rearrangement realization method |
| CN114121066B (en) * | 2021-09-09 | 2024-04-30 | 西安电子工程研究所 | Dynamic ping-pong stack type data rearrangement realization method based on DDR3 |
| CN114666289B (en) * | 2022-03-18 | 2024-01-16 | 安方高科电磁安全技术(北京)有限公司 | Data transmission method and system based on electromagnetic shielding body |
| CN114666289A (en) * | 2022-03-18 | 2022-06-24 | 安方高科电磁安全技术(北京)有限公司 | Data transmission method and system based on electromagnetic shielding body |
| CN115328822A (en) * | 2022-08-19 | 2022-11-11 | 扬州宇安电子科技有限公司 | DDR 3-based read-write control dynamic scheduling method and storage medium thereof |
| CN115309676B (en) * | 2022-10-12 | 2023-02-28 | 浪潮电子信息产业股份有限公司 | Asynchronous FIFO read-write control method, system and electronic equipment |
| CN115309676A (en) * | 2022-10-12 | 2022-11-08 | 浪潮电子信息产业股份有限公司 | Asynchronous FIFO read-write control method, system and electronic equipment |
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