CN103106177B - Interconnect architecture and method thereof on the sheet of multi-core network processor - Google Patents
Interconnect architecture and method thereof on the sheet of multi-core network processor Download PDFInfo
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- CN103106177B CN103106177B CN201310036017.8A CN201310036017A CN103106177B CN 103106177 B CN103106177 B CN 103106177B CN 201310036017 A CN201310036017 A CN 201310036017A CN 103106177 B CN103106177 B CN 103106177B
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Abstract
The present invention discloses a kind of interconnect architecture and method thereof on multi-core network processor sheet, between the quick interconnect module in structure of the present invention, processing unit, fast shared resource by read data identification bus, write identification bus, write data bus, command line connect.At a slow speed interconnect module, processing unit, at a slow speed between shared resource by read data identification bus, write identification bus, write data bus, command line connect.Method of the present invention comprises: send order; Select command; Receive order; Judge whether order is read command; Send read data identification information; Select read data identification information; Receive read data identification information; Identification information is write in transmission; Identification information is write in selection; Identification information is write in reception; Data message is write in transmission; Data message is write in selection; Data message is write in reception.The present invention proposes that a kind of structure that can be used for multi-core network processor is simple, the interconnect architecture of higher bandwidth, good concurrency, extensibility and fairness and method thereof.
Description
Technical field
The present invention relates to network equipment field, interconnect architecture and method thereof on the sheet further relating to multi-core network processor.The present invention can make multi-core network processor relatively simply provide higher bandwidth in structure simultaneously, has good concurrency, extensibility and fairness.
Background technology
Mainstream network processor generally comprises several multithreading packet handlers (PPE), a coprocessor, dynamic RAM (DRAM) and static RAM (SRAM) control module, encryption/decryption element, network data flow interface unit etc.Coprocessor is configured each unit of network processing unit when system starts, and multiple packet handler, in the inner parallel running of network processing unit, carrys out control treatment flow process by good microcode prepared in advance.The data Storage and Processing unit such as storage unit (as DRAM and sram cell), encryption/decryption element, network data flow interface unit all belong to shared resource.There is provided and carry out data between shared resource and user thereof and be called interconnected with the structure that order control information intercoms mutually, also known as bus, it ensures the high performance deciding factor of network processing unit.
Model brave show in the paper of " research of multiprocessor systems on chips high performance bus Interconnection ", disclose the interconnect architecture of a kind of use based on shared bus.This structure is transmitted in bus owing to a timing node in office only allowing one group of independent data, therefore this structure exist deficiency be, lack extendability and communication bandwidth lower.
Zhu Yan show in the paper of the design of cross bar switch bus " in the multi-core CPU ", disclose a kind of interconnect architecture based on cross bar switch.This structure achieves point-to-point connection between processing unit and shared resource, and communication bandwidth can't be subject to the restriction of bus contention.But the deficiency that this interconnect architecture exists, will pay very large cost in cost, area at complex structure.
Summary of the invention
The object of the invention is to overcome above-mentioned the deficiencies in the prior art, propose a kind of structure and can provide higher bandwidth relatively simply simultaneously, and there is interconnect architecture and the method thereof of good concurrency, extensibility and fairness.
Interconnect architecture on the sheet of multi-core network processor of the present invention, quick interconnect module with between processing unit (1), processing unit (2), SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by read data identification bus, write identification bus, write data bus, command line be connected; At a slow speed interconnect module and processing unit (1), processing unit (2), DRAM control module (1), DRAM control module (2) read data identification bus, write identification bus, write data bus, command line be connected.
Processing unit (1) and processing unit (2), for sending command information, writing data message, receive read data identification information, write identification information.
SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, for receiving command information rapidly, writing data message, send read data identification information, write identification information.
DRAM control module (1), DRAM control module (2), for slower speeds receiving command information, writing data message, send read data identification information, write identification information.
Quick interconnect module, for by the command information of processing unit (1), processing unit (2), write data message and be sent to SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, by the read data identification information of SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, write identification information and be sent to processing unit (1), processing unit (2).
Interconnect module at a slow speed, for by the command information of processing unit (1), processing unit (2), write data message and be sent to DRAM control module (1), DRAM control module (2), by the read data identification information of DRAM control module (1), DRAM control module (2), write identification information and be sent to processing unit (1), processing unit (2).
Interconnected method on the sheet of multi-core network processor of the present invention, comprises the steps:
(1) order is sent
Processing unit (1) and processing unit (2) send data request command.
(2) select command
2a) command unit (1) carries out decoding with the moderator in command unit (2) to the command information on command line, and enable FIFO write bus, writes First Input First Output FIFO by command information.
2b) moderator monitoring FIFO dummy status bus, to not for empty First Input First Output FIFO carries out priority arbitration, the FIFO read bus that enable current highest priority First Input First Output FIFO is corresponding, reads First Input First Output FIFO by command information.
2c) the selection signal that sends according to moderator of MUX, selects corresponding path.
(3) order is received
SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2), by after carrying out decoding to the command information on command line, receive the order of mailing to this unit respectively.
(4) judge whether order is read command
4a) SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) carry out decoding to the order received, and obtain the command type that processing unit sends.
4b) judge whether the command type that processing unit sends is read command, if so, then performs step (5); If not, then step (8) is performed.
(5) read data identification information is sent
SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) send read data identification information.
(6) read data identification information is selected
Moderator 6a) in read data identify unit (1), read data identify unit (2) carries out decoding to the read data identification information in read data identification bus, enable FIFO write bus, by read data identification information write First Input First Output FIFO.
6b) moderator monitoring FIFO dummy status bus, priority arbitration is carried out to the First Input First Output FIFO not being sky, the FIFO read bus that enable current highest priority First Input First Output FIFO is corresponding, reads First Input First Output FIFO by read data identification information.
6c) the corresponding path of selection signal behavior that sends according to moderator of MUX.
(7) read data identification information is received
Processing unit (1), processing unit (2), by after carrying out decoding to the read data identification information in read data identification bus, receive the read data identification information mailing to this unit respectively.
(8) identification information is write in transmission
SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) send read data identification information.
(9) select to write identification information
9a) write identify unit (1), the moderator write in identify unit (2) carries out decoding to the identification information of writing write in identification bus, enable FIFO write bus, identification information write First Input First Output FIFO will be write.
9b) moderator monitoring FIFO dummy status bus, to not for empty First Input First Output FIFO carries out priority arbitration, the FIFO read bus that enable current highest priority First Input First Output FIFO is corresponding, will write identification information and read First Input First Output FIFO.
9c) the selection signal that sends according to moderator of MUX, selects corresponding path.
(10) identification information is write in reception
Processing unit (1), processing unit (2) by writing identification bus writing after identification information carries out decoding, receive respectively mail to this unit write identification information.
(11) data message is write in transmission
Processing unit (1), processing unit (2), respectively by after identification information carries out decoding to writing of receiving, send and write data message.
(12) select to write data message
Code translator in write data unit (1), write data unit (2), write data unit (3) according to writing identify unit (1), write identify unit (2), write mark (3) in the data select signal that sends of moderator, selection respective channels.
(13) data message is write in reception
SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) by write data bus writes after data message carries out decoding, receive respectively mail to this unit write data message.
The present invention compared with prior art has following characteristics:
First, because shared resource each in system of the present invention has Management Information Base bus, read data identification bus, writes identification bus, write data bus, overcome prior art shared bus structure bring the shortcoming of extendability difference, the quantity of shared resource of the present invention can be expanded as required.
The second, the interconnect architecture adopted due to system of the present invention makes each processing unit can concurrent working, overcomes the shortcoming that prior art communication bandwidth is lower, thus makes communication bandwidth of the present invention higher.
3rd, because interconnect architecture on sheet to be divided into quick interconnect architecture and interconnect architecture at a slow speed by system of the present invention, overcome the complex structure that between prior art processing unit and shared resource, point to point connect brings, the shortcoming that area is large, cost is high, to make on sheet of the present invention interconnect architecture relatively simple, area and cost control more satisfactory.
4th, because method of the present invention ensure that the fairness of command selection and data selection, make processing unit of the present invention and shared resource to give full play to performance.
Accompanying drawing explanation
Fig. 1 is the block scheme of structure of the present invention;
Fig. 2 is the block scheme of quick interconnect module in structure of the present invention;
Fig. 3 is the block scheme of interconnect module at a slow speed in structure of the present invention;
Fig. 4 is the process flow diagram of the inventive method.
Embodiment
Below in conjunction with accompanying drawing, structure of the present invention is further described.
With reference to accompanying drawing 1, structure of the present invention comprises processing unit (1), processing unit (2), SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2).Because SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element and DRAM control module (1), DRAM control module (2) there are differences, so be divided into quick interconnect module and interconnect module at a slow speed by interconnected on sheet on the speed receiving data and send data speed.Simultaneously in order to make interconnect architecture on sheet possess good extendability, processing unit (1), processing unit (2), SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) have respectively a group number-reading according to identification bus, write identification bus, write data bus, command line.Quick interconnect module with between processing unit (1), processing unit (2), SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by read data identification bus, write identification bus, write data bus, command line be connected; At a slow speed interconnect module and processing unit (1), processing unit (2), DRAM control module (1), DRAM control module (2) read data identification bus, write identification bus, write data bus, command line be connected; Processing unit (1) and processing unit (2), for sending command information, writing data message, receive read data identification information, write identification information; SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, for receiving command information rapidly, writing data message, send read data identification information, write identification information; DRAM control module (1), DRAM control module (2), for slower speeds receiving command information, writing data message, send read data identification information, write identification information; Quick interconnect module, for by the command information of processing unit (1), processing unit (2), write data message and be sent to SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, by the read data identification information of SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, write identification information and be sent to processing unit (1), processing unit (2); Interconnect module at a slow speed, for by the command information of processing unit (1), processing unit (2), write data message and be sent to DRAM control module (1), DRAM control module (2), by the read data identification information of DRAM control module (1), DRAM control module (2), write identification information and be sent to processing unit (1), processing unit (2).
With reference to accompanying drawing 2, the quick interconnect module in structure of the present invention comprises read data identify unit (1), read data identify unit (2), writes identify unit (1), writes identify unit (2), write data unit (1), write data unit (1), command unit (1).Each like this processing unit respectively with a group number-reading according to identify unit, write identify unit, write data unit is corresponding, and SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element can be made can to transmit and receive data fast, concurrently information.Because an order can ask multi-group data, SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element receive the number of times of order much smaller than the number of times transmitted and receive data, so be only provided with a command unit (1) in quick interconnect module between processing unit (1), processing unit (2) and SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element.Read data identify unit (1) in quick interconnect module comprises a moderator, four FIFO, MUX; The input end of moderator is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by read data identification bus; The output terminal of moderator is connected with four FIFO by FIFO write bus, FIFO read bus; The input end of four FIFO is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by read data identification bus; The output terminal of four FIFO is connected with moderator by FIFO dummy status bus; The input end of MUX is connected with four FIFO by fifo bus; The input end of MUX is connected with moderator by selecting bus; The output terminal of described MUX is connected with processing unit (1) by read data identification bus.
Read data identify unit (2) in quick interconnect module comprises a moderator, four FIFO, MUX; The input end of moderator is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by read data identification bus; The output terminal of moderator is connected with four FIFO by FIFO write bus, FIFO read bus; The input end of four FIFO is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by read data identification bus; The output terminal of four FIFO is connected with moderator by FIFO dummy status bus; The input end of MUX is connected with four FIFO by fifo bus; The input end of MUX is connected with moderator by selecting bus; The output terminal of MUX is connected with processing unit (2) by read data identification bus.
Identify unit (1) of writing in quick interconnect module comprises a moderator, four FIFO, MUX; The input end of moderator is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by writing identification bus; The output terminal of moderator is connected with four FIFO by FIFO write bus, FIFO read bus; The input end of four FIFO is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by writing identification bus; The output terminal of four FIFO is connected with moderator by FIFO dummy status bus; The input end of MUX is connected with four FIFO by fifo bus; The input end of MUX is connected with moderator by selecting bus; The output terminal of MUX is connected with processing unit (1) by writing identification bus.
Identify unit (2) of writing in quick interconnect module comprises a moderator, four FIFO, MUX; The input end of moderator is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by writing identification bus; The output terminal of moderator is connected with four FIFO by FIFO write bus, FIFO read bus; The input end of four FIFO is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by writing identification bus; The output terminal of four FIFO is connected with moderator by FIFO dummy status bus; The input end of MUX is connected with four FIFO by fifo bus; The input end of MUX is connected with moderator by selecting bus; The output terminal of MUX is connected with processing unit (2) by writing identification bus.
Write data unit (1) in quick interconnect module comprises a code translator, and the input end of code translator is connected with processing unit (1) by write data bus; The input end of code translator is connected with the moderator write in identify unit (1) by data selection bus; The output terminal of code translator is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by write data bus.
Write data unit (2) in quick interconnect module comprises a code translator, and the input end of code translator is connected with processing unit (2) by write data bus; The input end of code translator is connected with the moderator write in identify unit (2) by data selection bus; The output terminal of code translator is connected with SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element by write data bus.
Command unit (1) in quick interconnect module comprises a moderator, two FIFO, MUX, and the input end of moderator is connected with processing unit (1), processing unit (2) by command line; The output terminal of moderator is connected with two FIFO by FIFO write bus, FIFO read bus; The input end of two FIFO is connected with processing unit (1), processing unit (2) by command line; The output terminal of two FIFO is connected with moderator by FIFO dummy status bus; The input end of MUX is connected with two FIFO by fifo bus; The input end of MUX is connected with moderator by selecting bus; The output terminal of MUX is connected with DRAM control module (1), DRAM control module (2) by command line.
Moderator, for monitoring bus, the FIFO dummy status bus of input, controlling the writing and reading of First Input First Output FIFO, sending and selecting signal gating MUX; First Input First Output FIFO, for the information that buffer memory is corresponding; MUX, for the corresponding data path of gating; Code translator, for the corresponding data path of gating.
With reference to accompanying drawing 3, at a slow speed interconnect module comprise read data identify unit (3), write identify unit (3), write data unit (3), command unit (2).To receive due to DRAM control module (1), DRAM control module (2) and to send data speed slow, so processing unit (1), processing unit (2) and DRAM control module (1), only have a group number-reading according to identify unit between DRAM control module (2), write identify unit, write data unit.An order can ask multiple data, so be only provided with a command unit too.Read data identify unit (3) at a slow speed in interconnect module comprises a moderator, two FIFO, MUX; The input end of moderator is connected with DRAM control module (1), DRAM control module (2) by read data identification bus; The output terminal of moderator is connected with two FIFO by FIFO write bus, FIFO read bus; The input end of two FIFO is connected with DRAM control module (I), DRAM control module (2) by read data identification bus; The output terminal of two FIFO is connected with moderator by FIFO dummy status bus; The input end of described MUX is connected with two FIFO by fifo bus; The input end of MUX is connected with moderator by selecting bus; The output terminal of MUX is connected with processing unit (1), processing unit (2) by writing identification bus;
Identify unit (3) of writing at a slow speed in interconnect module comprises a moderator, two FIFO, MUX; The input end of moderator is connected with DRAM control module (1), DRAM control module (2) by writing identification bus; The output terminal of moderator is connected with two FIFO by FIFO write bus, FIFO read bus; The input end of two FIFO is connected with DRAM control module (1), DRAM control module (2) by writing identification bus; The output terminal of two FIFO is connected with moderator by FIFO dummy status bus; The input end of MUX is connected with two FIFO by fifo bus; The input end of MUX is connected with moderator by selecting bus; The output terminal of MUX is connected with processing unit (1), processing unit (2) by writing identification bus;
The write data unit (3) of interconnect module comprises a MUX, a code translator at a slow speed; The input end of MUX is connected with processing unit (1), processing unit (2) by write data bus; The input end of MUX is connected with the moderator write in identify unit (3) by selecting bus; The output terminal of MUX is connected with code translator by output bus; The input end of code translator is connected with the moderator write in identify unit (3) by selecting bus; The output terminal of code translator is connected with DRAM control module (1), DRAM control module (2) by write data bus;
Moderator, for monitoring bus, the FIFO dummy status bus of input, the writing and reading of control FIFO, sending and selecting signal gating MUX; First Input First Output FIFO, for the information that buffer memory is corresponding; MUX, for the corresponding data path of gating; Code translator, for the corresponding data path of gating.
With reference to accompanying drawing 4, the concrete steps of the inventive method are described below.
Step 1. sends order
Processing unit (1) and processing unit (2) send data request command concurrently, the information such as object element, command type, data address are comprised in order, can by obtaining correct operation to the decoding of command information in the operation below.
Step 2. select command
Because each first-in first-out FIFO has corresponding processing unit, simultaneously fast interconnect module and have command unit in interconnect module at a slow speed, so need moderator to carry out decoding to the command information on command line, the write of control command information.The priority algorithm of moderator needs the fairness ensureing command selection, the continuous poll of priority.
2a) command unit (1) carries out decoding with the moderator in command unit (2) to the command information on command line, and enable FIFO write bus, writes First Input First Output FIFO by command information.
2b) moderator monitoring FIFO dummy status bus, to not for empty First Input First Output FIFO carries out priority arbitration, the FIFO read bus that enable current highest priority First Input First Output FIFO is corresponding, reads First Input First Output FIFO by command information.
2c) the selection signal that sends according to moderator of MUX, selects corresponding path.
Step 3. receives order
SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2), by after carrying out decoding to the command information on command line, receive the order of mailing to this unit respectively.
Step 4. judges whether order is read command
The order that processing unit is sent has two kinds, and one is read command, and one is write order.SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) are different with the processing mode of write order for read command, so need the type judging order.
4a) SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) carry out decoding to the order received, and obtain the command type that processing unit sends.
4b) judge whether the command type that processing unit sends is read command, if so, then performs step (5); If not, then step (8) is performed.
Step 5. sends read data identification information
SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) are according to the information in order, send read data identification information, in read data identification information, comprise data and identification information.
Step 6. selects read data identification information
Because each first-in first-out FIFO has corresponding unit, simultaneously fast interconnect module and have read data identify unit in interconnect module at a slow speed, so need moderator to carry out decoding to the read data identification information in read data identification bus, control the write of read data identification information.The priority algorithm of moderator needs the fairness ensureing that read data identification information is selected, the continuous poll of priority.
Moderator 6a) in read data identify unit (1), read data identify unit (2), read data identify unit (3) carries out decoding to the read data identification information in read data identification bus, enable FIFO write bus, by read data identification information write First Input First Output FIFO.
6b) moderator monitoring FIFO dummy status bus, priority arbitration is carried out to the First Input First Output FIFO not being sky, the FIFO read bus that enable current highest priority First Input First Output FIFO is corresponding, reads First Input First Output FIFO by read data identification information.
6c) the corresponding path of selection signal behavior that sends according to moderator of MUX.
Step 7. receives read data identification information
Processing unit (1), processing unit (2), by after carrying out decoding to the read data identification information in read data identification bus, receive the read data identification information mailing to this unit respectively.
Step 8. sends and writes identification information
SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) send and write identification information.
Step 9. is selected to write identification information
Because each first-in first-out FIFO has corresponding unit, simultaneously fast interconnect module and have read data identify unit in interconnect module at a slow speed, so need moderator to carry out decoding to the command information on command line, the write of identification information is write in control.The priority algorithm of moderator needs the fairness ensureing command selection, the continuous poll of priority.
The first step, write identify unit (1), write identify unit (2), the moderator write in identify unit (3) carries out decoding to the identification information of writing write in identification bus, enable FIFO write bus, will write identification information write First Input First Output FIFO.
Second step, moderator monitoring FIFO dummy status bus, to not for empty First Input First Output FIFO carries out priority arbitration, the FIFO read bus that enable current highest priority First Input First Output FIFO is corresponding, will write identification information and read First Input First Output FIFO.
3rd step, the selection signal that MUX sends according to moderator, selects corresponding path.
Step 10. receives and writes identification information
Processing unit (1), processing unit (2), by writing identification bus writing after identification information carries out decoding, determine the object element writing identification information, receive mail to this unit write identification information.
Step 11. sends and writes data message
Processing unit (1), processing unit (2), respectively by after identification information carries out decoding to writing of receiving, obtain writing data message, send and write data message.
Step 12. is selected to write data message
The gating writing data message should be corresponding with the gating writing identification information.
Code translator in write data unit (1), write data unit (2), write data unit (3) according to writing identify unit (1), write identify unit (2), write mark (3) in the data select signal that sends of moderator, selection respective channels.
Step 13. receives and writes data message
SRAM control module (1), SRAM control module (2), network packet I/O interface unit, encryption/decryption element, DRAM control module (1), DRAM control module (2) by write data bus writes after data message carries out decoding, receive respectively mail to this unit write data message.
Claims (4)
1. interconnect architecture on the sheet of multi-core network processor, it is characterized in that, quick interconnect module with between the first processing unit, the second processing unit, a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by read data identification bus, write identification bus, write data bus, command line be connected; At a slow speed interconnect module and the first processing unit, the second processing unit, a DRAM control module, the 2nd DRAM control module read data identification bus, write identification bus, write data bus, command line be connected; Wherein:
The first described processing unit and the second processing unit, for sending command information, writing data message, receive read data identification information, write identification information;
A described SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element, for receiving command information rapidly, writing data message, send read data identification information, write identification information;
A described DRAM control module, the 2nd DRAM control module, for slower speeds receiving command information, writing data message, send read data identification information, write identification information;
Described quick interconnect module, for by the command information of the first processing unit, the second processing unit, write data message and be sent to a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element, by the read data identification information of a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element, write identification information and be sent to the first processing unit, the second processing unit;
Described interconnect module at a slow speed, for by the command information of the first processing unit, the second processing unit, write data message and be sent to a DRAM control module, the 2nd DRAM control module, by the read data identification information of a DRAM control module, the 2nd DRAM control module, write identification information and be sent to the first processing unit, the second processing unit.
2. interconnect architecture on the sheet of multi-core network processor according to claim 1, it is characterized in that, described quick interconnect module comprises the first read data identify unit, the second read data identify unit, first writes identify unit, second and write identify unit, the first write data unit, the second write data unit, the first command unit; The first read data identify unit in described quick interconnect module comprises a moderator, four FIFO, MUX; The input end of described moderator is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by read data identification bus; The output terminal of described moderator is connected with four FIFO by FIFO write bus, FIFO read bus; The input end of four described FIFO is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by read data identification bus; The output terminal of described four FIFO is connected with moderator by FIFO dummy status bus; The input end of described MUX is connected with four FIFO by fifo bus; The input end of described MUX is connected with moderator by selecting bus; The output terminal of described MUX is connected with the first processing unit by read data identification bus;
The second read data identify unit in described quick interconnect module comprises a moderator, four FIFO, MUX; The input end of described moderator is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by read data identification bus; The output terminal of described moderator is connected with four FIFO by FIFO write bus, FIFO read bus; The input end of four described FIFO is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by read data identification bus; The output terminal of described four FIFO is connected with moderator by FIFO dummy status bus; The input end of described MUX is connected with four FIFO by fifo bus; The input end of described MUX is connected with moderator by selecting bus; The output terminal of described MUX is connected with the second processing unit by read data identification bus;
In described quick interconnect module first writes identify unit comprises a moderator, four FIFO, MUX; The input end of described moderator is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by writing identification bus; The output terminal of described moderator is connected with four FIFO by FIFO write bus, FIFO read bus; The input end of four described FIFO is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by writing identification bus; The output terminal of described four FIFO is connected with moderator by FIFO dummy status bus; The input end of described MUX is connected with four FIFO by fifo bus; The input end of described MUX is connected with moderator by selecting bus; The output terminal of described MUX is connected with the first processing unit by writing identification bus;
In described quick interconnect module second writes identify unit comprises a moderator, four FIFO, MUX; The input end of described moderator is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by writing identification bus; The output terminal of described moderator is connected with four FIFO by FIFO write bus, FIFO read bus; The input end of four described FIFO is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by writing identification bus; The output terminal of described four FIFO is connected with moderator by FIFO dummy status bus; The input end of described MUX is connected with four FIFO by fifo bus; The input end of described MUX is connected with moderator by selecting bus; The output terminal of described MUX is connected with the second processing unit by writing identification bus;
The first write data unit in described quick interconnect module comprises a code translator, and the input end of described code translator is connected with the first processing unit by write data bus; The input end of described code translator is connected with the first moderator write in identify unit by data selection bus; The output terminal of described code translator is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by write data bus;
The second write data unit in described quick interconnect module comprises a code translator, and the input end of described code translator is connected with the second processing unit by write data bus; The input end of described code translator is connected with the second moderator write in identify unit by data selection bus; The output terminal of described code translator is connected with a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element by write data bus;
The first command unit in described quick interconnect module comprises a moderator, two FIFO, MUX, and the input end of described moderator is connected with the first processing unit, the second processing unit by command line; The output terminal of described moderator is connected with two FIFO by FIFO write bus, FIFO read bus; The input end of described two FIFO is connected with the first processing unit, the second processing unit by command line; The output terminal of described two FIFO is connected with moderator by FIFO dummy status bus; The input end of described MUX is connected with two FIFO by fifo bus; The input end of described MUX is connected with moderator by selecting bus; The output terminal of described MUX is connected with a DRAM control module, the 2nd DRAM control module by command line;
Described moderator, for monitoring bus, the FIFO dummy status bus of input, the writing and reading of control FIFO, sending and selecting signal gating MUX; Described FIFO, for the information that buffer memory is corresponding; Described MUX, for the corresponding data path of gating; Described code translator, for the corresponding data path of gating.
3. interconnect architecture on the sheet of multi-core network processor according to claim 1, it is characterized in that, described interconnect module at a slow speed comprises third reading Data Identification unit, the 3rd and writes identify unit, the 3rd write data unit, the second command unit; Third reading Data Identification unit in described interconnect module at a slow speed comprises a moderator, two FIFO, MUX; The input end of described moderator is connected with a DRAM control module, the 2nd DRAM control module by read data identification bus; The output terminal of described moderator is connected with two FIFO by FIFO write bus, FIFO read bus; The input end of two described FIFO is connected with a DRAM control module, the 2nd DRAM control module by read data identification bus; The output terminal of described two FIFO is connected with moderator by FIFO dummy status bus; The input end of described MUX is connected with two FIFO by fifo bus; The input end of described MUX is connected with moderator by selecting bus; The output terminal of described MUX is connected with the first processing unit, the second processing unit by writing identification bus;
In described interconnect module at a slow speed the 3rd writes identify unit comprises a moderator, two FIFO, MUX; The input end of described moderator is connected with a DRAM control module, the 2nd DRAM control module by writing identification bus; The output terminal of described moderator is connected with two FIFO by FIFO write bus, FIFO read bus; The input end of two described FIFO is connected with a DRAM control module, the 2nd DRAM control module by writing identification bus; The output terminal of described two FIFO is connected with moderator by FIFO dummy status bus; The input end of described MUX is connected with two FIFO by fifo bus; The input end of described MUX is connected with moderator by selecting bus; The output terminal of described MUX is connected with the first processing unit, the second processing unit by writing identification bus;
3rd write data unit of described interconnect module at a slow speed comprises a MUX, a code translator; The input end of described MUX is connected with the first processing unit, the second processing unit by write data bus; The input end of described MUX is connected with the 3rd moderator write in identify unit by selecting bus; The output terminal of described MUX is connected with code translator by output bus; The input end of described code translator is connected with the 3rd moderator write in identify unit by selecting bus; The output terminal of described code translator is connected with a DRAM control module, the 2nd DRAM control module by write data bus;
Described moderator, for monitoring bus, the FIFO dummy status bus of input, the writing and reading of control FIFO, sending and selecting signal gating MUX; Described FIFO, for the information that buffer memory is corresponding; Described MUX, for the corresponding data path of gating; Described code translator, for the corresponding data path of gating.
4. interconnected method on the sheet of multi-core network processor, comprises the steps:
(1) order is sent
First processing unit and the second processing unit send data request command;
(2) select command
Moderator 2a) in the first command unit and the second command unit carries out decoding to the command information on command line, and enable FIFO write bus, writes First Input First Output FIFO by command information;
2b) moderator monitoring FIFO dummy status bus, to not for empty First Input First Output FIFO carries out priority arbitration, the FIFO read bus that enable current highest priority First Input First Output FIFO is corresponding, reads First Input First Output FIFO by command information;
2c) the selection signal that sends according to moderator of MUX, selects corresponding path;
(3) order is received
One SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element, a DRAM control module, the 2nd DRAM control module, by after carrying out decoding to the command information on command line, receive the order of mailing to this unit respectively;
(4) judge whether order is read command
4a) a SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element, a DRAM control module, the 2nd DRAM control module carry out decoding to the order received, and obtain the command type that processing unit sends;
4b) judge whether the command type that processing unit sends is read command, if so, then performs step (5); If not, then step (8) is performed;
(5) read data identification information is sent
One SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element, a DRAM control module, the 2nd DRAM control module send read data identification information;
(6) read data identification information is selected
Moderator 6a) in the first read data identify unit, the second read data identify unit carries out decoding to the read data identification information in read data identification bus, enable FIFO write bus, by read data identification information write First Input First Output FIFO;
6b) moderator monitoring FIFO dummy status bus, priority arbitration is carried out to the First Input First Output FIFO not being sky, the FIFO read bus that enable current highest priority First Input First Output FIFO is corresponding, reads First Input First Output FIFO by read data identification information;
6c) the corresponding path of selection signal behavior that sends according to moderator of MUX;
(7) read data identification information is received
First processing unit, the second processing unit, by after carrying out decoding to the read data identification information in read data identification bus, receive the read data identification information mailing to this unit respectively;
(8) identification information is write in transmission
One SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element, a DRAM control module, the 2nd DRAM control module send read data identification information;
(9) select to write identification information
9a) first write the moderator that identify unit, second writes in identify unit and decoding is carried out to the identification information of writing write in identification bus, enable FIFO write bus, identification information write First Input First Output FIFO will be write;
9b) moderator monitoring FIFO dummy status bus, to not for empty First Input First Output FIFO carries out priority arbitration, the FIFO read bus that enable current highest priority First Input First Output FIFO is corresponding, will write identification information and read First Input First Output FIFO;
9c) the selection signal that sends according to moderator of MUX, selects corresponding path;
(10) identification information is write in reception
First processing unit, the second processing unit by writing identification bus writing after identification information carries out decoding, receive respectively mail to this unit write identification information;
(11) data message is write in transmission
First processing unit, the second processing unit, respectively by after identification information carries out decoding to writing of receiving, send and write data message;
(12) select to write data message
Code translator in first write data unit, the second write data unit, the 3rd write data unit is write identify unit, second according to first and is write identify unit, the 3rd and write the data select signal that moderator in identify unit sends, and selects respective channels;
(13) data message is write in reception
One SRAM control module, the 2nd SRAM control module, network packet I/O interface unit, encryption/decryption element, a DRAM control module, the 2nd DRAM control module by write data bus writes after data message carries out decoding, receive respectively mail to this unit write data message.
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