CN104572574B - Ethernet controller IP kernel and method based on gigabit Ethernet vision agreement - Google Patents
Ethernet controller IP kernel and method based on gigabit Ethernet vision agreement Download PDFInfo
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Abstract
The invention discloses a kind of ethernet controller IP kernel based on gigabit Ethernet vision agreement, it is made up of control module, PHY management interfaces module, transmission control module, flow control module, receive and control module, realized using FPGA, it then follows Avalon Memory Mapped interface specifications and gmii interface specification.The present invention is the special IP kernel designed according to GigE Vision agreements feature, the reception of GigE camera images and automatic storage can be realized, while IMAQ is realized, overcome the shortcomings such as traditional ethernet controller resource occupation amount is big, CPU usage is high, IMAQ efficiency is low, the characteristics of using FPGA parallel processings, improve information rate and system real time.Under the same testing conditions, realize IMAQ using this patent, than altera corp three fast ethernet ips examine and make cuts it is few more than half FPGA resource consumption.
Description
Technical field
It is more particularly to a kind of to be based on gigabit Ethernet vision (GigE the present invention relates to a kind of image capturing system
Vision) the gigabit Ethernet control unit in the embedded imaging system of agreement.
Background technology
Image capture device is broadly divided into both direction at present, first, being based on personal computer (Personal
Computer, PC) machine image pick-up card, second, the image capturing system based on embedded microprocessor.
Due to external controller interface (Peripheral Component Interconnect, PCI) EBI bandwidth
It is relatively low, and shared bus structures are used, therefore the image pick-up card product based on pci bus is eliminated substantially.Though
Right PCI Express buses of new generation are greatly improved compared to the performance of traditional pci bus, but it still can not
Solves the problems such as PC system real times are poor, stability is bad and cost is high, therefore, the image pick-up card product based on PC is
It is difficult to meets the needs of modern industry detection.At present, the image capture device of main flow is mainly based upon embedded microprocessor
Image capturing system.
With the quickening of Informatization Development speed, people also increasingly increase the demand of transmission of video images bandwidth.Currently
The camera interface standard Camera Link interfaces of main flow, IEEE1394 interfaces, USB interface etc. can not meet people to figure
As the requirement of information pickup speed.Unlike, gigabit Ethernet (GigE) interface connects using gigabit Ethernet as data transfer
Mouthful, while view data transmission is realized, without extra collecting device, and there is absolute superiority bandwidth.
But the image capturing system for being currently based on common Gigabit Ethernet controller be primarily present it is following two important
Problem：
First, in order to realize GigE Vision agreements, design must use general ethernet controller.So towards logical
The ethernet controller designed with function, often structure is more complicated, and resource occupation amount is big.Second, CPU usage is too high.For
Reception view data, it is necessary to using software to Ethernet protocol (Internet Protocol, IP), UDP
(User Datagram Protocol, UDP) and GigE Vision protocol datas carry out layering, and this will necessarily increase
The processing load of CPU (Central Processing Unit, CPU), improve CPU usage.
Application No. 201010603189.5, a kind of entitled " the machine vision system based on FPGA and DSP of patent of invention
System ", the system are used the collection and pretreatment of FPGA internal hardware circuit realiration images, the logic control of system are realized using DSP
The advanced processes of system and image.The image capture module of the system has following defect：
(1) ethernet controller uses the fast ethernet medium access controllers of 10/100/1000M tri-, although powerful,
But its realization needs to consume the storage money of more than 4800 individual logic units, more than 5300 individual register resources and 19000 multibytes
Source, consumed resource is huge, adds the cost of hardware development；
(2) software carries out task scheduling using μ C/OS systems, and IP, udp protocol package and parsing are provided soft using system
Part protocol stack, software complexity is high, and system burden is big, poor real；
(3) realization of GigE Vision agreements is completed by software, will necessarily due to the limitation of embedded system real-time
The judgement of packet drop is influenceed, causes missing and the damage of view data.
Application No. 201310328995.X, patent of invention are entitled " a kind of embedded parallel more based on GigE interfaces
Railway digital image capturing system ", the system are used based on the digital image acquisition embedded device of GigE interfaces to multichannel GigE
Camera image is acquired, and transmits view data to host computer according to the order of host computer, and it focuses on to multiway images
Signal is acquired, and is uploaded to PC and handled.The system has following a few point defects：
(1) transmitting-receiving of its network data still needs to software using the realization of the procotol such as commodity ethernet controller, IP, UDP
Realize that system burden is big, CPU usage is high；
(2) network data received needs to be carried in real time by system arbitrament module, could be by GigE protocol analysis
Module is read, and the view data that GigE protocol resolution modules parse to obtain must be read by system arbitrament module again after, is restored again into
Corresponding memory.This mechanism causes substantial amounts of data transmission back in bus, considerably increases bus occupancy, improves
The complexity of system arbitrament module, influence the real-time of system；
(3) although the system is parsed using hardware resource to GigE interface data bags, GVSP agreements are not directed to
The optimization on hardware is carried out, the retransmission mechanism of packet still needs to software realization, is extremely difficult to higher real-time, influences picture number
According to integrality and image-receptive frame per second.
The content of the invention
Goal of the invention：
Lacked to overcome that traditional ethernet controller resource occupation amount is big, CPU usage is high, IMAQ efficiency is low etc.
Point, the present invention optimize to traditional ethernet controller, the special IP kernel designed according to GigE Vision agreements feature.
The present invention realizes IP, address resolution protocol (Address Resolution Protocol, ARP), UDP, thousand using hardware logic
The package of mbit ethernet visual spatial attention agreement (GigE Vision Control Protocol, GVCP) and parsing.Meanwhile this hair
Bright the characteristics of utilizing FPGA parallel processings, in the case where being assisted without CPU, Avalon Memory-Mapped main interfaces are controlled,
, automatically will figure according to the ID of gigabit Ethernet vision stream protocol (GigE Vision Stream Protocol, GVSP) packet
In the memory headroom specified as data deposit user, information rate and system real time are improved.
Technical scheme：
A kind of ethernet controller IP kernel based on GigE Vision agreements, it is field programmable gate array (Field
Programmable Gate Array, FPGA) in an IP core, specifically by MAC control modules, PHY management interfaces
Module, control module, flow control module, receive and control module composition are sent, realized using FPGA, mapped by Avalon internal memories
Type (Memory-Mapped) is connected from interface with NIOS processors, passes through Avalon Memory-Mapped main interfaces and image
RAM connections are stored, pass through PHY management interfaces and gigabit medium-specific interface (Gigabit Media Independent
Interface, GMII) it is connected with physical layer (PHY).
MAC control modules include register cell, module control unit and bus control unit, receive NIOS processors
The bus message of transmission, control other modules；
PHY management interfaces module is used to access PHY registers, according to PHY access controls signal and PHY management interface sequential
Specification, MDC clocks and MDIO data are automatically generated, control PHY management interfaces, access PHY registers, generation PHY accesses feedback
Signal；
Send control module and include the first two-port RAM, agreement package module, the second two-port RAM and GMII transmissions
Module, corresponding Ethernet is sent automatically according to control signal, ARP transmission control signals and packet loss repeating transmission control signal is sent
Packet, generation send feedback signal；
Flow control module includes image storage control module and stream detection module, according to storage control signal, flow control
Signal, GVSP data are read by GVSP data read bus, view data write-in image is stored in RAM, and generate storage
Feedback signal, while packet drop is detected, control packet loss retransmits control signal；
Receive and control module includes the 3rd two-port RAM, the 4th two-port RAM, the 5th two-port RAM, protocol analysis mould
Block, asynchronous FIFO and GMII receiving modules, Ethernet data bag is received, it is parsed according to control signal is received, it is raw
Into reception feedback signal and flow control signals, and sent respectively by receiving data read bus and GVSP data read bus
The data of parsing.
Preferably, register cell is used to deposit control information, status information, native network address information and camera net
Network address information；The information and the feedback information of reception that module control unit is deposited according to register cell, generation PHY access control
Signal, transmission control signal, reception control signal and storage control signal processed；Bus control unit is to from Avalon
Memory-Mapped is parsed from the address of interface and control signal, realizes visits of the CPU to address space different in IP kernel
Ask, including register cell, the first two-port RAM, the 3rd two-port RAM and the 4th two-port RAM.
Preferably, the first two-port RAM will send data by sending data write bus reception transmission data and caching
Clock zone where from system is transformed into clock zone where GMII sending modules；Agreement package module include IP agreement package module,
Udp protocol package module, GVCP agreement package modules and ARP protocol package module, according to control signal is sent, automatic is hair
Data packet procotol is sent, first data will be wrapped and be stored in the second two-port RAM；GMII sending modules include CRC-32 generation moulds
Block, the data of the first two-port RAM and the second two-port RAM are combined into ethernet frame and sent；CRC-32 generation modules
Automatically generate 32 CRC check codes.
Preferably, flow detection module and read the 5th two-port RAM, view data bag ID number and figure are obtained according to GVSP agreements
As data, packet drop, the automatic ID number for calculating lost data packets are detected, generation packet loss retransmits control signal；Image storage control
Molding root tuber controls Avalon Memory-Mapped main interfaces, automatically according to view data bag ID number and storage control signal
Calculating memory addresses, view data storage is stored in RAM to image.
Preferably, GMII receiving modules embed CRC-32 inspection modules, receiving network data bag, are written into asynchronous FIFO
In, and it is verified；The Ethernet data that asynchronous FIFO caching receives, data are received into clock place clock zone from GMII
Clock zone where being transformed into protocol resolution module；Protocol resolution module include ARP protocol parsing module, IP agreement parsing module,
Udp protocol parsing module, GVCP protocol resolution modules and GVSP protocol resolution modules, parsed to receiving data, and will
The data of parsing are stored in different two-port RAMs respectively；The GVCP data that 3rd two-port RAM caching receives；5th both-end
The GVSP data that mouth RAM cachings receive；Other data that 4th two-port RAM caching receives.
The image data transfer method of the ethernet controller IP kernel based on GigE Vision agreements of the invention is：
Bus control unit read Avalon bus line commands, and according to read-write, address information control register unit,
The read-write of first two-port RAM, the 3rd two-port RAM and the 4th two-port RAM.
When sending Ethernet data,
[1] bus control unit (1.3) will send data and write in the first two-port RAM (3.1) according to bus address,
By in control command write-in register cell (1.1)；
[2] the real-time detected register unit (1.1) of module control unit (1.2), after detecting transmission order, generation is corresponding
Transmission control signal (8)；
[3] agreement package module (3.2), which is read, sends control signal (8), generates corresponding protocol package head, and will wrap first number
According in the second two-port RAM of deposit (3.3)；
[4] GMII sending modules (3.4) read the number in the first two-port RAM (3.1) and the second two-port RAM (3.3)
According to formation ethernet frame is transmitted；
[5] at the same time, send control module (3) and produce transmission feedback signal (10)；
[6] module control unit (1.2) detection in real time sends feedback signal (10), and feedback information is write into register list
First (1.1)；
Entirely the ethernet data acceptance flow of IP kernel is：
(1) GMII receiving modules (5.6) real-time reception broadcast data packet or send to local mac address packet, and
Write data into asynchronous FIFO (5.5)；
(2) protocol resolution module (5.4) reads the data in asynchronous FIFO (5.5), and the agreement of packet is solved
Analysis；
(3) if packet is ARP request packet, ARP protocol parsing module (5.4.1) produces according to request data
ARP request signal, request send control module (3) and send arp reply packet；
(4) if packet is IP packets, IP agreement parsing module (5.4.5) further enters to the agreement of packet
Row parsing, judges whether the packet is UDP message bag；
(5) if packet is UDP message bag, udp protocol parsing module (5.4.4) judges destination slogan, and judging should
Whether packet is GVCP packets or GVSP packets；
(6) if packet is GVCP packets, GVCP protocol resolution modules (5.4.2) parsing packet, by GVCP numbers
According to the 3rd two-port RAM (5.1) of write-in, and produce corresponding reception feedback signal (12)；
(7) if packet is GVSP packets, GVSP protocol resolution modules (5.4.3) parsing packet, by GVSP numbers
According to the 5th two-port RAM (5.3) of write-in, and produce flow control signals (19)；
(8) other packets are write the 4th two-port RAM (5.2) by protocol resolution module (5.4), and are produced corresponding
Receive feedback signal (12)；
(9) after flow control module (4) receives flow control signals (19), control-flow detection module (4.2) reads the 5th pair
Port ram (5.3)；
(10) flow detection module (4.2) in the data of reading obtain GVSP packets Block ID, Packet ID with
And view data, and packet drop is judged according to Block ID and Packet ID, if it find that packet loss, then produce and lose
Packet retransmission control signal (15)；
(11) image storage control module (4.1) obtains image storage first address, root from storage control signal (14)
The storage address of view data in the packet is calculated according to the Packet ID of view data and the length gauge of view data, and
Avalon Memory-Mapped main interfaces are controlled by view data write-in image storage RAM；When the write-in complete image of one width
After data, image storage control module (4.1) then produces storage feedback signal (13).
(12) compared with prior art, the present invention has advantages below：
(13) present invention is directed to the ethernet controller of GigE Vision Protocol Design lightweights, compatible GigE
Vision 1.0 realizes protocol filtering with parsing, the design of flattening is big with the agreements of GigE Vision 2.0 on hardware logic
The big complexity for reducing ethernet controller, reduces the consumption on hardware logic, while image transmitting speed is improved, reduces
The cost of system.
(14) present invention using the automatic package of hardware logic or parses the network data based on GigE Vision agreements,
So that the package of network data and filtering do not need the intervention of software, so as to greatly reduce the burden of software systems.
(15) automatic Mosaic of the present invention and storage image data, view data receive process can completely disengage CPU and
Independent operating, from utmost reducing CPU usage.
(16) are developed using the present invention, user need not structure multitask software environment, also need not grasp with
The too building form of net frame, IP agreement, udp protocol, the particular content of GigE Vision agreements, need not more be concerned about GVSP data
Processing method, user need only add IP kernel of the present invention in systems, register is simply configured,
To realize the collection of the access of GigE cameras and image, so as to reduce the development difficulty of image capturing system to the full extent,
Large-scale promotion and application can be realized.
(17) illustrate
(18) Fig. 1 is the hardware system block diagram of case study on implementation of the present invention；
(19) Fig. 2 is the system module block diagram of case study on implementation of the present invention；
(20) Fig. 3 is the interface diagram of the present invention；
(21) Fig. 4 is the structured flowchart of the present invention；
(22) Fig. 5 is the process chart of the present invention；
(23) Fig. 6 is the transmission operational flowchart of case study on implementation of the present invention；
(24) Fig. 7 is the reception operational flowchart of case study on implementation of the present invention.
(25) embodiment
(26) reference picture 1, a kind of ethernet controller IP kernel based on GigE Vision agreements use FPGA system
Realized, main hardware includes FPGA module, EPCS management modules, power management module, SSRAM, PHY used by implementation
Chip and its module and GigE cameras, the specific chip used are：
The FPGA that (27) described implementation system uses is using the Stratix II series of altera corp
EP2S60F672C3N chips；
The SSRAM that (28) described implementation system uses for Cypress companies CY7C1380D chips；
The PHY chip that (29) described implementation system uses for Marvell companies 88E1111 chips；
The GigE cameras that (30) described implementation system uses for Basler companies acA640-90gc cameras.
(31) reference picture 2, case study on implementation used IP modules on FPGA include NIOS II microprocessors, outer
Portion's RAM module interface, image storage module, the ethernet controller IP kernel of the present invention based on GigE Vision agreements
And other modules.
(32) reference picture 3, the ethernet controller based on GigE Vision agreements realized in the implementation case
The interface of IP kernel includes Avalon Memory-Mapped main interfaces, Avalon Memory-Mapped connect from interface, PHY management
Mouth and gmii interface.
The Avalon Memory-Mapped main interfaces signal that (33) described GVSP receiving modules provide is piece choosing letter
Number, request waiting signal, write enable signal, read enable signal, 32 bit address signals, 32 place readings it is believed that number and 32 write number
It is believed that number.
Avalon Memory-Mapped described in (34) from interface signal be clock signal of system, 125MHz
GMII tranmitting data registers, systematic reset signal, chip selection signal, read enable signal, write enable signal, 14 bit address signals, 32 write
Data-signal and 32 place readings it is believed that number.
PHY management interfaces signal described in (35) is 2MHz MDC signals and MDIO signals.
GMII transmission interfaces signal described in (36) is 125MHz GMII tranmitting data registers, sends enable signal, sends
Error signal, data-signal is sent, clock is received, receives data valid signal, receive error signal, receive data-signal, carry
Ripple intercepts signal and collision detection signal.
(37) reference picture 4, the ethernet controller based on GigE Vision agreements realized in the implementation case
IP kernel includes control module 1, PHY management interfaces module 2, sends control module 3, flow control module 4, receive and control module 5, leads to
Cross Avalon Memory-Mapped to be connected with CPU from interface, deposited by Avalon Memory-Mapped main interfaces with image
RAM connections are stored up, are connected by PHY management interfaces and gmii interface with PHY.
Control module 1 described in (38) includes register cell 1.1, module control unit 1.2 and bus marco
Unit 1.3, the bus message that NIOS processors are sent is received, controls other modules.Register cell 1.1 is used to deposit control letter
Breath, status information, native network address information and camera network address information；Module control unit 1.2 is believed according to register
Breath, PHY access feedback signal 7, transmission feedback signal 10, receive feedback signal 12 and store the generation of feedback signal 13 PHY and access
Control signal 6, send control signal 8, receive control signal 11 and storage control signal 14；Bus control unit 1.3 obtains
Avalon Memory-Mapped are from interface message, operation note unit 1.1, the first two-port RAM 3.1, the 3rd dual-port
The two-port RAMs 5.2 of RAM 5.1 or the 4th.
(39) described MAC control modules 1, which have, receives interrupt requests function, and module control unit 1.2 is according to reception
Feedback signal 12, storage feedback signal 13 produce interrupt signal, and CPU judges interrupt type by reading reception state register.
Register cell 1.1 described in (40) includes MAC control registers, mac state register, interrupts control deposit
Device, interrupt status register, PHY control registers, PHY read data registers, PHY write data registers, transmission control deposit
Device, receive control register, flow control register, the machine MAC Address register, local IP address register, GVCP port numbers
Register, GVSP port numbers register, camera MAC Address register and camera IP address register.
Bus control unit 1.3 described in (41) to from Avalon Memory-Mapped from the address of interface and
Control signal is parsed, and realizes that CPU conducts interviews to address space different in IP kernel, wherein the distribution of the address such as institute of table 1
Show：
(42)
The bus control unit (1.3) of (43) table 1 is distributed the address in IP kernel different access space
(44) offset
(one zero eight) 0x014
(one by one six)
PHY access controls signal 6 described in (one by one seven) for PHY access enable signal, 5 PHY register address signals,
32 PHY register writes data-signals and 32 PHY register reading data signals.
It is PHY management interface module busy signals that PHY described in (one by one eight), which accesses feedback signal 7,.
Transmission control signal 8 described in (one by one nine) is the machine and the bit mac address of camera 48,32 IP of the machine and camera
16 location, the machine GVCP port numbers, send enable signal, 16 transmission protocol types and 9 transmission data length (units：
Byte).
Transmission feedback signal 10 described in (one two zero) is transmission control module busy signal.
Reception control signal 11 described in (one two one) is the machine and 32 the bit mac address of camera 48, the machine and camera IP
16 address, 16 GVCP port numbers of the machine and the machine GVSP port numbers.
Reception feedback signal 12 described in (one two two) is receipt completion signal, 16 reception protocol types, 11 GVSP
Data address and 11 reception data length (units：Byte).
Storage control signal 14 described in (one two three) stores first address for storage enable signal and 32 bit images.
Storage feedback signal 13 described in (one two four) completes signal for image storage.
PHY management interfaces module 2 described in (one two five) is used to access PHY registers, according to PHY access controls signal 6
And PHY management interface timing sequence specifications, MDC clocks and MDIO data are automatically generated, controls PHY management interfaces, accesses PHY deposits
Device, generation PHY access feedback signal 7.
(one two six) send control module 3 and include the first two-port RAM 3.1, agreement package module 3.2, the second dual-port
RAM 3.3 and GMII sending modules 3.4, control is retransmitted according to control signal 8, ARP transmission control signals 17 and packet loss is sent
Signal 15 processed sends corresponding Ethernet data bag automatically, and generation sends feedback signal 10；First two-port RAM 3.1 passes through hair
Send data write bus 9 to receive to send data and cache, data will be sent and be transformed into GMII transmission moulds from clock zone where system
The place clock zone of block 3.4；Agreement package module 3.2 include IP agreement package module 3.2.1, udp protocol package module 3.2.2,
GVCP agreements package module 3.2.3 and ARP protocol package module 3.2.4, control letter is sent according to transmission control signal 8, ARP
Numbers 17 and packet loss retransmit control signal 15, it is automatic to send data packet procotol, first data will be wrapped and be stored in the second both-end
Mouth RAM 3.3；Second two-port RAM 3.3 is used for the bag head data for storing generation；GMII sending modules 3.4 are given birth to comprising CRC-32
Into module 3.4.1, it is concurrent that the data of the first two-port RAM 3.1 and the second two-port RAM 3.3 are combined into ethernet frame
Send；CRC-32 generation modules 3.4.1 automatically generates 32 CRC check codes；
Transmission control module (3) described in (one two seven) has ARP protocol automatic answer function, can be sent according to ARP
Control signal (17), it is automatic to send arp reply packet, and the MAC Address of host computer and IP address are recorded.
Transmission control module (3) described in (one sixteen) has GVSP data packet retransmission request functions, being capable of packet loss repeating transmission
Control signal (15), automatically generated data packet retransmission order, request camera retransmit corresponding GVSP packets.
The first two-port RAM 9 described in (one two nine) realizes that the first two-port RAM 9 is write using memory block on FPGA pieces
Port uses system clock, and data bit width is 32, and read port uses GMII tranmitting data registers, and data are a width of 8.
ARP described in (one three zero) send control signal 17 be ARP send request signal, 48 host MAC address and
32 host IP address.
Packet loss described in (one three one) retransmits control signal 15 to retransmit request signal, 16 GVSP port numbers, 24 weights
Send out the minimum ID and maximum ID of packet.
Flow control module 4 described in (one three two) includes image storage control module 4.1 and stream detection module 4.2, leads to
Cross GVSP data read bus 18 and read GVSP data, by view data write-in image storage RAM, generation stores feedback signal
13, while packet drop is detected, control packet loss retransmits control signal 15.Flow detection module 4.2 and read the 5th two-port RAM
5.3, view data bag ID number and view data are obtained according to GVSP agreements, detect packet drop, generation packet loss retransmits control letter
Numbers 15.For image storage control module 4.1 according to view data bag ID number, control Avalon Memory-Mapped main interfaces will
In view data write-in image storage RAM.
Receive and control module 5 described in (one three three) includes the 3rd two-port RAM 5.1, the 4th two-port RAM 5.2, the
Five two-port RAMs 5.3, protocol resolution module 5.4, asynchronous FIFO 5.5 and GMII receiving modules 5.6, receive ether netting index
According to bag, it is parsed according to control signal 11 is received, and generate and receive feedback signal 12 and flow control signals 19.GMII connects
Receive module 5.6 and embed CRC-32 inspection module 5.6.1, receiving network data bag, be written into asynchronous FIFO 5.5, and to it
Verified；The Ethernet data that the caching of asynchronous FIFO 5.5 receives, data are received into clock place clock zone from GMII and changed
Clock zone where to protocol resolution module；The GVCP data that 3rd two-port RAM 5.1 caching receives；5th two-port RAM
The GVSP data that 5.3 cachings receive；Other data that 4th two-port RAM 5.2 caching receives；Protocol resolution module 5.4 includes
ARP protocol parsing module 5.4.1, IP agreement parsing module 5.4.5, udp protocol parsing module 5.4.4, GVCP protocol analysis mould
Block 5.4.2 and GVSP protocol resolution module 5.4.3, asynchronous FIFO 5.5 is read according to control signal 11 is received, to reception
Data are parsed, and the data of parsing are stored in different two-port RAMs respectively, and the 3rd two-port RAM 5.1 caching connects
The GVCP data of receipts；The GVSP data that 5th two-port RAM 5.3 caching receives；4th two-port RAM 5.2 caching receives
Other data.3rd two-port RAM 5.1, the data of the 4th two-port RAM 5.2 caching are by receiving data read bus 16
Send to MAC control modules 1, the data of the 5th two-port RAM 5.3 caching and sent by GVSP data read bus 18 to stream
Control module 4.
The 3rd two-port RAM 5.1, the 4th two-port RAM 5.2 and the 5th two-port RAM 5.3 described in (one three four)
Realized using memory block on FPGA pieces, write port uses GMII tranmitting data registers, and data bit width is 32, when read port uses system
Clock, data are a width of 8.
Asynchronous FIFO 5.5 described in (one three five) is realized using memory block on FPGA pieces, when write port is received using GMII
Clock, data bit width are 32, and read port uses GMII tranmitting data registers, and data are a width of 8.
(one three six) reference picture 5, the ethernet controller based on GigE Vision agreements realized in the implementation case
The workflow of IP kernel is：
Parsings of (pseudo-ginseng) the Avalon Memory-Mapped from interface：
The implementing monitoring Avalon Memory-Mapped of (one three eight) bus control unit 1.3 are from interface；Detection lug choosing letter
Number, read/write signal and address signal；
When (three nine-day periods after the winter solstice) chip selection signal is effective, bus control unit 1.3 judges according to read/write signal and address signal
The resource accessed needed for CPU, and read/write is carried out to respective resources and enabled, while by address resolution so that CPU is to addressing space
Operated.
(one four zero) Ethernet data is sent：
The detection in real time of (one four one) module control unit 1.2 sends feedback signal 10, and will send state write-in register
In unit 1.1, read for CPU；
1.2 real-time detected register unit 1.1 of (one four two) module control unit, after detecting transmission order, generate phase
The transmission control signal 8 answered；
(one four three) agreement package module 3.2, which is read, sends control signal 8, and it is first and bag is first to generate corresponding protocol package
Data are stored in the second two-port RAM 3.3；
(one four four) GMII sending modules 3.4 read the number in the first two-port RAM 3.1 and the second two-port RAM 3.3
According to formation ethernet frame is transmitted；
(one four five) at the same time, send control module 3 and produce transmission feedback signal 10；.
(one four six) Ethernet data is received：
The real-time reception broadcast data packet of (one four seven) GMII receiving modules 5.6 is sent to the packet of local mac address,
And write data into asynchronous FIFO 5.5；
(one four eight) protocol resolution module 5.4 reads the data in asynchronous FIFO 5.5, and the agreement of packet is solved
Analysis；
(one four nine) if packet is ARP request packet, ARP protocol parsing module 5.4.1 is according to request data, production
Raw ARP request signal, request send control module 3 and send arp reply packet；
(First Five-Year Plan zero), IP agreement parsing module 5.4.5 was further to the agreement of packet if packet is IP packets
Parsed, judge whether the packet is UDP message bag；
(May Day), udp protocol parsing module 5.4.4 judged destination slogan if packet is UDP message bag, judged
Whether the packet is GVCP packets or GVSP packets；
(First Five-Year Plan two), GVCP protocol resolution modules 5.4.2 parsed packet, by GVCP if packet is GVCP packets
Data write the 3rd two-port RAM 5.1, and produce corresponding reception feedback signal 12；
(First Five-Year Plan three), GVSP protocol resolution modules 5.4.3 parsed packet, by GVSP if packet is GVSP packets
Data write the 5th two-port RAM 5.3, and produce flow control signals 19；
Other packets are write the 4th two-port RAM 5.2 by (the May 4th) protocol resolution module 5.4, and are produced corresponding
Receive feedback signal 12；
After (First Five-Year Plan five) flow control module 4 receives flow control signals 19, control-flow detection module 4.2 reads the 5th both-end
Mouth RAM 5.3；
(First Five-Year Plan six) stream detection module 4.2 obtains Block ID, the Packet ID of GVSP packets in the data of reading
And view data, and packet drop is judged according to Block ID and Packet ID, if it find that packet loss, then produce
Packet loss retransmits control signal 15；
(First Five-Year Plan seven) image storage control module 4.1 obtains image storage first address from storage control signal 14, according to
The Packet ID of view data and the length gauge of view data calculate the storage address of view data in the packet, and control
View data write-in image is stored RAM by Avalon Memory-Mapped main interfaces processed；When the write-in complete picture number of one width
According to rear, image storage control module 4.1 then produces storage feedback signal 13.
(First Five-Year Plan eight) reference picture 6, the operating process that CPU sends needed for Ethernet data are：
(First Five-Year Plan nine), which reads, sends status register, judges to send whether control module 3 is in transmission state, if sending control
Molding block 3 sends state, then is waited；
(one six zero) return if the stand-by period is long and send miscue, and CPU needs to match somebody with somebody IP kernel again
Put；
(one six one) are in idle state if sending control module 3, and CPU will send data and write the first two-port RAM
Address space where 3.1, corresponding register space is write by control command；
After (one six two) IP kernel receives transmission order, start to sending data packet, and be transmitted.
(one six three) reference picture 7, the operating process needed for CPU reception Ethernet datas or view data are：
(one six four) CPU judges reception state by inquire-receive status register mode or by interrupt mode, and
Call reception processing function；
(parathion) CPU reads reception state register and obtains the data type received, data type be divided into GVCP data,
Single image data or other network datas；
(one six six) if GVCP data, CPU reads GVCP data as needed, and carries out corresponding operating；
(one six seven) if view data, CPU according to the actual requirements, is handled image, and performs corresponding operating；
(one six eight) if other data, CPU reads data as needed, and carries out corresponding operating.
(one six nine) in the implementation case, the ethernet controller IP kernel based on GigE Vision agreements consumes about
The storage resource of more than 2000 individual logic units, more than 1500 individual register resources and 8000 multibytes, in collection image pixel
Under the conditions of 640 × 480 gray level image, it is per second that image-receptive speed has reached 90 frames, and CPU usage is less than 1%；Same
Test condition under, examine this existing function using Altera three fast ethernet ips, consume individual logic unit, 5300 more than 4800
The storage resource of multiple register resources and about 19000 bytes, in addition, the reception of image needs extra addition DMA resources,
The parsing person of needing to use of GVSP packets is completed by software, and development cost is high, resource occupation amount is big.
(one seven zero) these are only example of the present invention, not form any limitation of the invention, therefore, appoint
What what those skilled in the art can think change, should all fall in the protection domain of the application.
Claims (10)
- A kind of 1. ethernet controller IP kernel based on GigE Vision agreements, it is characterised in that：Whole IP kernel is by MAC control modules (1), PHY management interfaces module (2), transmission control module (3), flow control module (4), receive and control module (5) form, using hardware logic realize IP, ARP, UDP and GigE Vision agreements package and Parsing, it then follows Avalon Memory-Mapped interface specifications and gmii interface specification；MAC control modules (1) include register cell (1.1), module control unit (1.2) and bus control unit (1.3), The bus message that NIOS processors are sent is received, controls other modules；PHY management interfaces module (2) is used to access PHY registers, during according to PHY access controls signal (6) and PHY management interfaces Sequence specification, MDC clocks and MDIO data are automatically generated, control PHY management interfaces, access PHY registers, generation PHY accesses anti- Feedback signal (7)；Send control module (3) and include the first two-port RAM (3.1), agreement package module (3.2), the second two-port RAM (3.3) and GMII sending modules (3.4), according to send control signal (8), ARP sends control signal (17) and packet loss weight Hair control signal (15) sends corresponding Ethernet data bag automatically, and generation sends feedback signal (10)；Flow control module (4) includes image storage control module (4.1) and stream detection module (4.2), according to storage control letter Number (14), flow control signals (19), GVSP data are read by GVSP data read bus (18), view data is write into image Store in RAM, and generate storage feedback signal (13), while detect packet drop, control packet loss retransmits control signal (15)；Receive and control module (5) includes the 3rd two-port RAM (5.1), the 4th two-port RAM (5.2), the 5th two-port RAM (5.3), protocol resolution module (5.4), asynchronous FIFO (5.5) and GMII receiving modules (5.6), Ethernet data bag is received, It is parsed according to control signal (11) is received, generation receives feedback signal (12) and flow control signals (19), and respectively The data of parsing are sent by receiving data read bus (16) and GVSP data read bus (18).
- 2. the ethernet controller IP kernel according to claim 1 based on GigE Vision agreements, it is characterised in that deposit Device unit (1.1) is used to deposit control information, status information, native network address information and camera network address information；Mould Block control unit (1.2) is according to register cell（1.1）The information of storage and the feedback information of reception, generate PHY access controls Signal (6), send control signal (8), receive control signal (11) and storage control signal (14)；Bus control unit (1.3) To being parsed from Avalon Memory-Mapped from the address of interface and control signal, realize CPU to different in IP kernel Address space access, including register cell (1.1), the first two-port RAM (3.1), the 3rd two-port RAM (5.1) and 4th two-port RAM (5.2).
- 3. the ethernet controller IP kernel according to claim 1 based on GigE Vision agreements, it is characterised in that first Two-port RAM (3.1) will send data where system by sending data write bus (9) reception transmission data and caching Clock zone is transformed into clock zone where GMII sending modules (3.4)；Agreement package module (3.2) includes IP agreement package module (3.2.1), udp protocol package module (3.2.2), GVCP agreement package modules (3.2.3) and ARP protocol package module (3.2.4), according to control signal (8) is sent, automatic is to send data packet procotol, will wrap first data and is stored in the second both-end Mouth RAM (3.3)；GMII sending modules (3.4) include CRC-32 generation modules (3.4.1), by the first two-port RAM (3.1) and The data of second two-port RAM (3.3) are combined into ethernet frame and sent；CRC-32 generation modules (3.4.1) automatically generate 32 CRC check codes.
- 4. the ethernet controller IP kernel according to claim 1 based on GigE Vision agreements, it is characterised in that stream inspection Survey module (4.2) and read the 5th two-port RAM (5.3), view data bag ID number and view data, inspection are obtained according to GVSP agreements Packet drop, the automatic ID number for calculating lost data packets are surveyed, generation packet loss retransmits control signal (15)；Image storage control module (4.1) according to view data bag ID number and storage control signal (14), Avalon Memory-Mapped main interfaces are controlled, from Dynamic calculating memory addresses, view data storage is stored in RAM to image.
- 5. the ethernet controller IP kernel according to claim 1 based on GigE Vision agreements, it is characterised in that GMII Receiving module (5.6) embeds CRC-32 inspection modules (5.6.1), receiving network data bag, is written into asynchronous FIFO (5.5) In, and it is verified；The Ethernet data that asynchronous FIFO (5.5) caching receives, by data where GMII receives clock Clock zone is transformed into clock zone where protocol resolution module；Protocol resolution module (5.4) includes ARP protocol parsing module (5.4.1), IP agreement parsing module (5.4.5), udp protocol parsing module (5.4.4), GVCP protocol resolution modules (5.4.2) And GVSP protocol resolution modules (5.4.3), parsed to receiving data, and the data of parsing are stored in different pairs respectively In port ram；The GVCP data that 3rd two-port RAM (5.1) caching receives；5th two-port RAM (5.3) caching receives GVSP data；Other data that 4th two-port RAM (5.2) caching receives.
- 6. the ethernet controller IP kernel according to claim 1 based on GigE Vision agreements, it is characterized in that, it is described Transmission control module (3) there is ARP protocol automatic answer function, can receive and parse through host computer transmission ARP request number According to bag, and corresponding arp reply packet is sent automatically and carries out response, and the MAC Address of host computer and IP address are remembered Record.
- 7. the ethernet controller IP kernel according to claim 1 based on GigE Vision agreements, it is characterized in that, it is described Transmission control module (3) there is GVSP data packet retransmission request functions, GVSP packet packet drops can be detected in real time, and Automatic to send data packet retransmission request when finding packet loss, request camera retransmits corresponding GVSP packets.
- 8. the ethernet controller IP kernel according to claim 1 based on GigE Vision agreements, it is characterized in that, it is described MAC control modules (1), which have, receives interrupt requests function, and module control unit (1.2) is according to reception feedback signal (12), storage Feedback signal (13) produces interrupt signal, and CPU judges interrupt type by reading reception state register.
- 9. the ethernet controller IP kernel according to claim 1 based on GigE Vision agreements, it is characterized in that, it is described Register cell (1.1) include MAC control registers, mac state register, interrupt control register, interrupt status register, PHY control registers, PHY read data registers, PHY write data registers, send control register, receive control register, Flow control register, the machine MAC Address register, local IP address register, GVCP port numbers register, GVSP port numbers are posted Storage, camera MAC Address register and camera IP address register.
- 10. a kind of image data transfer method of the ethernet controller IP kernel based on GigE Vision agreements, its feature exist In, the IP kernel by MAC control modules (1), PHY management interfaces module (2), send control module (3), flow control module (4), Receive and control module (5) form, the MAC control modules (1) include register cell (1.1), module control unit (1.2) with And bus control unit (1.3)；Send control module (3) include the first two-port RAM (3.1), agreement package module (3.2), Second two-port RAM (3.3) and GMII sending modules (3.4)；Agreement package module (3.2) includes IP agreement package module (3.2.1), udp protocol package module (3.2.2), GVCP agreement package modules (3.2.3) and ARP protocol package module (3.2.4)；GMII sending modules (3.4) include CRC-32 generation modules (3.4.1)；Flow control module (4) stores comprising image Control module (4.1) and stream detection module (4.2)；Receive and control module (5) include the 3rd two-port RAM (5.1), the 4th pair Port ram (5.2), the 5th two-port RAM (5.3), protocol resolution module (5.4), asynchronous FIFO (5.5) and GMII receive mould Block (5.6)；Protocol resolution module (5.4) includes ARP protocol parsing module (5.4.1), IP agreement parsing module (5.4.5), UDP Protocol resolution module (5.4.4), GVCP protocol resolution modules (5.4.2) and GVSP protocol resolution modules (5.4.3)；GMII connects Receive module (5.6) and include CRC-32 inspection modules (5.6.1)；Entirely the Ethernet data transmission flow of IP kernel is：[1] bus control unit (1.3) will send data and write in the first two-port RAM (3.1), will control according to bus address In system order write-in register cell (1.1)；[2] the real-time detected register unit (1.1) of module control unit (1.2), after detecting transmission order, corresponding send out is generated Send control signal (8)；[3] agreement package module (3.2), which is read, sends control signal (8), generates corresponding protocol package head, and will wrap first data and deposit Enter in the second two-port RAM (3.3)；[4] GMII sending modules (3.4) read the data in the first two-port RAM (3.1) and the second two-port RAM (3.3), shape It is transmitted into ethernet frame；[5] at the same time, send control module (3) and produce transmission feedback signal (10)；[6] detection sends feedback signal (10) to module control unit (1.2) in real time, and feedback information is write into register cell (1.1)；Entirely the ethernet data acceptance flow of IP kernel is：(1) GMII receiving modules (5.6) real-time reception broadcast data packet or send to the packet of local mac address, and by number According to write-in asynchronous FIFO (5.5)；(2) protocol resolution module (5.4) reads the data in asynchronous FIFO (5.5), and the agreement of packet is parsed；(3) if packet is ARP request packet, ARP protocol parsing module (5.4.1) produces ARP according to request data Request signal, request send control module (3) and send arp reply packet；(4) if packet is IP packets, IP agreement parsing module (5.4.5) further solves to the agreement of packet Analysis, judges whether the packet is UDP message bag；(5) if packet is UDP message bag, udp protocol parsing module (5.4.4) judges destination slogan, judges the data Whether bag is GVCP packets or GVSP packets；(6) if packet is GVCP packets, GVCP protocol resolution modules (5.4.2) parsing packet, GVCP data are write Enter the 3rd two-port RAM (5.1), and produce corresponding reception feedback signal (12)；(7) if packet is GVSP packets, GVSP protocol resolution modules (5.4.3) parsing packet, GVSP data are write Enter the 5th two-port RAM (5.3), and produce flow control signals (19)；(8) other packets are write the 4th two-port RAM (5.2) by protocol resolution module (5.4), and produce corresponding receive Feedback signal (12)；(9) after flow control module (4) receives flow control signals (19), control-flow detection module (4.2) reads the 5th dual-port RAM(5.3)；(10) BlockID, PacketID and image that detection module (4.2) obtains GVSP packets in the data of reading are flowed Data, and packet drop is judged according to Block ID and Packet ID, if it find that packet loss, then produce packet loss and retransmit Control signal (15)；(11) image storage control module (4.1) obtains image storage first address from storage control signal (14), according to figure As the Packet ID of data and the length gauge of view data calculate the storage address of view data in the packet, and control View data write-in image is stored RAM by Avalon Memory-Mapped main interfaces；When the write-in complete view data of one width Afterwards, image storage control module (4.1) then produces storage feedback signal (13).
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