CN106612141B - A kind of fiber channel protocol common simulation test card and its data interactive method - Google Patents

Abstract

The invention discloses a kind of fiber channel protocol common simulation test card and its data interactive method, the fiber channel protocol common simulation test card includes: on-site programmable gate array FPGA unit, for realizing control logic function according to preset application demand；Optical module interface unit SFP is used for receiving-transmitting chain optical signal, and converts serial digital signal for FPGA unit processing for the optical signal received, while converting optical signal for the serial digital signal from FPGA unit and being sent to optical fiber link；Edge connector, the high-speed data between host computer being inserted into for realizing test card with test card exchange；Further include: synchronous DRAM SDRAM, configuration circuit, flash cell, clock unit, joint test working group jtag interface.It is capable of providing triggering abundant and filtering function, user is facilitated to emulate and test fiber channel interface, suitable for constructing the emulation testing application of FC Unified Network.

Description

A kind of fiber channel protocol common simulation test card and its data interactive method

Technical field

The present invention relates to high-speed serial bus communication and the field of test technology, espespecially a kind of fiber channel protocol common simulations Test card and its data interactive method.

Background technique

The formulation of FC (Fibre Channel fiber channel protocol) starts from 1988, by American National Standard Committee ANSI X3T11 group is responsible for.Formd a huge protocol suite at present, and also be continuously updated with it is perfect.In recent years Come, China also starts to study FC agreement correlation high speed interconnection technique energetically, and has continuously issued " GJB6410-2008 optical-fibre channel Physics and signaling interface FC-PH ", a series of FC Protocol Standards such as " GJB6411-2008 optical-fibre channel aviation electronics environment FC-AE " Standard, and have been widely used in various types of aerospace vehicle internal electron communications network systems.

FC protocol network be propose one of all round computer channel and data network concept be different from traditional channel and The interconnection scheme of network structure.It is a kind of with high real-time, reliability, bandwidth, the open communication technology of cost performance, uses Channel counts control signal transmission, handle medium access collision using exchanging or arbitrating ring topology, control net using credit policy Network flow.Its main feature is as follows:

1) full-duplex high-speed serial bus interface is used；

2) commonly using rate is 1.0625/2.125/4.25Gbps, and can be with the upgrading of physical interface and transmission medium, energy Reach the high bandwidth of 8/16Gbps；

3) transmission medium using wavelength 850nm multimode fibre or 1310nm single mode optical fiber, non-relay theoretical transmission away from From 500m and 15km is respectively reached, has superelevation anti-electromagnetic interference capability；

4) bit error rate is better than 10-12, and line transmission delay is better than 5us/km；

5) the effective passband ratio is high, is encoded using 8B/10B, and the load of frame data packet is maximum up to 2112Byte, and theory is effectively Bandwidth is better than the 75% of port speed；

6) it supports point-to-point, arbitrates ring, the multiple network topological structures such as switching network, networking flexibility；

7) support that the whole network clock is synchronous, clock synchronization accuracy is better than 0.1us；

8) upper-layer protocol type is abundant, and definition is complete.Distributed networking protocol is represented as FC-AE-ASM, and (anonymity signature disappears Cease transport protocol), centralized control type network protocol is represented as FC-AE-1553 (MIL-STD-1553 high level FC shadowing agreement).

It currently, the various applications of country's FC fiber channel protocol have been gradually spread out, and is in ardent ascendant trend.Especially army With in terms of field, aerospace system all starts to have for next-generation novel spacecraft consideration more high bandwidth, higher reliability, more Good anti-spoke is made an uproar the communication core network that performance, more upper-layer protocols use parallel.Currently, with FC-AE-ASM, FC-AE-1553, FC- AV, ARINC818 are the FC agreement or class FC protocol equipment of representative, grinding in each aerospace and related fields Study carefully institute and suppliers appearance is very frequent.

FC protocol bus communication products increase, and certainly will bring a large amount of protocol conformance verifying, intelligence communication simulation, lead to Believe that Performance Evaluation, real time data inspecting, communication process record emulation testing demand relevant to many FC protocol bus such as playback.

Summary of the invention

It is the general introduction to the theme being described in detail herein below.This general introduction is not the protection model in order to limit claim It encloses.

The embodiment of the invention provides a kind of fiber channel protocol common simulation test card and its data interactive methods, can Meet emulation testing demand relevant to FC protocol bus.

To achieve the goals above, the embodiment of the invention provides a kind of fiber channel protocol common simulation test card, with Emulation testing function is realized in host computer cooperation, comprising:

On-site programmable gate array FPGA unit, for realizing control logic function according to preset application demand；

Optical module interface unit SFP is used for receiving-transmitting chain optical signal, and converts serial digital for the optical signal received Signal converts optical signal for the serial digital signal from FPGA unit and is sent to optical fiber chain for FPGA unit processing Road；

Edge connector, the bus interface PCI-E slot for the host computer backboard that one end connecting test card is inserted into, separately One end is connect with FPGA unit, and the high-speed data between the host computer being inserted into for realizing test card and test card is handed over It changes；

Synchronous DRAM SDRAM, external memory chip on fixed plate, for micro process inside FPGA unit The instruction of device PowerPC and data store；

Configuration circuit powers on load configuration for FPGA unit, is non-volatile flash memory chip；

Flash cell, the load that powers on for PowerPC in FPGA unit configure, and are non-volatile flash memory chip；

Clock unit generates the clock source used for each circuit module for providing high-precision active clock；

Joint test working group jtag interface, for being used for FPGA download configuration and for PowerPC debugging.

Optionally, the joint test working group jtag interface shares 3 sets, wherein it is a set of dedicated for FPGA download configuration, Other two sets use for PowerPC debugging.

Optionally, the active clock of high-precision that the clock unit provides is 25MHz.

Optionally, the fiber channel protocol common simulation test card further include with lower module it is one or two kinds of more than Combination:

DIMM formula connection slot of dual inline memory module, the large capacity external data for FPGA unit are deposited Storage；

Front-panel led, for providing binary channels optical port working condition mark；

Extended interface unit is used for customized multi-purpose interface, including international time format code IRIG-B signal, outside Triggering input, trigger output signal.

Optionally, the FPGA unit includes one of following submodule or two or more any combination:

First coding module GTX_0 and the second coding module GTX_1, for receiving and dispatching optical signal, and realize optical signal with Mutual conversion between serial data signal；

Routing module, provide variable outbound data stream topological structure for two channels FPGA, it can be achieved that two channels simultaneously The data of the types such as row, intersection, interior winding route；

First main logic module Port_0 or the second main logic module Port_1, for being realized according to preset application demand Control logic function,

PCI-E IP kernel module directly uses IP kernel for the interface module that FGPA unit is connect with host computer PC I-E bus Exampleization；

Channel data buffer and arbitration logic, for dispatching the first main logic module Port_0 and the second main logic mould Two logic modules of block Port_1 solve the conflict of data transmission between multiport to the data flow between PCI-E bus.

Optionally, the FPGA unit further include:

Expansion module, for keeping for extended function module and interface.

Optionally, the first main logic module Port_0 or the second main logic module Port_1 includes following submodule Any combination: buffer area is received, buffer area is sent, transmit queue management module, international time format code IRIG module, posts Storage group, direct memory access dma controller, monitoring data preprocessing module, buffering are to buffering BB credit buffer area, end-to-end EE credit buffer area, link control logic module, frame establish module, direct fault location module, transmit queue management module, send and delay Rush area, microprocessor PPC interrupt control unit, synchronous DRAM sdram controller, Double Data Rate synchronous dynamic random Memory DDR2 controller, channel data buffer area, local self-defined bus Local Bus, pipeline burst type cache PLB；Its In,

The reception buffer area is respectively supplied to monitoring data for receiving data flow and caching from routing module Preprocessing module, BB credit buffer area, direct fault location module, for monitoring data access, link control access, direct fault location access It uses；

The transmission buffer area, for caching the data flow from transmit queue management module, being aligned, arrange and being sent to Routing module；

The IRIG module is also used to realize transmitting-receiving and processing outer synchronous signal for generating IRIG markers；

The register group has the set of registers with base register PCI-E BAR space reflection address；

The dma controller, the data flow control on local self-defined bus Local Bus between each submodule；

The monitoring data preprocessing module, for receiving and buffering link data, at categorized, compression and alignment Reason after adding markers and additional information, is sent in DDR2 or is sent directly to channel data buffer area；

BB credit buffer area, for receiving fiber channel protocol FC message and link response original with frame structure Language carries out buffer area and judges buffer area flow control, and prompts frame to establish module and generate link response primitive appropriate；

EE credit buffer area carries out end-to-end buffer area flow control judgement for receiving the FC message with frame structure, And it prompts frame to establish module and generates FC response frame appropriate；

The link control logic module, the primitive sequence for the control of protocol layer link for being received according to chain road Column and frame message, execute corresponding link reset or control protocol, and prompt frame to establish module and generate FC response primitive appropriate Sequence or response frame；

The frame establishes module, for being sent according to BB credit buffer area, EE credit buffer area, link control logic module Framing or group primitives, and FC message appropriate is generated according to the content of corresponding states register, then by the suitable of agreement Sequence is sent to transmit queue management module；

The direct fault location module, for according to brief introduction trigger Trigger register matching instruction and direct fault location The instruction of strategy registers carries out real time fail injection behavior to the link original message received, then by modified report Text is sent to transmit queue management module；

The transmit queue management module, for receiving the gentle transmission message brought from multiple modules, and according to agreement Rule compositor and be sent to send buffer area be also responsible for the management of message length matching mechanisms under direct fault location mode；

The transmission buffer area receives and buffers the message from transmit queue management module, is then forwarded to routing mould Block；

The microprocessor PPC interrupt control unit, for management role in the interrupt signal of PowerPC；

The sdram controller, for providing the interface module of SDRAM chip outside access FPGA；

The DDR2 controller, for providing the interface module of DDR2SDRAM chip outside access FPGA；

The channel data buffer area, the main logic module for managing and buffering single channel connect PCI-E bus The uplink and downlink data flow of mouth mold block；

The Local Bus, for connect the data of multiple submodule, address and control signal customized inside it is total Line；

The PLB, for connecting the internal bus of PowerPC submodule associated therewith.

The embodiment of the invention also provides a kind of fiber channel protocol common simulation test card data interactive method, for into The interaction of row upstream data, which comprises

1) the rear host computer driving application space memory Mem is powered on, and establishes corresponding address table, including upper row address Table and downlink address table；

2) host computer driving is respectively written into uplink address table and downlink to FPGA unit in a manner of register mappings access BAR The physical address and length of address table；

3) host computer driving notifies FPGA unit address table to come into force in a manner of BAR；

4) FPGA unit reads the address table of 512B with direct memory access dma mode；

5) when the OwnerBit for determining the address Mem is 1 data are written to the Mem address entries, when sentencing in FPGA unit When the OwnerBit to break to the address Mem is 0, FPGA unit is sent out to host computer is interrupted, and indicates that Mem resource can not be used, until upper Machine issues Mem resource available alert；

6) FPGA updates address table with dma mode, the OwnerBit letter of the address table including modifying the used address Mem Breath；

7) FPGA sends out to host computer and interrupts, and indicates that a upstream data access is completed；

8) host computer driving to be to interrupt as signal, to OwnerBit in updated address table be 0 Mem address space into Row read operation reads data and updates the OwnerBit of appropriate address, sets 1 with Free up Memory；

9) FPGA address pointer is directed toward next Mem address entries after last time DMA, when continuing have upload data Demand, and 64 address entries of last application are not finished, then repeatedly step 5~8；When 64 address entries are finished and still It has data to transmit, FPGA executes step 4, then executes step 5~8.

The embodiment of the invention also provides a kind of fiber channel protocol common simulation test card data interactive method, for into The interaction of row downlink data, which comprises

1) power on the rear host computer driving application space Mem, and establish corresponding address table, including uplink address table with Downlink address table；

2) host computer driving is respectively written into uplink address table and downlink address table physically to FPGA unit in a manner of BAR Location and length；

3) host computer writes data to the corresponding space Mem by address table sequence；

4) it is 0 that host computer, which sets the corresponding OwnerBit of address table,；

5) in a manner of BAR, notice FPGA unit has downlink data for host computer driving；

6) FPGA unit reads the address table of 512B with dma mode；

7) FPGA unit is fixed length DMA according to the address that OwnerBit in address table is 0, reads the number in the corresponding space Mem According to；

8) FPGA unit updates address table with dma mode, and the OwnerBit for setting last time read Mem space address is 1；

9) host computer determine next address entrance OwnerBit to be used be 0 when, temporarily cease and write data and wait To, the OwnerBit situations of address entries is inquired again after being spaced setting time, until OwnerBit is 1, then repeatedly step 3 ~8 or time-out report an error.

Compared with prior art, the embodiment of the invention provides the high-performance based on the interface of PCIe × 8, dual-port FC optical fiber Channel protocol common simulation test card can be for logical based on optical fiber as the FC interface testing module of a multi-functional high intelligence The node and exchange communication test of road agreement and inspection provide data generation, emulation and monitoring and analytic function.It is specific next Say, FC fiber channel protocol common simulation detection clamp provided in an embodiment of the present invention for port configure, data generate and emulation, The multiple functions such as data monitoring, the analysis of FC-4 layer protocol, video interface extension.It is capable of providing triggering abundant and filtering function, Facilitate user to emulate and test fiber channel interface, can be assisted for user's building based on FC based on the common simulation test card General exploitation, the experiment, test, analysis, monitor supervision platform of view, suitable for constructing the emulation testing application of FC Unified Network, Ke Yiman A variety of application demands of sufficient user.

After reading and understanding attached drawing and detailed description, it can be appreciated that other aspects.

Detailed description of the invention

Attached drawing is used to provide to further understand technical scheme, and constitutes part of specification, with this The embodiment of application is used to explain the technical solution of the application together, does not constitute the limitation to technical scheme.Attached In figure:

Fig. 1 is the structural schematic diagram of fiber channel protocol common simulation test card provided in an embodiment of the present invention.

Fig. 2 is FPGA unit structural schematic diagram provided in an embodiment of the present invention.

Fig. 3 is the first main logic module Port_0 included by FPGA unit provided in an embodiment of the present invention or second main The submodule schematic diagram for including in logic module Port_1.

Fig. 4 is upstream data interaction diagrams provided in an embodiment of the present invention.

Fig. 5 is downlink data interaction diagrams provided in an embodiment of the present invention.

Fig. 6 is FPGA internal data flow diagram provided in an embodiment of the present invention.

Fig. 7 is the segmentation of ULP provided in an embodiment of the present invention (Upper Level Protocol, upper-layer protocol) data block With recombination schematic diagram.

The embodiments will be further described with reference to the accompanying drawings for realization, functional characteristics and the advantage of the application purpose.

Specific embodiment

It should be appreciated that specific embodiment described herein is only used to explain the application, it is not used to limit the application.

The data acquisition module of each embodiment of the present invention is realized in description with reference to the drawings.In subsequent description, Be conducive to the explanation of the application using the suffix for indicating such as " module ", " component " or " unit " of element, There is no specific meanings for itself.Therefore, " module " can be used mixedly with " component ".

Embodiment 1

Fig. 1 is fiber channel protocol common simulation test card structural schematic diagram provided in an embodiment of the present invention, such as Fig. 1 institute Show, fiber channel protocol common simulation test card provided in this embodiment, comprising:

FPGA (Field-Programmable Gate Array, i.e. field programmable gate array) unit, for according to Preset application demand realizes control logic function；

Optical module interface unit SFP is used for receiving-transmitting chain optical signal, and converts serial digital for the optical signal received Signal converts optical signal for the serial digital signal from FPGA unit and is sent to optical fiber chain for FPGA unit processing Road；

Edge connector, PCI-E (bus interface) slot for the host computer backboard that one end connecting test card is inserted into, The other end and the coding module GTX interface of FPGA unit connect, and calculate for realizing the host that test card and test card are inserted into High-speed data exchange between machine.

The edge connector is 8 channel PCI-E printed board edge connecting interfaces.

SDRAM (Synchronous Dynamic Random Access Memory, synchronous DRAM), Gu External memory chip on fixed plate, instruction and data for bit microprocessor inside FPGA store；Two channels.

Configuration circuit powers on load configuration for FPGA, is non-volatile flash memory chip；

Flash cell, the load that powers on for PowerPC in FPGA configure, and are non-volatile flash memory chip,

Clock unit: for providing high-precision active clock, and the PLL that arranges in pairs or groups (Phase Locked Loop, phase-locked loop Or phaselocked loop) circuit, generate the clock source used for each circuit module.The active clock of high-precision is 25MHz.

JTAG (Joint Test Action Group, joint test working group) interface: 3 sets of jtag interfaces.It is wherein a set of It is dedicated for FPGA download configuration, in addition used for PowerPC debugging for two sets.

In the present embodiment, the fine channel protocol common simulation test card further include:

DIMM (Dual-Inline-Memory-Modules, i.e. dual inline memory module) formula connection slot, Large capacity external data storage for FPGA；

Can spread memory bar capacity, two channels.

In the present embodiment, the fine channel protocol common simulation test card further include:

Front-panel led: two sets of color LED indicator lights provide intuitive binary channels optical port working condition mark.

In the present embodiment, the fine channel protocol common simulation test card further include:

Extended interface unit, is used for customized multi-purpose interface, including IRIG-B (international time format code) signal, outer Portion's triggering input, trigger output signal, internally connect with FPGA.

Embodiment 2

It is FPGA unit structural schematic diagram provided in an embodiment of the present invention referring to shown in Fig. 2.It is provided in an embodiment of the present invention FC common simulation test card is using double optical port channel structure designs.It therefore, include two sets of main logic modules inside FPGA unit, Two channels are corresponded respectively to, as shown in Fig. 2, two sets of main logic modules are respectively the first main logic module Port_0 and second main Logic module Port_1, this two sets of main logic inside modules logics are identical.Other than two above main logic module, FPGA It further include routing module and PCI-E IP kernel module in unit, for realizing logical between board hardware and host computer Letter；It further include channel data buffer corresponding with PCI-E core and arbitration logic；It further include serve as FC channel coding layer two A GTX module (the first coding module GTX_0, the second coding module GTX_1), for realizing board hardware to optical fiber transmission medium Electro-optical signal coding and conversion, further include expansion module.

Referring to shown in Fig. 2, the function of modules described in detail below.

Firstly the need of explanation, IP kernel example refers to will be predefined, is able to achieve the FPGA code of specific function, It is added in the design scheme of user with specific process, and realizes the process of the specific function.

The first coding module GTX_0 and the second coding module GTX_1, the first coding module GTX_0 module and the One optical fiber interface SFP_0 and routing module direct interface, the second coding module GTX_1 module and the second optical fiber interface SFP_1 and Routing module direct interface is the IP kernel module of direct example inside FPGA, for optical mode described in external connection embodiment 1 Block SFP interface unit receives and dispatches optical signal, and realizes the mutual conversion between optical signal and serial data signal.In addition FC is realized The FC-1 in channel encodes layer function, and the transmission-receiving function of the parallel data of 32 (or 40) is provided for main logic module；

Routing module provides variable outbound data stream topological structure for two channels FPGA.It is configured according to upper layer software (applications), The data routing of the types such as two channel parallels, intersection, interior winding can be achieved；

First main logic module Port_0 (or second main logic module Port_1): it realizes and controls according to preset application demand Logic function processed, including the submodules such as part FC-2 layer protocol, direct fault location, link data buffering and pretreatment.Meanwhile it also wrapping Containing the interface sub-module to the FPGA external equipment such as SDRAM, DDR2, Flash, JTAG, expansion interface；

PCI-E IP kernel module directly uses IP kernel example for the interface module that FGPA is connect with host computer PC I-E bus Change, makes the test card of the embodiment of the present invention that can be generalized machine and be identified as a PCI-E device；

Channel data buffer and arbitration logic, for dispatching the first main logic module Port_0 and the second main logic mould Two logic modules of block Port_1 solve the collision problem of data transmission between multiport to the data flow between PCI-E bus；

Expansion module, the extended function module and interface of the common simulation test card for keeping for the embodiment of the present invention.

Embodiment 3

As described above, the first main logic module Port_0 and the second main logic module Port_1 are the core that FPGA function is realized The heart, the inside modules contain a large amount of submodules to realize different logic or interface.Below with reference to shown in Fig. 3, in detail The submodule for including in the first main logic module Port_0 once or the second main logic module Port_1 is described.

Shown in exhibition Fig. 3, the first main logic module Port_0 or the second main logic module Port_1 include following Submodule: buffer area is received, buffer area is sent, transmit queue management module, IRIG (international time format code) module, posts Storage group, DMA (direct memory access) controller, monitoring data preprocessing module, BB (buffering is to buffering) credit buffer area, EE (end-to-end) credit buffer area, link control logic module, frame establish module, direct fault location module, transmit queue management module, Send buffer area, PPC (PowerPC) interrupt control unit, SDRAM (synchronous DRAM) controller, DDR2 (double-speed Rate synchronous DRAM) controller, channel data buffer area, Local Bus (local self-defined bus), PLB pipeline Burst type caching,

It receives buffer area and is then respectively supplied to monitoring data for receiving data flow and caching from routing module Preprocessing module, BB credit buffer area, direct fault location module, for monitoring data access, link control access, direct fault location access It uses；

Buffer area is sent to be aligned, arrange and be sent to routing for caching the data flow from transmit queue management module Module；

IRIG module: for generating IRIG markers, it is also used to realize transmitting-receiving and processing outer synchronous signal.When needed, The real-time stamp of 64bit is provided for monitoring data preprocessing module.In addition, being also used to realize transmitting-receiving and processing external sync letter Number, which is communicated by the private port and external relevant device of expansion interface；

Register group has the set of registers with PCI-E BAR (base register) space reflection address.Including The configuration register and status register of each submodule, the brief introduction trigger Trigger register group for condition triggering, group Close Trigger sequential register group, direct fault location strategy registers group etc..By host computer to each register or register group into Row configuration；

DMA (direct memory access) controller, the number on local self-defined bus Local Bus between each submodule According to flow control.Channel setting with burst access mode and with priority；

Monitoring data preprocessing module adds for receiving and buffering link data, categorized, compression and registration process After added-time mark and additional information, channel data buffer area is sent in DDR2 or is sent directly to.The data are used for host computer Real time monitoring and communication use；

BB credit buffer area carries out buffer area to slow for receiving FC message and link response primitive with frame structure The judgement of area's flow control is rushed, and prompts frame to establish module and generates link response primitive appropriate；

EE credit buffer area carries out end-to-end buffer area flow control judgement, and mention for receiving the FC message with frame structure Show that frame establishes module and generates FC response frame appropriate；

Link control logic module, for according to chain road receive for protocol layer link control primitive sequence and Frame message executes corresponding link reset or control protocol, and prompts frame to establish module and generate FC response primitive sequence appropriate Or response frame；

Frame establishes module, according to BB credit buffer area, EE credit buffer area, link control logic module send framing or Group primitives, and FC message appropriate is generated according to the content of corresponding states register, then it is sent to by the sequence of agreement Transmit queue management module；

Direct fault location module is deposited according to the matching instruction of brief introduction trigger Trigger register and direct fault location strategy The instruction of device carries out real time fail injection behavior to the link original message received, is then sent to modified message Transmit queue management module；

Transmit queue management module, for receiving the gentle transmission message brought from multiple modules, and according to treaty rule It sorts and is sent to transmission buffer area and be also responsible for the management of message length matching mechanisms under direct fault location mode；

Buffer area is sent, receives and buffers the message from transmit queue management module, be then forwarded to routing module；

The stone of PowerPC 440 inside PowerPC, the FPGA of example；

PPC (PowerPC) interrupt control unit, for management role in the interrupt signal of PowerPC；

SDRAM (synchronous DRAM) controller, for providing connecing for access FPGA unit outside SDRAM chip Mouth mold block；

DDR2 controller, for providing the interface module of DDR2SDRAM chip outside access FPGA；

Channel data buffer area, for managing and buffering the main logic module in single channel for PCI-E bus interface mould The uplink and downlink data flow of block；

Local Bus, the main logic inside modules in single channel, for connect the data of multiple submodule, address and Control the customized internal bus of signal；

PLB (pipeline burst type caching), the main logic inside modules in single channel are associated therewith for connecting PowerPC The internal bus of submodule.

Each submodule function included by FPGA unit is described in detail below.

1, the first coding module GTX_0, the second coding module GTX_1 module

First coding module GTX_0 and the second coding module GTX_1 module are two identical functional modules, mono- by FPGA The GTX IP kernel example of member obtains.Pass through the first optical fiber interface on the specialized high-speed I/O connection board of FPGA unit respectively SFP_0 and the second optical fiber interface SFP_1.Its major function is:

1) realize that the data between FC of embodiment of the present invention common simulation test card board internal data and fiber optic network pass It is defeated；

2) it realizes and the serial data stream (1bit) of the optical fiber interface SFP input/output on board to GTX inside modules The mutual conversion of parallel data stream (10bit)；

3) it realizes that the 8B/10B coding/decoding to FPGA unit internal data is converted, and is correlation module inside FPGA unit 32bit the or 40bit data and relevant control, status signal of alignment are provided, or are received from correlation module inside FPGA 32bit or 40bit data and relevant control, status signal；

4) receiving path logic is according to the serial data stream received, using recovery tranmitting data register, and with the docking of this clock It receives data and carries out reliable samples；

5) dropout for meeting FC-1 layers of specification, bit synchronization, word synchronous regime judgment mechanism are provided, and are FPGA unit Internal correlation module provides above-mentioned status signal.

6) optical fiber interface SFP line status needs can be inquired.

First coding module GTX_0 module is compiled with the first optical fiber interface SFP_0 and routing module direct interface, second respectively Code module GTX_1 module respectively with the second optical fiber interface SFP_1 and routing module direct interface.

In one embodiment, the first coding module GTX_0 module and the second coding module GTX_1 module section function It is enabled to need host computer with configuration to manage, directly its special register is configured by special register bus.In order to It realizes the function, needs carry register to decode mould at the first coding module GTX_0 and the second coding module GTX_1 module interface Block.

2, routing module

Routing module is custom logic module, and the purpose is to provide the first coding module GTX_0 of one kind, the second coding mould Block GTX_1 signal is to the overall data between the first main logic module Port_0, the second main logic module Port_1 and controls letter Number flexible routing mechanism.It can be in the case where user change optical fiber line on two external SFP optical fiber interfaces, easily It is selected according to the function of emulation testing card to realize required port data flow direction.Its function mainly realizes following five kinds of routes Routing:

1) run-in index route routes: the first coding module GTX_0 sends signal group (interior) and the first main logic module Port_ 0, which receives signal group, is connected,

First coding module GTX_0 receives signal group (interior) and is connected with the first main logic module Port_0 transmission signal group,

Second coding module GTX_1 sends signal group (interior) and is connected with the second main logic module Port_1 reception signal group,

Second coding module GTX_1 receives signal group (interior) and is connected with the second main logic module Port_1 transmission signal group；

2) staggered form route routes the first coding module: the first coding module GTX_0 sends signal group (interior) and the first master Logic module Port_0 receives signal group and is connected,

First coding module GTX_0 receives signal group (interior) and is connected with the second main logic module Port_1 transmission signal group,

Second coding module GTX_1 sends signal group (interior) and is connected with the second main logic module Port_1 reception signal group,

Second coding module GTX_1 receives signal group (interior) and is connected with the first main logic module Port_0 transmission signal group；

3) parallel bypass type route routing: the first coding module GTX_0 sends signal group (interior) and the first main logic module Port_0 receives signal group and is connected,

First coding module GTX_0 receives signal group (interior) and is connected with the first coding module GTX_0 transmission signal group,

Second coding module GTX_1 sends signal group (interior) and is connected with the second main logic module Port_1 reception signal group,

Second coding module GTX_1 receives signal group (interior) and is connected with the second coding module GTX_1 transmission signal group；

4) duplexing bypass type route routing: the first coding module GTX_0 sends signal group (interior) and the first main logic module Port_0 receives signal group and is connected,

First coding module GTX_0 receives signal group (interior) and is connected with the first coding module GTX_0 transmission signal group,

First coding module GTX_0 receives signal group (interior) and is connected with the second main logic module Port_1 reception signal group；

5) winding formula route routes in: the first main logic module Port_0 sends signal group and the first main logic module Port_0 receives signal group and is connected,

Second main logic module Port_1 sends signal group and is connected with the second main logic module Port_1 reception signal group.

Routing module, which is generally acknowledged that, only needs multiple selector structure, does not need data buffering structure.

Routing module outward direction simultaneously with the first coding module GTX_0, the second coding module GTX_1 direct interface, to Interior direction and the first main logic module Port_0, the second main logic module Port_1 direct interface.

The route pattern selection of routing module needs host computer by special register bus to its specialized configuration register It is managed for configuration, while being also required to single user state register and being inquired for host computer.

3, monitoring data preprocessing module

Monitoring data preprocessing module belongs to the son of the first main logic module Port_0 or the second main logic module Port_1 One of module.Its timing signal for receiving the transmission signal group signal from routing module inward direction and IRIG-B module, The upstream data format that processing is integrated into agreement format is carried out with this two paths of signals, is then sent to dma logic module.It is main Function includes:

1) FC original link message is buffered, message is with 32bit or 40bit alignment (decoding or non-codec format)；

2) the continuous primitive of the same name or primitive sequence of frame gap are compressed；

3) frame boundaries are determined, and 32 crc checks are carried out to content frame；

4) original link message is integrated according to the format classification of frame or primitive packet；

It 5) is classification message packet addition label and markers by agreement format；

6) it is sent to the message after integration or after clock domain is converted dma logic module or is sent to corresponding DDR2.It is (straight The mode received and sent to dma logic module is more efficient, but will buffer size according to actual needs determine)

Monitoring data preprocessing module outward direction and routing module direct interface, inward direction and dma logic module (or DDR2 module for reading and writing) and IRIG-B module direct interface.With EE credit buffer module direct interface.

Monitoring data preprocessing module needs host computer to carry out by special register bus to its specialized configuration register Configuration management, while being also required to single user state register and being inquired for host computer.

4, condition trigger module

Condition trigger module belongs to one of the first main logic module Port_0 or the second main logic module Port_1 submodule. The purpose is to which the original link message matching message good with configured in advance to be compared, the triggering of agreement is if the same exported Signal.In addition to message matching mode, should also have time match, triggering times matching, the matched advanced additional function of combination condition Energy.Trigger signal can be used as message capturing Switching Condition, message capturing condition, direct fault location condition and use.In addition, should also can be with Trigger signal is exported to another channel or external board and is used, equally, also to support the triggering in another channel or external board Signal input.Its major function includes:

1) the message matching function on the basis of offset and mask.For primitive, offset is always zero.For frame, Offset is using SOF as initial address.Mask can position each of 32bit or 40bit；(offset is using broad sense frame as standard)

2) timer can be set as to individual trigger condition, or be based on the combination trigger condition of (1)；

3) it can be used as based on (1) with counter and combine trigger condition；

It 4) can be by the FC-1 layer provided by coding module GTX module, FC-2 control logic module, FC-2 fault error signal As trigger condition；

5) another channel condition can be triggered to input and the condition entry of external plates card as one of local trigger condition；

6) it is based on many condition composite sequence trigger mechanism of (1) (2) (3) (4) (5)；

7) based on (1) (2) (3) (4) (6) condition trigger signal export, the signal can be used for this channel, another channel with And external board.

Condition trigger module outward direction and routing module direct interface, inward direction and direct fault location module, FC-2 are controlled In addition logic module direct interface processed has the external trigger conditions of the condition trigger module and expansion interface that are directed toward another channel defeated Enter output signal.

Condition trigger module needs host computer to carry out configuration pipe to its specialized configuration register by special register bus Reason, while being also required to single user state register and being inquired for host computer.In addition, also having the match registers as trigger condition Group, for match registers sequence group of compound trigger condition etc..

5, IRIG-B module

IRIG-B module belongs to one of the submodule of the first main logic module Port_0 or the second main logic module Port_1. It is used the purpose is to generate precise time label and be supplied to monitoring data preprocessing module.The markers is generated by local timer, together When, which should support the markers synchronization signal from external board, or export markers synchronization signal to external board.It is main Function includes:

1) two groups of 32bit are provided and count markers, high 32bit counter should include D, H, M, S, and low 32bit counter should wrap Include m, u, n.Resolution ratio is not lower than 1ns；(64bit continuous counter)

2) markers be used for monitoring data preprocessing module, and type of data packet be primitive when, markers mark should be of the same name The first primitive position of continuous primitive；When type of data packet is frame, what markers marked should be the position SOF of the frame；

3) when markers is used for filtering module, markers should add markers to each message for meeting filter condition；

4) external markers synchronization signal is modified in the counter high 32bit counter by agreement coded format Hold.For low 32bit counter, until using reseting signal reset.In addition, synchronization signal needs to calculate line according to engagement arithmetic Delay between road simultaneously eliminates it；

5) module should have the function to the IRIG-B module of external board output (4) described synchronization signal.

IRIG-B module and monitoring data preprocessing module direct interface, have with the IRIG-B module in another channel and directly connect Mouthful, there is direct interface with external expansion interface.

IRIG-B module needs host computer that its specialized configuration register is managed for configuration by special register bus, Single user state register is also required to simultaneously to inquire for host computer.

6, BB credit buffer module

BB credit buffer module belong to the first main logic module Port_ or the second main logic module Port_1 submodule it One.The purpose is to be used for buffered links message, and to the FC transmission frame received, FC-2 protocol layer buffer area is carried out to buffer area Grade data flow control.Its major function includes:

1) original link message is received and buffered, and incoherent individual buffer area is configured according to the service class of support, together When buffer area number and size configured by host computer；

2) it checks the appointed position in FC transmission frame, assert that its validity in terms of BB credit (delimit by service type, frame Symbol etc.)；

If 3) a FC transmission frame is determined as valid frame in (2), which is stored in corresponding buffering area and is led to immediately Know that EE buffer zone module receives the frame, and notice FC-2 control logic module is ready for sending response frame or primitive appropriate；

If 4) a FC transmission frame is determined as invalid frame in (2), abandons the frame and only notify FC-2 control logic Module is ready for sending response frame appropriate；

5) for FC primitive, the module is without any processing.

BB credit buffer module outward direction is believed to routing module direct interface (data-signal is related), inward direction and EE (data-signal is related) is directly connected to buffer module, to FC-2 control logic module direct interface (marking signal is related).

BB credit buffer module needs host computer to configure by special register bus to its specialized configuration register Management, while being also required to single user state register and being inquired for host computer.

7, EE credit buffer module

EE credit buffer module belongs to the submodule of the first main logic module Port_0 or the second main logic module Port_1 One of.The purpose is to be used for buffered links message, and to the FC data frame received from BB credit buffer module, FC-2 association is carried out Discuss the end-to-end grade data flow control of layer.Its major function includes:

1) message of BB credit buffer module transmission is received and buffers, and reserved according to the concurrent sequence number of the maximum supported FC frame data buffer area, the buffer area number and size are configured by host computer；

2) it checks the appointed position in FC data frame, assert its validity (content validity, CRC in terms of EE credit Check etc.)；

If 3) a FC data frame is determined as valid frame in (2), which is stored in corresponding buffering area and organizes packet, with And notice FC-2 control logic module is ready for sending response frame appropriate；

If 4) a FC data frame is determined as invalid frame in (2), abandons the frame and notify FC-2 control logic mould Block determines the processing mode to all data frames in buffer area of the same name belonging to the frame by FC-2 control logic module, and then Generate response frame appropriate；

5) for FC primitive and FC link response frame, the module is without any processing.

EE credit buffer module outward direction and BB buffer module direct interface (data-signal is related), with FC-2 (link Control logic module) direct interface (marking signal is related).

EE credit buffer module needs host computer to configure by special register bus to its specialized configuration register Management, while being also required to single user state register and being inquired for host computer.

8, FC-2 (link control logic module)

FC-2 control logic module belongs to the submodule of the first main logic module Port_0 or the second main logic module Port_1 One of block.The purpose is to realize the most data flow control of FC-2 protocol layer, automatic-answering back device, false judgment and restore function, Optional additional function interface also is provided for upper layer (FC-3, FC-4 and FC-4 are with upper layer) agreement simultaneously.In addition, the module is also It is the sign generating source that frame establishes that a variety of response frames of module generate.Its major function includes:

1) according to the link reset class primitive sequence (from EE credit buffer module) received or according to the volume received The agreement mark of code module GTX module, generates link reset logic；

2) according to the arbitration ring class primitive or primitive sequence received, arbitration central link arbitrated logic is generated；

3) it can produce and log in and publish logic, judge port topology structure, and safeguard and log in result and parameter；

4) according to the response frame or primitive received, sender of communications BB or EE credit value is counted, and is made suitably with this Data flow control response or movement；

5) it to the base link service frame or extension link service frame received, is made just according to the parameter of internal register True response or movement (response action of each link sen frame may be incoherent independent logical)；

6) according to (1) (2) (3) (4) (5) the case where, instruction frame establish module and generate corresponding frame or primitive and primitive Sequence is simultaneously sent；

7) special register of the read-write protocol-dependent internal module of multiple FC, such as BB credit buffer module, EE letter Module etc. is established with buffer module, coding module GTX module, frame.

FC-2 control logic module and EE credit buffer module have direct interface, and signal is mostly primitive, primitive sequence, link Control frame, link sen frame etc. also include flag bit or register read-write interface；With BB credit buffer module, coding module GTX Module (passing through routing module interface) has direct interface, and signal is mostly flag bit or register read-write interface；Module is established with frame There is direct interface, including flag bit or register read-write interface, and sends content queue, it is considered that be a kind of FIFO (first in, first out) structure；Have direct interface with host computer or upper-layer protocol, it is considered that be by the read-write of special register come It realizes.

The special register quantity of FC-2 control logic module is relatively more, is chiefly used in the configuration and maintenance of all kinds of parameters, respectively The status register etc. that class is inquired for host computer.

9, frame establishes module

Frame establishes one of the submodule that module belongs to the first main logic module Port_0 or the second main logic module Port_1. Its purpose generates response frame or primitive and primitive sequence appropriate, and lead to first is that according to the instruction of FC-2 control logic module Cross the transmission of transmit queue module；The other is receiving the instruction from host computer, the message content in DDR2, and root are read It is required according to parameter configuration, the generation of control frame interstitial structure, crc field etc., and sent by transmit queue module.Its main function Can include:

1) according to the instruction of FC-2 control logic module, response frame, primitive or the primitive sequence of (2)~(6) type are generated；

2) primitive or primitive sequence for being used for link reset protocol integrated test system are generated；

3) primitive or primitive sequence for arbitrating central link arbitration are generated；

4) primitive or primitive sequence or link sen frame for FC-3 utility are generated；

5) response frame or primitive of link control frame are generated；

6) response frame of link sen frame is generated；

7) it requests and configures according to host computer, send corresponding link control frame or link sen frame；

8) interframe gap structure or crc field are added automatically for the downgoing communication message from host computer；

9) message is emulated for the downlink from host computer add interframe gap structure or crc field automatically；

10) transmit queue management module is sent by the message that (1)~(9) generate.

Frame establishes module and link control logic module FC-2 direct interface, is register read-write interface and transmission instruction Queue fifo interface；With DDR2 module for reading and writing direct interface, for reading the message content in DDR2；Mould is managed with transmit queue Block direct interface, for sending ready frame, primitive or primitive sequence；It is generally acknowledged that the direct interface with host computer passes through specially It is realized with the read-write of register.

Frame establishes module and needs host computer that its specialized configuration register is managed for configuration by special register bus, Single user state register is also required to simultaneously to inquire for host computer.

10, transmit queue management module

Transmit queue management module belongs to the submodule of the first main logic module Port_0 or the second main logic module Port_1 One of block.The purpose is to buffer, manage and send the transmission message from multiple modules；In addition priority sendaisle should be managed And period sendaisle.Its major function includes:

1) it receives and establishes the transmission message of module from frame and buffer；

2) it receives the transmission message from direct fault location module and buffers；

3) it prefetches the period message from DDR2 and buffers, it is considered that the message establishes module forwards via frame；

4) to from (1) (2) (3) message by default priority or mark priority be ranked up after send (recognize Will not occur simultaneously for the different message of some types)；

5) should have the deletion or the request for adding IDLE (idle signal) primitive that reply direct fault location message is likely to occur.

Transmit queue management module and frame establish module direct interface, and data type is that direct 32bit or 40bit is aligned FC Format message；With direct fault location module direct interface, data type is that direct 32bit or 40bit is aligned FC format message.

Transmit queue management module needs host computer to match by special register bus to its specialized configuration register Management is set, while being also required to single user state register and being inquired for host computer.

11, direct fault location module

Direct fault location module belong to the first main logic module Port_0 or the second main logic module Port_1 submodule it One.The purpose is to be modified, replaced according to the target and strategy arranged in advance to the original link message received, be inserted into, A plurality of types of direct fault location behaviors such as deletion.Its major function includes:

1) it is triggered according to the event of condition trigger module to determine direct fault location target；

2) direct fault location behavior is executed to corresponding direct fault location object according to the configuration of direct fault location strategy registers；

3) direct fault location strategy is similar with condition trigger policy, is all the positioning method on the basis of offset and mask；

4) modification type fault injection, refers to and modifies to the designated position data bit of object message, do not change object Length；

5) replacement type fault injection, refers to delete target message, and is inserted into newly at the queue position of object script Message.The length of original message queue is likely to increase or shortened after the completion, and transmit queue management module is needed to be intervened；

6) insertion type fault injection, refers to and adds new agreement message, object message itself in the tail portion of object message It is unaffected.The length that will increase original message queue after the completion needs transmit queue management module to be intervened；

7) type fault injection is deleted, refers to and directly deletes object message from message queue.Original can be shortened after the completion There is message queue size, transmit queue management module is needed to be intervened；

8) there is plan to execute number and the practical management for executing number and miss number for reply (4) (5) (6) (7) Function.

Direct fault location module and condition trigger module direct interface, for receiving Event trigger；It is straight with routing module Connection interface, for receiving original link message；With transmit queue management module direct interface, for send execute direct fault location after Message queue, and send message queue size's intervention request.

Transmit queue management module needs host computer to match by special register bus to its specialized configuration register It sets management and direct fault location strategy registers group is managed for configuration, while being also required to single user state register for host computer Inquiry.

12, DDR2 controller IP module

DDR2 controller IP module belongs to the submodule of the first main logic module Port_0 or the second main logic module Port_1 One of block.It is obtained by the direct example of DDR2 controller IP, and the purpose is to provide the straight of the DDR2 SDRAM outside to FPGA unit Connect access interface.Its major function includes:

1) access interface to DDR2 SDRAM is provided；

2) cooperate with DDR2 module for reading and writing, most of number between emulation testing snap-gauge card of the embodiment of the present invention and host computer is provided According to large capacity cache function.

DDR2 controller IP module outward direction directly with external DDR2 SDRAM direct interface；Inward direction and DDR2 are read Writing module direct interface.

DDR2 controller IP module needs host computer to be managed for configuration by special purpose interface.

13, DDR2 module for reading and writing

DDR2 module for reading and writing belong to the first main logic module Port_0 or the second main logic module Port_1 submodule it One.The purpose is to provide the arbitrated logic of a customized more data path timesharing access DDR2 SDRAM.Its major function Include:

1) coordinate timesharing between multichannel uplink and downlink data flow and access DDR2 SDRAM.

DDR2 module for reading and writing outward direction and DDR2 controller IP module direct interface；Inward direction and frame establish module with And dma logic module direct interface.

The module do not need special register for configure or status inquiry.

Referring to shown in Fig. 4, upstream data interaction diagrams provided in an embodiment of the present invention, show in figure FPGA unit with The communication flow of host computer.The common simulation test card of the embodiment of the present invention be as a PCI-E device, it is total by PCI-E Line comes and host computer communication.Two port channel the first main logic module Port_0 and the second main logic module in FPGA unit The data flow of Port_1 is logically incoherent, but communication modes are identical.The data of two port channels By the time-sharing multiplex logic of module, it is used in conjunction with PCI-E bus resource and host computer communicates.

FPGA unit is interacted with the upstream data of host computer:

FPGA unit is interacted as described below by PCI-E bus with the upstream data of host computer:

1) rear host computer driving application Mem (memory) space is powered on, and establishes corresponding address table (upstream and downstream is equal Have)；

2) host computer driving is respectively written into uplink address table under in a manner of BAR (register mappings access) to FPGA unit The physical address and length of row address table；

3) host computer driving notifies FPGA unit address table to come into force in a manner of BAR；

4) FPGA unit reads an address table (address table unit knot of 512B in a manner of DMA (direct memory access) Structure is 64bit, and wherein 32bit indicates practical Mem physical address, and in addition 32bit includes the information such as OwnerBit, virtual address. Therefore it only includes 64 Mem address entries that the address table of 512B is practical)；

5) FPGA unit presses the Mem address entries of address table with dma mode, if the OwnerBit of an address Mem is 1, then to Mem address entries write-in data, (data of write-in are the integral multiple of 512B, and incomplete part is had using filling It imitates data length to be indicated by frame head inside data).If the OwnerBit of an address Mem is 0, FPGA unit if, can Xiang Shangwei Machine hair interrupts, and indicates, until host computer execution step 3, to issue Mem resource available alert without that can use Mem resource；

6) FPGA updates address table with dma mode, mainly modifies the OwnerBit of the address table of the used address Mem Etc. information.This time DMA write is non-fixed length；

7) FPGA sends out to host computer and interrupts, and indicates that a upstream data access is completed；

8) host computer driving to be to interrupt as signal, to OwnerBit in updated address table be 0 Mem address space into Row read operation reads data and updates the OwnerBit of appropriate address, sets 1 with Free up Memory；

9) FPGA has next Mem address entries after address pointer is directed toward last time DMA, if on continuing to have Data requirements is passed, and 64 address entries of last application are not finished, then repeatedly step 5~8.If 64 address entries It is finished and still has data to transmit, FPGA can preferentially execute step 4, then execute step 5~8.

It referring to Figure 5, is downlink data interaction diagrams provided in an embodiment of the present invention.FPGA unit is shown in figure With the downlink data interactive process of host computer.

FPGA unit can be summarized by the downlink data interaction of PCI-E bus and host computer are as follows:

1) it powers on the rear host computer driving application space Mem, and establishes corresponding address table (upstream and downstream has)；

2) host computer driving is respectively written into uplink address table and downlink address table physically to FPGA unit in a manner of BAR Location and length；

3) host computer writes data to the corresponding space Mem by address table sequence；

4) it is 0 that host computer, which sets the corresponding OwnerBit of address table,；

5) in a manner of BAR, notice FPGA unit has downlink data for host computer driving；

6) FPGA unit reads the address table of 512B with dma mode；

7) FPGA unit is fixed length DMA according to the address that OwnerBit in address table is 0, reads the number in the corresponding space Mem According to；

8) FPGA unit updates address table with dma mode, and the OwnerBit for setting last time read Mem space address is 1. This DMA is non-fixed length；

9) if host computer encounters the case where next address entrance OwnerBit to be used is 0 (i.e. FPGA unit is very All the data of Mem are not taken away for a long time), then it can temporarily cease and write data and wait, inquire address again after a certain period of time The OwnerBit situation of entrance.Until OwnerBit is 1, then repeatedly step 3~8 or time-out report an error.

It is FPGA internal data flow diagram provided in an embodiment of the present invention referring to shown in Fig. 6.

It is segmentation and the recombination schematic diagram of ULP data block provided in an embodiment of the present invention referring to shown in Fig. 7.

It is provided in FC-2 layers of communications protocol, FC-2 layers (Upper Level Protocol, upper-layer protocol are FC associations with ULP A kind of protocol hierarchy defined in view) between transmission block minimum unit be " sequence ".So-called " sequence " just refers to identical Sequence I D (sequence identifier) a frame or multiple frames set, one include n frame sequence, can be each frame By transmission sequence, Sequence Counter (sequence number) value of 0~n-1 is distributed.Sequence ID and Sequence The value of Counter can all correspond in position in the frame head of each frame to be embodied.

During ULP sends data to optical port, ULP passes through PCIE bus, data block to be sent and transmission ginseng Number (service class, transmission strategy, error handle strategy etc.) is sent to FC-2 layers.FC-2 layers of logical root are according to information above, by data Block splits into sizeable segmentation (one or more) in order, then these data sectionals are encapsulated into the data field of FC frame In, and add SOF, EOF, frame head and CRC (cyclic redundancy check) appropriate.This completes a data blocks to decompose simultaneously The process of framing.

Equally, FC-2 layers of logic receive a complete sequence via optical port, can be according to frame each in the sequence Sequence Counter extracts the content in data field in order and assembles.This completes a frame parsings simultaneously The process of recombination data block.It can be in due course later and the data block is uploaded to host computer via PCIE bus.

In embodiments of the present invention, FC common simulation test card product function and performance indicator are as described below:

1) double optical port channels, full duplex communication；

2) optical port communication speed supports 1.0625Gbps or 2.125Gbps, can configure；

3) point-to-point and commutative Topology structure are supported；

4) meet FC-PI protocol requirement；

5) 1,2,3 class services are supported, support automatic BB diameter credit control；

6) FC-AE-ASM agreement is supported；

7) support multiple-working mode and line topological mode combination settings, can be formed parallel simulation, bypass monitor, in After integrated modes such as monitoring；

8) statistics and real-time display for supporting working global information, receiving frame sum, transmission frame including each optical port are total Number, erroneous frame sum, real-time bandwidth etc.；

9) it supports multi-page real time monitoring, supports the monitoring display filtering setting of multiple groups, polymorphic type；

10) support real-time protocol (RTP) parsing, the data entry that user chooses can protocol analysis page display data content with The detailed annotation in each region of frame head；

11) multiple groups, the setting of the reception trigger condition of polymorphic type, including the triggering such as data content matching, timing, quantitative are supported Type；

12) simple and direct text editing scripting language is provided, user is supported to write transmission data, sending data includes primitive class Type and frame type, and multiple groups, polymorphic type pre-configuration sendaisle are provided；

13) user can be arranged by interface and be sent immediately, or pass through the combination of trigger condition and pre-configuration sendaisle Setting is according to condition automatic to be sent；

14) it supports user setting complex state machine, realizes that the combination transmission of a variety of trigger conditions or automatic cycle send body System；

15) it supports to receive data storage, user may specify data storage location and storage file size, and when Coutinuous store surpasses Cross file maximum capacity new files will continue to store automatically；

16) multiple groups, polymorphic type stored filter condition setting are supported, user can be set only storage critical data and deposit to improve Store up efficiency；

17) it supports storing data playback, supports the association playback of Coutinuous store file；

18) it supports dedicated FC-AE-ASM agreement storing data playback parsing, provides FC-AE-ASM agreement for user ULP layer protocol analytical form；

19) the same display filter condition setting for supporting multiple groups, polymorphic type of storage playback；

20) second development interface is supported, above functions extends use with can realize per family by api interface.

21) Windows32 systems are supported；

22) PCIe x8 interface meets 1.0 interface protocol specification of PCIe.

The embodiment of the present invention is based on FPGA unit and constructs fiber channel protocol common simulation test card, and is provided with institute The structure of FPGA unit and the sub-modular structure of FPGA unit main logic module are stated, can be realized according to preset application demand Control logic function can satisfy user so as to cooperate the emulation testing function of realizing the embodiment of the present invention with host computer A variety of demands.

It should be noted that, in this document, the terms "include", "comprise" or its any other variant are intended to non-row His property includes, so that the process, method, article or the device that include a series of elements not only include those elements, and And further include other elements that are not explicitly listed, or further include for this process, method, article or device institute it is intrinsic Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including being somebody's turn to do There is also other identical elements in the process, method of element, article or device.

The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.

Through the above description of the embodiments, those skilled in the art can be understood that in above-described embodiment Method can realize by means of software and necessary general hardware platform, naturally it is also possible to by hardware, but many feelings The former is more preferably embodiment under condition.Based on this understanding, part of the invention can embody in the form of software products Out, which is stored in a storage medium (such as ROM/RAM, magnetic disk, CD), including some instructions are used So that a terminal device executes the method or process for including in the embodiment of the present invention.

The above is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair Equivalent structure or equivalent flow shift made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant skills Art field, is included within the scope of the present invention.

Claims (8)

1. a kind of fiber channel protocol common simulation test card cooperates with host computer and realizes emulation testing function, feature It is, comprising:

On-site programmable gate array FPGA unit, for realizing control logic function according to preset application demand；

Optical module interface unit SFP is used for receiving-transmitting chain optical signal, and converts serial digital signal for the optical signal received For FPGA unit processing, while optical signal is converted by the serial digital signal from FPGA unit and is sent to optical fiber link；

Edge connector, the bus interface PCI-E slot for the host computer backboard that one end connecting test card is inserted into, the other end It is connect with FPGA unit, the high-speed data between host computer being inserted into for realizing test card with test card exchanges；

Synchronous DRAM SDRAM, external memory chip on fixed plate are used for FPGA unit internal microprocessor The instruction of PowerPC and data store；

Configuration circuit powers on load configuration for FPGA unit, is non-volatile flash memory chip；

Flash cell, the load that powers on for PowerPC in FPGA unit configure, and are non-volatile flash memory chip；

Clock unit generates the clock source used for each circuit module for providing high-precision active clock；

Joint test working group jtag interface, for being used for FPGA download configuration and for PowerPC debugging；

Wherein, the FPGA unit includes one of following submodule or two or more any combination:

First coding module GTX_0 and the second coding module GTX_1 for receiving and dispatching optical signal, and realizes optical signal and serial Mutual conversion between data-signal；

Routing module provides variable outbound data stream topological structure for two channels FPGA, it can be achieved that two channel parallels, friendship The data of the types such as fork, interior winding route；

First main logic module Port_0 or the second main logic module Port_1 is controlled for realizing according to preset application demand Logic function,

PCI-E IP kernel module directly uses IP kernel example for the interface module that FGPA unit is connect with host computer PC I-E bus Change；

Channel data buffer and arbitration logic, for dispatching the first main logic module Port_0 and the second main logic module Two logic modules of Port_1 solve the conflict of data transmission between multiport to the data flow between PCI-E bus.

2. fiber channel protocol common simulation test card according to claim 1, which is characterized in that

The joint test working group jtag interface shares 3 sets, wherein it is a set of dedicated for FPGA download configuration, in addition it is used for for two sets PowerPC debugging uses.

3. fiber channel protocol common simulation test card according to claim 1, which is characterized in that the clock unit mentions The active clock of the high-precision of confession is 25MHz.

4. fiber channel protocol common simulation test card according to claim 1, which is characterized in that

The fiber channel protocol common simulation test card further includes one or more kinds of combinations with lower module:

DIMM formula connection slot of dual inline memory module, the large capacity external data storage for FPGA unit；

Front-panel led, for providing binary channels optical port working condition mark；

Extended interface unit is used for customized multi-purpose interface, including international time format code IRIG-B signal, external trigger Input, trigger output signal.

5. fiber channel protocol common simulation test card according to claim 1, which is characterized in that the FPGA unit is also Include:

Expansion module, for keeping for extended function module and interface.

6. fiber channel protocol common simulation test card according to claim 1, which is characterized in that first main logic Module Port_0 or the second main logic module Port_1 includes any combination of following submodule: receiving buffer area, sends buffering Area, transmit queue management module, international time format code IRIG module, register group, direct memory access DMA control Device, monitoring data preprocessing module, buffering are to buffering BB credit buffer area, end-to-end EE credit buffer area, link control logic Module, frame establish module, direct fault location module, transmit queue management module, send buffer area, microprocessor PPC interruption control Device, synchronous DRAM sdram controller, Double Data Rate synchronous DRAM DDR2 controller, port number PLB is cached according to buffer area, local self-defined bus Local Bus, pipeline burst type；Wherein,

The reception buffer area is respectively supplied to monitoring data and locates in advance for receiving data flow and caching from routing module Module, BB credit buffer area, direct fault location module are managed, is made for monitoring data access, link control access, direct fault location access With；

The transmission buffer area is aligned, arranges and be sent to routing for caching the data flow from transmit queue management module Module；

The IRIG module is also used to realize transmitting-receiving and processing outer synchronous signal for generating IRIG markers；

The register group has the set of registers with base register PCI-E BAR space reflection address；

The dma controller, the data flow control on local self-defined bus Local Bus between each submodule；

The monitoring data preprocessing module adds for receiving and buffering link data, categorized, compression and registration process After added-time mark and additional information, channel data buffer area is sent in DDR2 or is sent directly to；

BB credit buffer area, for receiving fiber channel protocol FC message and link response primitive with frame structure, into Row buffer judges buffer area flow control, and prompts frame to establish module and generate link response primitive appropriate；

EE credit buffer area carries out end-to-end buffer area flow control judgement, and mention for receiving the FC message with frame structure Show that frame establishes module and generates FC response frame appropriate；

The link control logic module, for according to chain road receive for protocol layer link control primitive sequence and Frame message executes corresponding link reset or control protocol, and prompts frame to establish module and generate FC response primitive sequence appropriate Or response frame；

The frame establishes module, the group for being sent according to BB credit buffer area, EE credit buffer area, link control logic module Frame or group primitives, and FC message appropriate is generated according to the content of corresponding states register, then by the sequence hair of agreement It send to transmit queue management module；

The direct fault location module, for according to brief introduction trigger Trigger register matching instruction and direct fault location strategy The instruction of register carries out real time fail injection behavior to the link original message received, then sends out modified message It send to transmit queue management module；

The transmit queue management module, for receiving the gentle transmission message brought from multiple modules, and according to treaty rule It sorts and is sent to transmission buffer area and be also responsible for the management of message length matching mechanisms under direct fault location mode；

The transmission buffer area receives and buffers the message from transmit queue management module, is then forwarded to routing module；

The microprocessor PPC interrupt control unit, for management role in the interrupt signal of PowerPC；

The sdram controller, for providing the interface module of SDRAM chip outside access FPGA；

The DDR2 controller, for providing the interface module of DDR2SDRAM chip outside access FPGA；

The channel data buffer area, for managing and buffering the main logic module in single channel for PCI-E bus interface mould The uplink and downlink data flow of block；

The Local Bus, for connecting data, address and the customized internal bus for controlling signal of multiple submodule；

The PLB, for connecting the internal bus of PowerPC submodule associated therewith.

7. a kind of fiber channel protocol common simulation test card data interactive method, for carrying out upstream data interaction, feature It is, the method is realized based on fiber channel protocol common simulation test card of any of claims 1-6, described Method includes:

1) power on the rear host computer driving application space memory Mem, and establish corresponding address table, including uplink address table with Downlink address table；

2) host computer driving is respectively written into uplink address table and downlink address to FPGA unit in a manner of register mappings access BAR The physical address and length of table；

3) host computer driving notifies FPGA unit address table to come into force in a manner of BAR；

4) FPGA unit reads the address table of 512B with direct memory access dma mode；

5) when the OwnerBit for determining the address Mem is 1 data are written to the Mem address entries, when determining in FPGA unit When the OwnerBit of the address Mem is 0, FPGA unit is sent out to host computer is interrupted, and indicates that Mem resource can not be used, until under host computer Send out Mem resource available alert；

6) FPGA updates address table with dma mode, the OwnerBit information of the address table including modifying the used address Mem；

7) FPGA sends out to host computer and interrupts, and indicates that a upstream data access is completed；

8) host computer driving reads the Mem address space for being 0 of OwnerBit in updated address table with interrupting as signal Operation reads data and updates the OwnerBit of appropriate address, sets 1 with Free up Memory；

9) FPGA address pointer is directed toward next Mem address entries after last time DMA, uploads data need when continuing to have It asks, and 64 address entries of last application are not finished, then repeatedly step 5~8；When 64 address entries are finished and are still had Data will be transmitted, and FPGA executes step 4, then execute step 5~8.

8. a kind of fiber channel protocol common simulation test card data interactive method, for carrying out downlink data interaction, feature It is, the method is realized based on fiber channel protocol common simulation test card of any of claims 1-6, described Method includes:

1) the rear host computer driving application space Mem is powered on, and establishes corresponding address table, including uplink address table and downlink Address table；

2) host computer driving in a manner of BAR to FPGA unit be respectively written into uplink address table and downlink address table physical address and Length；

3) host computer writes data to the corresponding space Mem by address table sequence；

4) it is 0 that host computer, which sets the corresponding OwnerBit of address table,；

5) in a manner of BAR, notice FPGA unit has downlink data for host computer driving；

6) FPGA unit reads the address table of 512B with dma mode；

7) FPGA unit is fixed length DMA according to the address that OwnerBit in address table is 0, reads the data in the corresponding space Mem；

8) FPGA unit updates address table with dma mode, and the OwnerBit for setting last time read Mem space address is 1；

9) host computer determine next address entrance OwnerBit to be used be 0 when, temporarily cease and write data and wait, The OwnerBit situation for inquiring address entries again after setting time, until OwnerBit is 1, then repeatedly step 3~8, Or time-out reports an error.