CN104780333A - High-bandwidth video source interface adaptation device based on FPGA (Field Programmable Gate Array) - Google Patents
High-bandwidth video source interface adaptation device based on FPGA (Field Programmable Gate Array) Download PDFInfo
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Abstract
The invention belongs to the field of video source interface adaptation technologies, and particularly relates to a high-bandwidth video source interface adaptation device based on an FPGA (Field Programmable Gate Array). The technical scheme is as follows: a high-speed serial GTX transceiver based on a multichannel FPGA chip can play the characteristic of parallel hardware execution of conversion of an FPGA interface protocol and complete conversion adaption of the protocols of multiple ways of video sources with different transmission protocols and different transmission ways of a video processing center, so that each video source is transmitted to a video processing node of a video processing platform according to a unified protocol, so that a video processing task is completed, analysis of the video processing node on the protocols of the different video sources is effectively avoided, and computing power of the video processing node can be released, and thus the task processing efficiency of the video processing center can be improved.
Description
Technical field
The invention belongs to video source interface adaptation technique field, be specifically related to a kind of high-bandwidth video source interface adaptive device based on FPGA.
Background technology
At present, along with naval vessel show control platform at a high speed, the demand of high-quality video information is increasing, video processing platform arises at the historic moment.The video processing duties such as video processing platform can superpose the video source such as radar, infrared, TV, meteorology, aobvious control image and Video processing center generation video, convergent-divergent, splicing, cutting, rotation, 2D/3D acceleration.The video source (computing node of video processing platform may have different frameworks) from outside and the generation of other nodes of video processing platform of video processing platform may be sent to Video processing center with the different agreements such as FC agreement, serial RapidIO, PCI-E, LVDS, VGA and DVI and transmission medium, and with different interface shapes.If utilize Video processing central task processing node to complete the computation burden that video source protocol analysis will certainly strengthen task processing node.Consider the high speed serialization GTX transceiver of FPGA can reach 600Mbps ~ 6.6Gbps wire rate (even higher), take that pin is few, EMI index is excellent and cost is lower and the advantage such as default multiple high speed transport protocols, be necessary to design a kind of multi-channel video source interface adaptive device based on FPGA, to solve video processing platform video source interface adaptation issues.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is: the interface resource how enriched based on FPGA and parallel processing capability solve the interface protocol adaptation issues in the multiple different video source of video processing platform.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of high-bandwidth video source interface adaptive device based on FPGA, it is arranged in Video processing central server, and described Video processing central server comprises several video processing modules, information exchange module, high-bandwidth video source interface adaptive device and power module; Described video processing module provides computational resource for aobvious control task, and it is based on Intel Virtualization Technology, is set to process multiple aobvious control task; Described information exchange module under VPX framework is used for realizing RapidIO, 1G Ethernet and LVDS function of exchange; Described high-bandwidth video source interface adaptive device, for realizing the conversion of FC, RapidIO, PCI-E, LVDS, DVI and VGA agreement, is converted into the video/image form of video processing module demand by aobvious control task; Described power module is used for, for the different power supply of above-mentioned block configuration, carrying out intelligent management by power management chip to power supply simultaneously;
Described high-bandwidth video source interface adaptive device comprises: multichannel GTX video source transmit-receive platform, XILINX V6FPGA module, Ethernet chip, DDR2, FLASH, JTAG debugging interface, SFP interface, Ethernet interface, RapidIO interface, PCI-E interface, LVDS interface, DVI interface, USB interface; After the video source signal transmitted by various different agreement and interface shape enters video source interface adaptation module, XILINX V6FPGA module is utilized to complete protocol adaptation conversion; Further, Ethernet protocol is resolved and is completed by Ethernet chip, and all kinds of high bandwidth interface is connected by FPGA GTX interface, and other video source interfaces are connected by FPGA general-purpose interface;
Wherein, utilize GTX to support the feature of FC, PCI-E, RapidIO, LVDS many kinds of Gb SERDES agreements, set up multichannel GTX video source transmit-receive platform; In GTX video source transmit-receive platform, according to the concrete form of video source interface and agreement, design corresponding GTX transceiver, GTX transceiver comprises serializer, deserializer, RX alignment unit, Clock Managing Unit, transmission cell fifo, reception cell fifo, simulation receiving interface, simulation transmission interface, line coder, line translator, clock correction and passage and binds unit, cyclic redundancy check unit and adjustable scrambler;
Complete in each video source interface protocol resolving:
For the video source of pressing FC protocol transmission, XILINX V6FPGA module is utilized to set up 5 layer protocol frameworks of FC-0 physical link layer, FC-1 decoding and coding layer, FC-2 flow control policy/frame protocol, FC-3 generic service layer and FC-4 upper-layer protocol mapping layer, framework content specifically comprises transmission medium, transmission rate, topological structure, light transceiver controller, coding protocol, frame format, frame sequence, Frame switch, and COS, Public service mechanism and upper layer application protocol are selected; Under normal circumstances, during transmission of video information, FC upper layer application protocol selects FC-AV sound, transmission of video agreement or ARINC818 transmission of video agreement; Adaptive in order to realize with the interface of FC protocol transmission video source, utilize XILINX V6FPGA module to resolve by FC upper layer application protocol; Video data stream is divided into a series of block of information to transmit by regular hour sequence, and each frame video information block is encapsulated in a container; After resolving by FC upper layer application protocol, obtain the video information of a frame, put it in DDR2 and carry out buffer memory, so that video processing module reads;
For the video source of pressing PCI-E protocol transmission, XILINX V6FPGA module is utilized to set up the multi-layer protocol framework of transport layer, data link layer, physical layer; When video information sends, crc field is added in transport layer, form transport layer data bag, sequence code and 4 byte link CRC formation data link layer packets of 2 bytes are added in data link layer, form physical layer data bag in physical layer, and complete byte split, scramble, coding and serioparallel exchange process; Receiving course is the inverse process of said process, unpacks the video information obtaining a frame sequentially through data, puts it in DDR2 and carries out buffer memory, so that video processing module reads;
For the video source of pressing RapidIO protocol transmission, XILINX V6FPGA module is utilized to set up logical layer, transport layer and physical layer protocol framework; Complete direct IO or DMA at logical layer, the mailbox number according to receiving packet is saved in corresponding buffering area data, forms the video information of a frame, so that video processing module reads; Interconnection mode between communication node, the route of packet switch and addressing mechanism is completed in transport layer; Reception difference AC-coupled signal, serial/parallel conversion, 10b/8b decode operation is carried out in physical layer;
For the video source of pressing the conventional display protocol transmission of LVDS, DVI and VGA, because agreement is relatively simple, without the need to setting up multi-layer protocol framework, XILINX V6FPGA module is directly utilized to complete protocol analysis, design corresponding buffering, store complete video requency frame data sequence, so that video processing module reads;
In the course of work, the conversion of the transmitting-receiving of specific implementation GTX HSSI High-Speed Serial Interface and agreement is the core work of video source interface adaptive device; Wherein, described serializer is for by speed being the serial data that the n bit wide parallel data of y changes n × y into; The work of described deserializer is the inverse process of serializer; Described RX alignment unit is used for the alignment of data of reception to suitable word boundary; Described timer manager has been used for frequency division, frequency multiplication, clock recovery clock operation; Described transmission cell fifo is used for preserving it before data send; Described reception cell fifo is used for preserving it before being extracted receiving data; Described simulation receiving interface and described simulation transmission interface are used for providing simulation to receive, sending difference channel; It is the form adapting to different circuit that described line coder is used for data encoding; Described line translator is for being decomposed into initial data by the coded data on circuit; Described clock correction and passage bind unit for revising the deviation between tranmitting data register and receive clock, simultaneously also for realizing the crooked correction between multichannel; Described cyclic redundancy check unit has been used for the generation of CRC code, the checking of CRC code; Described adjustable scrambler is used for realizing scrambler, daisy chain function.
(3) beneficial effect
By the multichannel GTX video source that relates in the present invention receive hardware platform, the adaptive control module of video source interface, the protocol adaptation conversion to the multiple video source by Gb SERDES protocol transmission and the video source to display protocol transmission routinely protocol adaptation conversion can solve the video source interface adaptation issues of video processing platform well.
Compared with prior art, the present invention possesses following beneficial effect: the high-bandwidth video source interface adaptive device based on FPGA that technical solution of the present invention provides, it comprises the high speed serialization GTX transceiver based on multichannel fpga chip, can play the conversion of FPGA interface protocol can the feature of hardware executed in parallel, complete the multichannel differing transmission protocols of Video processing center (Video processing private server), the protocol conversion of different transmission means video source is adaptive, each video source is made to transfer to the Video processing node of video processing platform by uniform protocol, to complete video processing duties, effectively prevent the protocol analysis of Video processing node to different video source, the computing capability of Video processing node can be discharged, and then the task treatment effeciency at Video processing center can be improved.
Accompanying drawing explanation
Fig. 1 is Video processing central server configuration diagram.
Fig. 2 is high-bandwidth video interface adaptive device theory diagram.
Fig. 3 is GTX high-speed serial I/O theory diagram.
Embodiment
For making object of the present invention, content and advantage clearly, below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
For solving the problem of prior art, the invention provides a kind of high-bandwidth video source interface adaptive device based on FPGA, it is arranged in Video processing central server, as shown in Figure 1, described Video processing central server comprises several video processing modules, information exchange module, high-bandwidth video source interface adaptive device and power module; Described video processing module provides computational resource for aobvious control task, and it is based on Intel Virtualization Technology, is set to process multiple aobvious control task; Described information exchange module under VPX framework is used for realizing RapidIO, 1G Ethernet and LVDS function of exchange; Described high-bandwidth video source interface adaptive device, for realizing the conversion of the agreements such as FC, RapidIO, PCI-E, LVDS, DVI and VGA, is converted into the video/image form of video processing module demand by aobvious control task; Described power module is used for, for the different power supply of above-mentioned block configuration, carrying out intelligent management by power management chip to power supply simultaneously;
As shown in Figure 2, be the theory diagram of high-bandwidth video source interface adaptive device; Described high-bandwidth video source interface adaptive device comprises: multichannel GTX video source transmit-receive platform, XILINX V6FPGA module, Ethernet chip, DDR2, FLASH, JTAG debugging interface, SFP interface, Ethernet interface, RapidIO interface, PCI-E interface, LVDS interface, DVI interface, USB interface; After the video source signal transmitted by various different agreement and interface shape enters video source interface adaptation module, XILINX V6FPGA module is utilized to complete protocol adaptation conversion; Further, Ethernet protocol is resolved and is completed by Ethernet chip, and all kinds of high bandwidth interface is connected by FPGA GTX interface, and other video source interfaces are connected by FPGA general-purpose interface;
Wherein, GTX (gigabit) is utilized to support the feature of the multiple Gb SERDES such as FC, PCI-E, RapidIO, LVDS agreement, adaptive for meeting various video source interface, set up multichannel GTX video source transmit-receive platform; In GTX video source transmit-receive platform, according to the concrete form of video source interface and agreement, design corresponding GTX transceiver, GTX transceiver comprises serializer, deserializer, RX alignment unit, Clock Managing Unit, transmission cell fifo, reception cell fifo, simulation receiving interface, simulation transmission interface, line coder, line translator, clock correction and passage and binds unit, cyclic redundancy check unit (CRC) and adjustable scrambler etc.;
The internodal communication issue of many Video processing for above-mentioned multichannel GTX video source transmit-receive platform and video processing module designs adaptive control device further.PCI-E is utilized the control information such as the selection of the video source of each Video processing node, video source form, transmission rate and buffer mode to be sent to the adaptive control device of FPGA realization.By setting up the virtual signal switching matrix between multichannel GTX transceiver channel and each video node, can complete each video source to object Video processing node transmission, switch in real time, the task such as the multichannel distribution of single channel video source, different aobvious control task can be met to the demand of video source.
Complete each video source interface protocol to resolve.
For the video source of pressing FC protocol transmission, XILINX V6FPGA module is utilized to set up 5 layer protocol frameworks of FC-0 physical link layer, FC-1 decoding and coding layer, FC-2 flow control policy/frame protocol, FC-3 generic service layer and FC-4 upper-layer protocol mapping layer, framework content specifically comprises transmission medium, transmission rate, topological structure, light transceiver controller, coding protocol, frame format, frame sequence, Frame switch, and COS, Public service mechanism and upper layer application protocol are selected; Under normal circumstances, during transmission of video information, FC upper layer application protocol selects FC-AV sound, transmission of video agreement or ARINC818 transmission of video agreement; Adaptive in order to realize with the interface of FC protocol transmission video source, XILINX V6FPGA module need be utilized to resolve by FC upper layer application protocol; Video data stream is divided into a series of block of information to transmit by regular hour sequence, and each frame video information block is encapsulated in a container; After resolving by FC upper layer application protocol, the video information of a frame can be obtained, put it in DDR2 and carry out buffer memory, so that video processing module reads;
For the video source of pressing PCI-E protocol transmission, XILINX V6FPGA module is utilized to set up the multi-layer protocol framework of transport layer, data link layer, physical layer; When video information sends, crc field is added in transport layer, form transport layer data bag, sequence code and 4 byte link CRC formation data link layer packets of 2 bytes are added in data link layer, form physical layer data bag in physical layer, and complete the processes such as byte split, scramble, coding and serioparallel exchange; Receiving course is the inverse process of said process, can unpack the video information obtaining a frame, put it in DDR2 and carry out buffer memory sequentially through data, so that video processing module reads;
For the video source of pressing RapidIO protocol transmission, XILINX V6FPGA module is utilized to set up logical layer, transport layer and physical layer protocol framework; Complete direct IO or DMA at logical layer, the mailbox number according to receiving packet is saved in corresponding buffering area data, forms the video information of a frame, so that video processing module reads; Interconnection mode between communication node, the route of packet switch and addressing mechanism is completed in transport layer; Reception difference AC-coupled signal, serial/parallel conversion, 10b/8b decode operation is carried out in physical layer;
For the video source of pressing the conventional display protocol transmission such as LVDS, DVI and VGA, because agreement is relatively simple, without the need to setting up multi-layer protocol framework, XILINX V6FPGA module is directly utilized to complete protocol analysis, design corresponding buffering, store complete video requency frame data sequence, so that video processing module reads;
In the course of work, the conversion of the transmitting-receiving of specific implementation GTX HSSI High-Speed Serial Interface and agreement is the core work of video source interface adaptive device; GTX workflow can see accompanying drawing 3; Wherein, described serializer is for by speed being the serial data that the n bit wide parallel data of y changes n × y into; The work of described deserializer is the inverse process of serializer; Described RX alignment unit is used for the alignment of data of reception to suitable word boundary; Described timer manager has been used for the various clock operations such as frequency division, frequency multiplication, clock recovery; Described transmission cell fifo is used for preserving it before data send; Described reception cell fifo is used for preserving it before being extracted receiving data; Described simulation receiving interface and described simulation transmission interface are used for providing simulation to receive, sending difference channel, and it supports multiple driving; It is the form adapting to different circuit that described line coder is used for data encoding; Described line translator is for being decomposed into initial data by the coded data on circuit; Described clock correction and passage bind unit for revising the deviation between tranmitting data register and receive clock, simultaneously also for realizing the crooked correction between multichannel; Described cyclic redundancy check unit has been used for the generation of CRC code, the checking of CRC code; Described adjustable scrambler is used for realizing scrambler, daisy chain function.
To sum up, high-bandwidth video source interface adaptive device based on FPGA provided by the present invention, it utilizes the parallel processing capability of FPGA, with multipath high-speed serial GTX transmit-receive platform for core, the interface protocol conversion adaptation with multichannel differing transmission protocols, different transmission means video source at Video processing center (Video processing special VPX IA frame serverPC) can be realized, make each video source transfer to the Video processing node of video processing platform by uniform protocol.Video source interface adaptive device can complete the conversion of the transmission of video agreement such as FC agreement, serial RapidIO, PCI-E, LVDS, VGA, DVI.Video source Interface Video device can effectively avoid Video processing node to the protocol analysis in different video source, and the computing capability of release Video processing node, improves the video task treatment effeciency at Video processing center greatly.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and distortion, these improve and distortion also should be considered as protection scope of the present invention.
Claims (1)
1. the high-bandwidth video source interface adaptive device based on FPGA, it is characterized in that, it is arranged in Video processing central server, and described Video processing central server comprises several video processing modules, information exchange module, high-bandwidth video source interface adaptive device and power module; Described video processing module provides computational resource for aobvious control task, and it is based on Intel Virtualization Technology, is set to process multiple aobvious control task; Described information exchange module under VPX framework is used for realizing RapidIO, 1G Ethernet and LVDS function of exchange; Described high-bandwidth video source interface adaptive device, for realizing the conversion of FC, RapidIO, PCI-E, LVDS, DVI and VGA agreement, is converted into the video/image form of video processing module demand by aobvious control task; Described power module is used for, for the different power supply of above-mentioned block configuration, carrying out intelligent management by power management chip to power supply simultaneously;
Described high-bandwidth video source interface adaptive device comprises: multichannel GTX video source transmit-receive platform, XILINX V6 FPGA module, Ethernet chip, DDR2, FLASH, JTAG debugging interface, SFP interface, Ethernet interface, RapidIO interface, PCI-E interface, LVDS interface, DVI interface, USB interface; After the video source signal transmitted by various different agreement and interface shape enters video source interface adaptation module, XILINX V6 FPGA module is utilized to complete protocol adaptation conversion; Further, Ethernet protocol is resolved and is completed by Ethernet chip, and all kinds of high bandwidth interface is connected by FPGA GTX interface, and other video source interfaces are connected by FPGA general-purpose interface;
Wherein, utilize GTX to support the feature of FC, PCI-E, RapidIO, LVDS many kinds of Gb SERDES agreements, set up multichannel GTX video source transmit-receive platform; In GTX video source transmit-receive platform, according to the concrete form of video source interface and agreement, design corresponding GTX transceiver, GTX transceiver comprises serializer, deserializer, RX alignment unit, Clock Managing Unit, transmission cell fifo, reception cell fifo, simulation receiving interface, simulation transmission interface, line coder, line translator, clock correction and passage and binds unit, cyclic redundancy check unit and adjustable scrambler;
Complete in each video source interface protocol resolving:
For the video source of pressing FC protocol transmission, XILINX V6 FPGA module is utilized to set up 5 layer protocol frameworks of FC-0 physical link layer, FC-1 decoding and coding layer, FC-2 flow control policy/frame protocol, FC-3 generic service layer and FC-4 upper-layer protocol mapping layer, framework content specifically comprises transmission medium, transmission rate, topological structure, light transceiver controller, coding protocol, frame format, frame sequence, Frame switch, and COS, Public service mechanism and upper layer application protocol are selected; Under normal circumstances, during transmission of video information, FC upper layer application protocol selects FC-AV sound, transmission of video agreement or ARINC818 transmission of video agreement; Adaptive in order to realize with the interface of FC protocol transmission video source, utilize XILINX V6 FPGA module to resolve by FC upper layer application protocol; Video data stream is divided into a series of block of information to transmit by regular hour sequence, and each frame video information block is encapsulated in a container; After resolving by FC upper layer application protocol, obtain the video information of a frame, put it in DDR2 and carry out buffer memory, so that video processing module reads;
For the video source of pressing PCI-E protocol transmission, XILINX V6 FPGA module is utilized to set up the multi-layer protocol framework of transport layer, data link layer, physical layer; When video information sends, crc field is added in transport layer, form transport layer data bag, sequence code and 4 byte link CRC formation data link layer packets of 2 bytes are added in data link layer, form physical layer data bag in physical layer, and complete byte split, scramble, coding and serioparallel exchange process; Receiving course is the inverse process of said process, unpacks the video information obtaining a frame sequentially through data, puts it in DDR2 and carries out buffer memory, so that video processing module reads;
For the video source of pressing RapidIO protocol transmission, XILINX V6 FPGA module is utilized to set up logical layer, transport layer and physical layer protocol framework; Complete direct IO or DMA at logical layer, the mailbox number according to receiving packet is saved in corresponding buffering area data, forms the video information of a frame, so that video processing module reads; Interconnection mode between communication node, the route of packet switch and addressing mechanism is completed in transport layer; Reception difference AC-coupled signal, serial/parallel conversion, 10b/8b decode operation is carried out in physical layer;
For the video source of pressing the conventional display protocol transmission of LVDS, DVI and VGA, because agreement is relatively simple, without the need to setting up multi-layer protocol framework, XILINX V6 FPGA module is directly utilized to complete protocol analysis, design corresponding buffering, store complete video requency frame data sequence, so that video processing module reads;
In the course of work, the conversion of the transmitting-receiving of specific implementation GTX HSSI High-Speed Serial Interface and agreement is the core work of video source interface adaptive device; Wherein, described serializer is for by speed being the serial data that the n bit wide parallel data of y changes n × y into; The work of described deserializer is the inverse process of serializer; Described RX alignment unit is used for the alignment of data of reception to suitable word boundary; Described timer manager has been used for frequency division, frequency multiplication, clock recovery clock operation; Described transmission cell fifo is used for preserving it before data send; Described reception cell fifo is used for preserving it before being extracted receiving data; Described simulation receiving interface and described simulation transmission interface are used for providing simulation to receive, sending difference channel; It is the form adapting to different circuit that described line coder is used for data encoding; Described line translator is for being decomposed into initial data by the coded data on circuit; Described clock correction and passage bind unit for revising the deviation between tranmitting data register and receive clock, simultaneously also for realizing the crooked correction between multichannel; Described cyclic redundancy check unit has been used for the generation of CRC code, the checking of CRC code; Described adjustable scrambler is used for realizing scrambler, daisy chain function.
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| CN113038054A (en) * | 2021-03-04 | 2021-06-25 | 苏州科达科技股份有限公司 | Video link dynamic building method and device, electronic equipment and storage medium |
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