CN111200432B - Discrete interface data receiving method - Google Patents
Discrete interface data receiving method Download PDFInfo
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- CN111200432B CN111200432B CN201911377426.8A CN201911377426A CN111200432B CN 111200432 B CN111200432 B CN 111200432B CN 201911377426 A CN201911377426 A CN 201911377426A CN 111200432 B CN111200432 B CN 111200432B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/17744—Structural details of routing resources for input/output signals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method for receiving data by a discrete interface, which comprises the following steps: firstly, software opens up an address space, sends data with the same length as the agreed data of a receiver according to test requirements, starts a receiving task, then enables a receiving enabling signal in the FPGA, polls a receiving state register of the FPGA by the software, and inquires whether a data half-empty mark bit and a frame end mark bit are valid or not; through designing a software address space, a receiving state register of a software polling FPGA and a receiving fifo in a logic end, the marking position can be effectively judged, the read data can be cleared, meanwhile, the data information can be verified in real time, the data reliability and stability are effectively improved, the problem that the traditional method for receiving the data by a discrete interface has certain defects, the corresponding judgment, clearing and verification of the information cannot be carried out, and the data reliability is difficult to guarantee is solved.
Description
Technical Field
The invention relates to the technical field of discrete interfaces, in particular to a method for receiving data by a discrete interface.
Background
The computer is a control core of electronic equipment, and is required to acquire more and more discrete quantity signals for acquiring the working state of the current system, and meanwhile, a large quantity of discrete quantity signals are required to be output for sending instructions, so that the discrete quantity signal processing capacity is continuously increased, the signal bandwidth is rapidly increased, the function is gradually complicated, and the existing discrete quantity processing scheme cannot meet the requirements of the system on various aspects such as discrete quantity signal switching speed, miniaturization, reliability and the like.
Along with the increase of discrete quantity, the traditional method for receiving data by a discrete interface has certain defects that the corresponding judgment, removal and verification work cannot be carried out on information, and the reliability of the data is difficult to ensure.
Disclosure of Invention
The invention aims to provide a method for receiving data by a discrete interface, which solves the problems that the traditional method for receiving data by the discrete interface, which is proposed in the background art, has certain defects, can not carry out corresponding judgment, clearing and checking work on information, and is difficult to ensure the reliability of the data.
In order to achieve the above purpose, the present invention provides the following technical solutions: a method of receiving data at a discrete interface, the method comprising:
(1) The software end receives the data flow:
firstly, software opens up an address space, and sends and receives data with the same length according to test requirements;
(1.2) the software initiates a receiving task and then enables a receiving enabling signal in the FPGA;
(1.3) software polls a receiving state register of the FPGA to inquire whether a data half-blank mark bit and an end-of-frame mark bit are valid;
(1.4) judging the size to be read according to the validity of the mark, and performing a clearing work of accumulating the number of the read data in the frame;
(1.5) the software reads the data with corresponding size and judges the size of the related data;
(1.6) ending;
(2) The logic receives the data flow:
(2.1) a receiving fifo is arranged inside the logic end;
(2.2) the logical side will mark after receiving 512 data or end of frame marks;
(2.3) performing data processing operations of corresponding functions through the control registers and the status registers;
(2.4) ending.
Preferably, in the step (1.2), the software needs to empty the received fifo in fpga while starting a receiving task.
Preferably, in the step (1.3), the data half-empty flag bit and the end-of-frame flag bit are respectively valid, and the data half-empty flag bit and the end-of-frame flag bit are respectively valid independently and valid simultaneously.
Preferably, in the step (1.4), if the data half-empty flag bit is valid, it indicates fifo half-empty, the size to be read is 512 bits, if the end-of-frame flag bit is valid, the software reads the frame size register, the size to be read is the value minus the value already segmented before, and if both are valid, it indicates fifo half-empty, the size to be read is 512 bits.
Preferably, in the step (1.5), the software clears the end-of-frame flag bit before reading the data.
Preferably, in the step (1.5), after the software reads the data with the corresponding size, it is determined whether the total length of the received data is reached, if so, the receiving enable signal of the FPGA is turned off, otherwise, the query of the data non-empty flag is continued.
Preferably, in the step (2.1), the default depth of the receiving fifo is 1024.
Preferably, in the step (2.2), if the logic end detects that the received fifo overflows, the logic end writes the data overflow bit, and the subsequent data is not written again until the frame is over and valid, and rewrites the received fifo.
Preferably, in the step (2.2), the logic terminal receives the enable signal, and when the enable signal is invalid, the logic terminal does not receive the data of the bus.
Preferably, in the step (2.3), the control register is configured to receive fifo empty, receive start, and receive frame length registers, and the status register is configured to perform end-of-frame (write 1 clear) and fifo half-empty.
Compared with the prior art, the invention provides a method for receiving data by a discrete interface, which has the following beneficial effects:
through designing a software address space, a receiving state register of a software polling FPGA and a receiving fifo in a logic end, the marking position can be effectively judged, the read data can be cleared, meanwhile, the data information can be verified in real time, the data reliability and stability are effectively improved, the problem that the traditional method for receiving the data by a discrete interface has certain defects, the corresponding judgment, clearing and verification of the information cannot be carried out, and the data reliability is difficult to guarantee is solved.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully, and it is apparent that the embodiments described are only some, but not all, of the embodiments of the present invention. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the inventor, are within the scope of the invention.
The invention provides a technical scheme that: a method of receiving data at a discrete interface, the method comprising:
(1) The software end receives the data flow:
firstly, software opens up an address space, and sends and receives data with the same length according to test requirements;
(1.2) the software initiates a receiving task and then enables a receiving enabling signal in the FPGA;
(1.3) software polls a receiving state register of the FPGA to inquire whether a data half-blank mark bit and an end-of-frame mark bit are valid;
(1.4) judging the size to be read according to the validity of the mark, and performing a clearing work of accumulating the number of the read data in the frame;
(1.5) the software reads the data with corresponding size and judges the size of the related data;
(1.6) ending;
(2) The logic receives the data flow:
(2.1) a receiving fifo is arranged inside the logic end;
(2.2) the logical side will mark after receiving 512 data or end of frame marks;
(2.3) performing data processing operations of corresponding functions through the control registers and the status registers;
(2.4) ending.
Embodiment one:
a method of receiving data at a discrete interface, the method comprising:
(1) The software end receives the data flow:
firstly, software opens up an address space, and sends and receives data with the same length according to test requirements;
(1.2) starting a receiving task by the software, and then enabling a receiving enabling signal in the FPGA, wherein the software needs to clear receiving fifo in FPGA when starting the receiving task, so that unknown data (not read or transmitted in time) left in the fifo can be prevented from influencing a program;
(1.3) software polls a receiving state register of the FPGA, inquires whether a data half-empty mark bit and a frame end mark bit are valid, wherein the valid conditions of the data half-empty mark bit and the frame end mark bit are three, namely, the data half-empty mark bit is valid singly, the frame end mark bit is valid singly and both are valid simultaneously, a time interval from a start bit to a stop bit is called a frame, the start bit is a transmitting data bit, the end bit is at the end and is used for marking the end of one character transmission, and the time interval corresponds to a logic 1 state;
(1.4) judging the size to be read according to the validity of the mark, and carrying out the clearing work of accumulating the number of the read data in the frame, if the data half-empty mark bit is valid, the size to be read is 512 16 bits, if the frame end mark bit is valid, the software reads the frame size register, the size to be read is the value obtained by subtracting the previous segmented value, if both the frame end mark bit and the frame end mark bit are valid, the fifo half-empty is indicated, the size to be read is 512 16 bits, for synchronous fifo, only the bit which is not empty and full is judged, for example, a 12bit signal is used for judging that the fifo is empty and full, and for asynchronous fifo, the half-full signal can be judged according to the read-write address;
(1.5) the software reads the data with corresponding size and judges the size of the related data;
(1.6) ending;
(2) The logic receives the data flow:
(2.1) a receiving fifo is arranged inside the logic end;
(2.2) the logical side will mark after receiving 512 data or end of frame marks;
(2.3) performing data processing operations of corresponding functions through the control registers and the status registers;
(2.4) ending.
Embodiment two:
a method of receiving data at a discrete interface, the method comprising:
(1) The software end receives the data flow:
firstly, software opens up an address space, and sends and receives data with the same length according to test requirements;
(1.2) starting a receiving task by the software, and then enabling a receiving enabling signal in the FPGA, wherein the software needs to clear receiving fifo in FPGA when starting the receiving task, so that unknown data (not read or transmitted in time) left in the fifo can be prevented from influencing a program;
(1.3) software polls a receiving state register of the FPGA, inquires whether a data half-empty mark bit and a frame end mark bit are valid, wherein the valid conditions of the data half-empty mark bit and the frame end mark bit are three, namely, the data half-empty mark bit is valid singly, the frame end mark bit is valid singly and both are valid simultaneously, a time interval from a start bit to a stop bit is called a frame, the start bit is a transmitting data bit, the end bit is at the end and is used for marking the end of one character transmission, and the time interval corresponds to a logic 1 state;
(1.4) judging the size to be read according to the validity of the mark, and carrying out the clearing work of accumulating the number of the read data in the frame, if the data half-empty mark bit is valid, the size to be read is 512 16 bits, if the frame end mark bit is valid, the software reads the frame size register, the size to be read is the value obtained by subtracting the previous segmented value, if both the frame end mark bit and the frame end mark bit are valid, the fifo half-empty is indicated, the size to be read is 512 16 bits, for synchronous fifo, only the bit which is not empty and full is judged, for example, a 12bit signal is used for judging that the fifo is empty and full, and for asynchronous fifo, the half-full signal can be judged according to the read-write address;
the software reads the data with corresponding size and judges the size of the related data, before the software reads the data, the software clears the end-of-frame marking bit, after the software reads the data with corresponding size, judges whether the total length of the received data is reached, if yes, the receiving enabling signal of the FPGA is closed, otherwise, the data non-empty marking is continuously inquired, each bit of the frame is confirmed through the check code, the sender attaches the check code at last, the receiver recalculates the check code, and the two numbers are the same and are considered to be correct;
(1.6) ending;
(2) The logic receives the data flow:
(2.1) a receiving fifo is arranged inside the logic end;
(2.2) the logical side will mark after receiving 512 data or end of frame marks;
(2.3) performing data processing operations of corresponding functions through the control registers and the status registers;
(2.4) ending.
Embodiment III:
a method of receiving data at a discrete interface, the method comprising:
(1) The software end receives the data flow:
firstly, software opens up an address space, and sends and receives data with the same length according to test requirements;
(1.2) starting a receiving task by the software, and then enabling a receiving enabling signal in the FPGA, wherein the software needs to clear receiving fifo in FPGA when starting the receiving task, so that unknown data (not read or transmitted in time) left in the fifo can be prevented from influencing a program;
(1.3) software polls a receiving state register of the FPGA, inquires whether a data half-empty mark bit and a frame end mark bit are valid, wherein the valid conditions of the data half-empty mark bit and the frame end mark bit are three, namely, the data half-empty mark bit is valid singly, the frame end mark bit is valid singly and both are valid simultaneously, a time interval from a start bit to a stop bit is called a frame, the start bit is a transmitting data bit, the end bit is at the end and is used for marking the end of one character transmission, and the time interval corresponds to a logic 1 state;
(1.4) judging the size to be read according to the validity of the mark, and carrying out the clearing work of accumulating the number of the read data in the frame, if the data half-empty mark bit is valid, the size to be read is 512 16 bits, if the frame end mark bit is valid, the software reads the frame size register, the size to be read is the value obtained by subtracting the previous segmented value, if both the frame end mark bit and the frame end mark bit are valid, the fifo half-empty is indicated, the size to be read is 512 16 bits, for synchronous fifo, only the bit which is not empty and full is judged, for example, a 12bit signal is used for judging that the fifo is empty and full, and for asynchronous fifo, the half-full signal can be judged according to the read-write address;
the software reads the data with corresponding size and judges the size of the related data, before the software reads the data, the software clears the end-of-frame marking bit, after the software reads the data with corresponding size, judges whether the total length of the received data is reached, if yes, the receiving enabling signal of the FPGA is closed, otherwise, the data non-empty marking is continuously inquired, each bit of the frame is confirmed through the check code, the sender attaches the check code at last, the receiver recalculates the check code, and the two numbers are the same and are considered to be correct;
(1.6) ending;
(2) The logic receives the data flow:
(2.1) a receiving fifo is arranged inside the logic end, and the default depth of the receiving fifo is 1024;
(2.2) after receiving 512 data or end-of-frame marks, the logic end will mark that if detecting that the received fifo overflows, the logic end will write the data overflow bit, and the subsequent data will not be written again until the end of the frame is valid, and then rewrites the received fifo, the logic end receives the data of the bus under the control of the reception enable signal, when the enable signal is invalid, the data of the bus will not be received, and the main reason for needing the enable signal is that in a large digital system, a plurality of chips/circuit units are usually needed to cooperate to complete a function, and the chips are not all the time working, so that the enable signal is needed to control which chip should be started to work;
(2.3) performing data processing operations with corresponding functions through a control register and a status register, wherein the control register is used for receiving fifo emptying, receiving starting and receiving frame length registers, and the status register is used for performing end-of-frame marking (writing 1 zero clearing) and fifo half-empty marking;
(2.4) ending.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A method of receiving data at a discrete interface, comprising: the method comprises the following steps:
(1) The software end receives the data flow:
firstly, software opens up an address space, and sends and receives data with the same length according to test requirements;
(1.2) the software initiates a receiving task and then enables a receiving enabling signal in the FPGA;
(1.3) software polls a receiving state register of the FPGA to inquire whether a data half-blank mark bit and an end-of-frame mark bit are valid;
(1.4) judging the size to be read according to the validity of the mark, and performing a clearing work of accumulating the number of the read data in the frame;
(1.5) the software reads the data with corresponding size and judges the size of the related data;
(1.6) ending;
(2) The logic receives the data flow:
(2.1) a receiving fifo is arranged inside the logic end;
(2.2) the logical side will mark after receiving 512 data or end of frame marks;
(2.3) performing data processing operations of corresponding functions through the control registers and the status registers;
(2.4) ending;
in the step (1.3), the valid conditions of the data half-empty mark bit and the frame end mark bit are three, namely, the data half-empty mark bit is valid independently, the frame end mark bit is valid independently and both are valid simultaneously;
in the step (1.4), if the data half-space flag bit is valid, it indicates that fifo is half-space, and the size to be read is 512 16 bits; if the end of frame flag bit is valid, the software reads the frame size register, the size to be read is the value minus the value that has been segmented away before; if both are valid at the same time, this indicates fifo half-space, and the size to be read is 512 16 bits.
2. A method of receiving data over a discrete interface as claimed in claim 1, wherein: in step (1.2), the software needs to empty the receiving fifo in fpga while starting a receiving task.
3. A method of receiving data over a discrete interface as claimed in claim 1, wherein: in step (1.5), the software clears the end of frame flag bit before reading the data.
4. A method of receiving data over a discrete interface as claimed in claim 1, wherein: in the step (1.5), after the software reads the data with the corresponding size, judging whether the total length of the received data is reached, if so, closing a receiving enabling signal of the FPGA, otherwise, continuing to inquire the data non-empty mark.
5. A method of receiving data over a discrete interface as claimed in claim 1, wherein: in the step (2.1), the default depth of the receiving fifo is 1024.
6. A method of receiving data over a discrete interface as claimed in claim 1, wherein: in the step (2.2), if the logic end detects that the received fifo overflows, the logic end writes the data overflow bit, the subsequent data is not written again until the frame is over and is valid, and then the received fifo is rewritten.
7. A method of receiving data over a discrete interface as claimed in claim 1, wherein: in the step (2.2), the logic terminal receives the enable signal, and when the enable signal is invalid, the logic terminal does not receive the data of the bus.
8. A method of receiving data over a discrete interface as claimed in claim 1, wherein: in the step (2.3), the control register is used for receiving fifo empty, receiving start and receiving frame length registers, and the status register is used for performing end-of-frame marking and fifo half-empty marking.
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