CN111917752A - Communication interface conversion device - Google Patents
Communication interface conversion device Download PDFInfo
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- CN111917752A CN111917752A CN202010722470.4A CN202010722470A CN111917752A CN 111917752 A CN111917752 A CN 111917752A CN 202010722470 A CN202010722470 A CN 202010722470A CN 111917752 A CN111917752 A CN 111917752A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
- H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
Abstract
The invention provides a communication interface conversion device, which comprises: the first communication interface is used for receiving and transmitting first type data transmitted based on a first communication protocol; the first cache unit is used for storing data waiting for converting the data transmission format into a second data transmission format; the second communication interface is used for receiving and transmitting second type data transmitted based on a second communication protocol; a second buffer unit, configured to store data waiting for transmission by the second communication interface; a parameter configuration unit, configured to configure interface parameters of the first communication interface and/or the second communication interface; and the data processing unit is used for converting the first type data into the second type data and/or converting the second type data into the first type data. The invention can solve the problem of different transmission rates between different communication interfaces and improve the adaptability.
Description
Technical Field
The invention relates to the field of digital communication, in particular to a communication interface conversion device.
Background
In the present society, with the increase of the number of electronic devices, some electronic devices are equipped with a Microprocessor (MCU), and the MCU needs to exchange data through a hardware interface. And the data format, the transmission rate and the like of the data on the software level are different based on different hardware interfaces. For example, a Serial Peripheral Interface (SPI) Interface and an Integrated Circuit bus (I2C) Interface are two interfaces very suitable for communication between chips at a short distance and a low speed, and are widely used in the field of digital communication. However, since the data formats, transmission rates, and the like of the I2C and the SPI interfaces are different, it becomes very difficult to communicate between the MCU using the I2C interface and the MCU using the SPI interface. The conventional communication interface conversion device can complete the conversion of data formats between different interfaces, but cannot solve the problem of different transmission rates between different communication interfaces.
Therefore, it is desirable to provide a communication interface conversion apparatus to solve the above problems.
Disclosure of Invention
The embodiment of the invention provides a communication interface conversion device which can assist two devices with different communication interfaces to communicate, enables the data transmission of the communication interfaces with different data transmission rates to be complete and has high applicability.
A first aspect provides a communication interface conversion apparatus, which includes a first communication interface, a first cache unit, a second communication interface, a second cache unit, a parameter configuration unit, and a data processing unit, wherein:
the first communication interface is configured to receive and transmit first type data transmitted in a first data transmission format based on a first communication protocol.
The first buffer unit is used for storing data which is received by the first communication interface and waits for converting the data transmission format from the first data transmission format into the second data transmission format.
The second communication interface is configured to receive and transmit second type data transmitted in a second data transmission format based on a second communication protocol.
The second buffer unit is configured to store the data to be sent by the second communication interface after the first data transmission format is converted into the second data transmission format.
The parameter configuration unit is configured to configure interface parameters of the first communication interface and/or the second communication interface so as to complete data transmission and reception transmitted through the first communication interface and/or the second communication interface.
The data processing unit is configured to convert the first type data into the second type data and/or convert the second type data into the first type data.
In some possible embodiments, the first buffer unit and the second buffer unit include one or more first-in-first-out queues.
In some possible embodiments, the apparatus further includes a cache management unit: the cache management unit is configured to configure the first cache unit and/or the second cache unit to read and write data according to a preset priority.
In some possible embodiments, the parameter configuration unit includes a dial switch: the dial switch is used for configuring interface parameters of the first communication interface and/or the second communication interface, and ensuring complete receiving and transmitting of data transmitted through the first communication interface and/or the second communication interface.
In some possible embodiments, the apparatus further includes a data determining unit, wherein: the data judging unit is configured to judge whether the first type data and/or the second type data received through the first communication interface and/or the second communication interface based on the interface parameters configured by the parameter configuration unit are complete, and send a judgment result to the parameter configuration unit.
In some possible embodiments, the parameter configuration unit is further configured to: polling and configuring each interface parameter of the first communication interface and/or the second communication interface, and when the data judgment unit judges that the data received by the first communication interface and/or the second communication interface based on any interface parameter is complete within a preset time, setting the interface parameter of the first communication interface and/or the second communication interface as the any interface parameter.
In some possible embodiments, the parameter configuration unit further includes a force-reset key, and the force-reset key is configured to: and restarting the parameter configuration unit to enable the parameter configuration unit to start polling and configuring the interface parameters of the first communication interface and/or the second communication interface.
In some possible embodiments, the apparatus further includes a forced reset unit, and the forced reset unit is configured to: and when the data in the first buffer unit and/or the second buffer unit overflows, emptying the data in the first buffer unit and/or the second buffer unit and the data processing unit.
In some possible embodiments, the first communication interface is a Serial Peripheral Interface (SPI) interface, and the second communication interface is an integrated circuit bus I2C interface; or the first communication interface is an I2C interface, and the second communication interface is an SPI interface.
In some possible embodiments, the interface parameters include: at least one of data transmission bit number, data transmission rate, data check bit, data transmission size end and clock level change time of the communication interface.
In the embodiment of the invention, the interface parameters of the communication interface are configured to carry out data conversion, so that two devices with different communication interfaces can be assisted to carry out communication; due to the addition of the cache unit, the data transmission rates of different communication interfaces can be matched, and the applicability of the communication system is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a communication interface conversion apparatus according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating a communication interface conversion apparatus according to an embodiment of the present invention;
fig. 3 is another schematic structural diagram of a communication interface conversion apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The following are detailed below.
It should be understood that the terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
It should also be appreciated that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
The communication interface conversion device provided by the embodiment of the invention can be suitable for any communication interface and related equipment thereof. For example, when the first communication protocol is the same as the second communication protocol, the apparatus provided by the embodiment of the present invention may also be used for conversion due to different transmission parameters, such as different data transmission bits, data transmission rates, data check bits, data transmission size ends, and clock level change times of the communication interfaces. For convenience of description, the SPI and I2C interface conversion device may be exemplified by the first communication protocol being different from the second communication protocol. For convenience of description, the following embodiments will be described with devices replacing the communication interface conversion device.
Fig. 1 is a schematic structural diagram of a communication interface conversion apparatus according to an embodiment of the present invention. The communication interface conversion apparatus shown in the figure includes a first communication interface 101, a first cache unit 102, a second communication interface 103, a second cache unit 104, a parameter configuration unit 105, a data processing unit 106, and a cache management unit 107, wherein:
the first communication interface 101 is configured to receive and transmit first type data transmitted according to a first data transmission format of a first communication protocol.
In some possible embodiments, the first communication interface 101 may be an SPI interface, which is a high-speed, full-duplex, synchronous communication bus, and only four wires are occupied on the pins of the chip, thereby saving the pins of the chip, and providing convenience for the PCB layout. Generally, the SPI interface includes four pins, which are a Master Output/Slave Input (MOSI) pin, a Master Input/Slave Output (MISO) pin, a clock signal SCLK pin, and a Slave device enable signal CS pin. When the first communication interface 101 receives a signal from the CS pin of the SPI host, it indicates that the current device is selected by the SPI host, and can communicate with the SPI host to receive and transmit SPI data.
The first buffer unit 102 is used for storing data received by the first communication interface 101 and waiting for converting the data transmission format from the first data transmission format to the second data transmission format.
In some possible embodiments, the transmission rate of the SPI interface is faster than that of the I2C interface, which makes it impossible to convert all SPI data at the first time when the device receives the SPI data, so the present device provides a first buffer unit 102 for temporarily storing (buffering) the SPI data to be converted. Optionally, when all the data temporarily stored in the first buffer unit 102 are transferred to the data processing unit 106 for conversion, the first buffer unit 102 is automatically released.
The second communication interface 103 is configured to receive and transmit second type data transmitted in a second data transmission format based on a second communication protocol.
In some possible embodiments, the second communication interface 103 may be an I2C interface, and the I2C interface is a higher speed, simplex, multi-host bus including two pins, which is simple to control and small in device package. Typically the I2C interface includes two pins, a serial data pin SDA and a serial clock pin SCL. When the SCL pin in the second communication interface 102 is at a high level, the SDA pin transitions from high to low, and can communicate with an external I2C device to transmit and receive I2C data. When the SCL pin in the second communication interface 102 is at a high level and the SDA pin transitions from low to high, the communication with the external I2C device is stopped, and the transmission and reception of I2C data are stopped.
The second buffer unit 104 is configured to store the data to be transmitted by the second communication interface 103 after the first data transmission format is converted into the second data transmission format.
Since the data transmitted on the I2C interface is not limited by the number of bits, the length of the data sent to the SDA pin each time must be 8 bits, and the bus is released after the host sends 8 bits of data, the slave pulls down one clock of the SDA pin after receiving the data, and the acknowledge signal indicates that the data reception is successful.
In some possible embodiments, after the slave receives a byte of data and needs some time to process, the level of the SCL pin is pulled down to enable the data transmission to enter a waiting state, and after the processing is finished, the SCL pin is released to continue the transmission. Therefore, a second buffer unit 104 for temporarily buffering I2C data exists in the apparatus, and is used for temporarily storing I2C data to be transmitted. Alternatively, the data in the second buffer unit 104 is automatically released when the data is completely transmitted to the external data transmission device.
The parameter configuration unit 105 is configured to configure interface parameters of the first communication interface 101 and/or the second communication interface 103 so as to complete data transmission and reception through the first communication interface 101 and/or the second communication interface 103.
In some possible embodiments, the interface parameters include: at least one of data transmission bit number, data transmission rate, data check bit, data transmission size end and clock level change time of the communication interface.
In some possible embodiments, the number of bits of the transmission data can be configured to be 8 bits or 16 bits by the dial switch; configuring a transmission rate to be 18Mbps, 4.5Mbps or 1.125 Mbps; configuring a data check bit as a 7 th bit, an 8 th bit or a 10 th bit, and configuring a data transmission size as MSB before, LSB after or LSB before, MSB after; the change time of the clock level is configured to be slow, medium, or fast.
In some possible embodiments, the parameter configuration unit includes a dial switch: the dial switch is used for configuring interface parameters of the first communication interface and/or the second communication interface, and ensuring complete receiving and transmitting of data transmitted through the first communication interface and/or the second communication interface. For example, through dial switch's setting, the data transmission rate of configuration SPI communication interface is 18Mbps, and the clock level is quick, and then corresponding can accurate receive data transmission rate be 18Mbps, and the clock level is quick SPI data to guarantee the accuracy and the integrality of data.
The data processing unit 106 is configured to convert the first type data into the second type data and/or convert the second type data into the first type data.
In some possible embodiments, the first buffer unit 102 and the second buffer unit 104 include one or more first-in-first-out queues.
In some possible embodiments, the apparatus further includes a cache management unit 107: the cache management unit 107 is configured to configure the first cache unit 102 and/or the second cache unit 104 to read and write data according to a preset priority.
In some possible embodiments, the buffer management unit 107 configures the working order of the fifo queues in the first buffer unit 102 and the second buffer unit 104 according to a preset priority, so that the data read-write rate of the buffer unit matches the transmission rate of different communication interfaces. For example, the data receiving rate of the SPI interface with the faster transmission rate is used as the first priority, the data receiving rate of the I2C interface with the slower transmission rate is used as the second priority, the data sending rate of the I2C interface with the larger data transmission bit number is used as the third priority, the data sending rate of the SPI interface with the smaller data transmission bit number is used as the fourth priority, and the SPI and I2C data read/write are automatically performed according to the priorities, so that the data read/write rate of the cache unit is matched with the transmission rates of the SPI and I2C interfaces.
For convenience of description, the flow shown in fig. 2 is taken as an example, and the device is taken as an execution subject to illustrate the working principle:
the interface parameters of the first communication interface 101 and/or the second communication interface 103 are configured by the parameter configuration unit 105.
In some possible embodiments, the dial switch may be set 0/1 according to the interface parameters of the external SPI data transceiving device and the I2C data transceiving device. For example, through reading dial switch's setting, the data transmission rate of configuration SPI communication interface is 18Mbps, and the clock level is quick, and then corresponding can accurate receive data transmission rate be 18Mbps, and the clock level is quick SPI data to guarantee the accuracy and the integrality of data.
The first type data transmitted by the first communication interface 101 based on the first data transmission format of the first communication protocol is obtained.
In some possible embodiments, when the first communication interface 101 receives a signal from the CS pin of the SPI host, it indicates that the device is currently selected by the SPI host, and can communicate with the SPI host to send and receive SPI data.
The received data in the first data transmission format is stored in the first buffer unit 102.
In some possible embodiments, the transmission rate of the SPI interface is faster than that of the I2C interface, which makes it impossible to convert all SPI data at the first time when the device receives the SPI data, so the present device provides a first buffer unit 102 for temporarily storing (buffering) the SPI data to be converted. Optionally, when all the data temporarily stored in the first buffer unit 102 are transferred to the data processing unit 106 for conversion, the first buffer unit 102 is automatically released.
The data processing unit 106 converts the data in the first buffer unit 102 into data in a second data transmission format.
The data in the second data transmission format obtained by the conversion is stored in the second buffer unit 104.
Since the data transmitted on the I2C interface is not limited by the number of bits, the length of the data sent to the SDA pin each time must be 8 bits, and the bus is released after the host sends 8 bits of data, the slave pulls down one clock of the SDA pin after receiving the data, and the acknowledge signal indicates that the data reception is successful.
In some possible embodiments, after the slave receives a byte of data and needs some time to process, the level of the SCL pin is pulled down to enable the data transmission to enter a waiting state, and after the processing is finished, the SCL pin is released to continue the transmission. Therefore, a second buffer unit for temporarily buffering the I2C data exists in the apparatus, and is used for temporarily storing the I2C data to be transmitted. Alternatively, the second buffer unit 104 is automatically released when the data is completely transmitted to the external data transmission device.
In some possible embodiments, the buffer management unit 107 configures the working order of the fifo queues in the first buffer unit 102 and the second buffer unit 104 according to a preset priority, so that the data read-write rate of the buffer unit matches the transmission rate of different communication interfaces. For example, the data receiving rate of the SPI interface with the faster transmission rate is used as the first priority, the data receiving rate of the I2C interface with the slower transmission rate is used as the second priority, the data sending rate of the I2C interface with the larger data transmission bit number is used as the third priority, the data sending rate of the SPI interface with the smaller data transmission bit number is used as the fourth priority, and the SPI and I2C data read/write are automatically performed according to the priorities, so that the data read/write rate of the cache unit is matched with the transmission rates of the SPI and I2C interfaces.
The data in the second buffer unit 104 is sent out through the second communication interface 103.
In the embodiment of the invention, the interface parameters of the communication interface are configured to carry out data conversion, so that two devices with different communication interfaces can be assisted to carry out communication in different working modes; due to the addition of the cache unit, the data read-write speed of the cache unit can be matched with the transmission speed of different communication interfaces, and the applicability of the communication system is improved.
Fig. 3 is a schematic structural diagram of a communication interface conversion apparatus according to another embodiment of the present invention. The communication interface conversion apparatus shown in the figure includes a first communication interface 201, a first buffer unit 202, a second communication interface 203, a second buffer unit 204, a parameter configuration unit 205, a data processing unit 206, a data determination unit 207, a forced reset unit 208, and a buffer management unit 209, wherein:
the first communication interface 201 is configured to receive and transmit first type data transmitted according to a first data transmission format of a first communication protocol.
In some possible embodiments, the first communication interface 201 may be an SPI interface, which is a high-speed, full-duplex, synchronous communication bus, and only four wires are occupied on the pins of the chip, thereby saving the pins of the chip, and providing convenience for the PCB layout. The SPI interface typically includes four pins, which are the MOSI pin, the MISO pin, the clock signal SCLK pin, and the slave enable signal CS pin. When the first communication interface 201 receives a signal from the CS pin of the SPI host, it indicates that the current device is selected by the SPI host, and can communicate with the SPI host to receive and transmit SPI data.
The first buffer unit 202 is used for storing data received by the first communication interface 201 and waiting for converting the data transmission format from the first data transmission format to the second data transmission format.
In some possible embodiments, the transmission rate of the SPI interface is faster than that of the I2C interface, which makes it impossible to convert all SPI data at the first time when the device receives the SPI data, so the present device provides a first buffer unit 202 for temporarily storing (buffering) the SPI data to be converted. Optionally, when all the data temporarily stored in the first buffer unit 202 is transferred to the data processing unit 206 for conversion, the first buffer unit 202 is automatically released.
The second communication interface 203 is configured to receive and transmit second type data transmitted in a second data transmission format based on a second communication protocol.
In some possible embodiments, the second communication interface 203 may be an I2C interface, and the I2C interface is a higher speed, simplex, multi-host bus including two pins, which is simple to control and small in device package. Typically the I2C interface includes two pins, a serial data pin SDA and a serial clock pin SCL.
When the SCL pin in the second communication interface 202 is at a high level, the SDA pin transitions from high to low, and can communicate with an external I2C device to send and receive I2C data. When the SCL pin in the second communication interface 202 is at a high level and the SDA pin transitions from low to high, the communication with the external I2C device is stopped, and the transmission and reception of I2C data are stopped.
The second buffer unit 204 is configured to store the data to be transmitted by the second communication interface after the first data transmission format of the first communication protocol is converted into the second data transmission format.
Since the data transmitted on the I2C interface is not limited by the number of bits, the length of the data sent to the SDA pin each time must be 8 bits, and the bus is released after the host sends 8 bits of data, the slave pulls down one clock of the SDA pin after receiving the data, and the acknowledge signal indicates that the data reception is successful.
In some possible embodiments, after the slave receives a byte of data and needs some time to process, the level of the SCL pin is pulled down to enable the data transmission to enter a waiting state, and after the processing is finished, the SCL pin is released to continue the transmission. Therefore, a second buffer unit 204 for temporarily buffering I2C data exists in the apparatus, and is used for temporarily storing I2C data to be transmitted. Alternatively, the data in the second buffer unit 204 may be automatically released when the data is completely transmitted to the external data transmission device.
The parameter configuration unit 205 is configured to configure interface parameters of the first communication interface 201 and/or the second communication interface 203, so as to ensure that the data transmitted through the first communication interface 201 and/or the second communication interface 203 is completely received and transmitted.
In some possible embodiments, the interface parameters include: at least one of data transmission bit number, data transmission rate, data check bit, data transmission size end and clock level change time of the communication interface.
In some possible embodiments, the apparatus further includes a data determining unit 207, wherein: the data determining unit 207 is configured to determine whether the first type data and/or the second type data received through the first communication interface 201 and/or the second communication interface 203 are complete, and send the result to the parameter configuring unit 205.
In some possible embodiments, the parameter configuration unit 205 is further configured to: polling the interface parameters of the first communication interface 201 and/or the second communication interface 203, and when the data determining unit determines that the data received by the first communication interface 201 and/or the second communication interface 203 based on any interface parameter is complete within a preset time, setting the interface parameters of the first communication interface 201 and/or the second communication interface 203 as any interface parameter.
In some possible embodiments, the setting of the dial switch cannot be directly performed according to the interface parameters of the external SPI data transceiver and the I2C data transceiver. The parameter configuration unit 205 may switch to the adaptive mode, sequentially try to configure all the selectable interface parameters, and receive data through the communication interface for a period of time (e.g., 2 seconds), and perform integrity detection on the received data through the data determination unit 207. For example, when the data transmission rate of the SPI communication interface is configured to be 18Mbps and the clock level is fast, the data determining unit 207 determines that the received data is complete by verifying the header of the received data, that is, the device is adjusted to be in the current mode, so that the received data transmission rate is 18Mbps and the clock level is fast SPI data.
In some possible embodiments, the parameter configuration unit 205 further includes a reset key, which enables the parameter configuration unit 205 to restart the adaptive mode for parameter configuration.
The data processing unit 206 is configured to convert the first type data into the second type data and/or convert the second type data into the first type data.
In some possible embodiments, the apparatus further includes a forced reset unit 208, and the forced reset unit 208 is configured to: when the data in the first buffer unit 202 and/or the second buffer unit 204 overflows, the data in the first buffer unit and/or the second buffer unit and the data processing unit are emptied, and the device is forcibly reset.
In some possible embodiments, the buffer management unit 209 configures the working order of the fifo queues in the first buffer unit 102 and the second buffer unit 104 according to a preset priority, so that the data read-write rate of the buffer unit matches the transmission rate of different communication interfaces. For example, the data receiving rate of the SPI interface with the faster transmission rate is used as the first priority, the data receiving rate of the I2C interface with the slower transmission rate is used as the second priority, the data sending rate of the I2C interface with the larger data transmission bit number is used as the third priority, the data sending rate of the SPI interface with the smaller data transmission bit number is used as the fourth priority, and the SPI and I2C data read/write are automatically performed according to the priorities, so that the data read/write rate of the cache unit is matched with the transmission rates of the SPI and I2C interfaces.
In the embodiment of the invention, the interface parameters of the communication interface are automatically configured to carry out data conversion, so that different external equipment of the communication interface with unknown interface parameters can be assisted to carry out communication, and the adaptability of the device is further improved. By configuring the forced reset unit 208, the device can be reset when the data in the buffer unit overflows, the device is prevented from being stuck or wrong due to the data overflow in the data conversion process, and the accuracy of the device is improved.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the terminal device and the unit described above may refer to corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed terminal device and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the above-described division of units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A communication interface conversion device is characterized in that the device comprises a first communication interface, a first cache unit, a second communication interface, a second cache unit, a parameter configuration unit and a data processing unit, wherein:
the first communication interface is used for receiving and transmitting first type data transmitted by a first data transmission format based on a first communication protocol;
the first buffer unit is used for storing data which is received by the first communication interface and waits for converting the data transmission format from the first data transmission format into the second data transmission format;
the second communication interface is used for receiving and transmitting second type data transmitted by a second data transmission format based on a second communication protocol;
the second cache unit is configured to store the data to be sent by the second communication interface after the first data transmission format is converted into the second data transmission format;
the parameter configuration unit is used for configuring interface parameters of the first communication interface and/or the second communication interface so as to enable data transmitted through the first communication interface and/or the second communication interface to be completely received and transmitted;
the data processing unit is configured to convert the first type of data into the second type of data, and/or convert the second type of data into the first type of data.
2. The communication interface conversion apparatus according to claim 1, further comprising a cache management unit:
the cache management unit is used for configuring the first cache unit and/or the second cache unit to read and write data according to a preset priority.
3. The communication interface conversion apparatus of claim 1, wherein the parameter configuration unit comprises a dial switch:
the dial switch is used for configuring interface parameters of the first communication interface and/or the second communication interface so as to enable the data transmission and receiving through the first communication interface and/or the second communication interface to be complete.
4. The communication interface converting apparatus according to claim 1, further comprising a data judging unit, wherein:
the data judging unit is used for judging whether the first type data and/or the second type data received by the first communication interface and/or the second communication interface based on the interface parameters configured by the parameter configuration unit are complete or not, and sending the judgment result to the parameter configuration unit.
5. The communication interface conversion apparatus according to claim 4, wherein the parameter configuration unit is further configured to:
and polling and configuring each interface parameter of the first communication interface and/or the second communication interface, and when the data judgment unit judges that the data received by the first communication interface and/or the second communication interface based on any interface parameter is complete in a preset time, setting the interface parameter of the first communication interface and/or the second communication interface as the any interface parameter.
6. The communication interface conversion apparatus of claim 5, wherein the parameter configuration unit further comprises a force reset key, the force reset key being configured to: and restarting the parameter configuration unit to enable the parameter configuration unit to start polling and configuring the interface parameters of the first communication interface and/or the second communication interface.
7. The communication interface conversion apparatus according to any one of claims 1 to 6, wherein the first buffer unit and the second buffer unit comprise one or more first-in-first-out queues.
8. The communication interface conversion apparatus according to any one of claims 1 to 7, further comprising a forced reset unit for:
and detecting the running state of the first cache unit and/or the second cache unit, and emptying the data in the first cache unit and/or the second cache unit and the data processing unit when the data in the first cache unit and/or the second cache unit overflow.
9. The communication interface conversion apparatus according to any one of claims 1 to 8, wherein the first communication interface is a Serial Peripheral Interface (SPI) interface, and the second communication interface is an integrated circuit bus (I2C) interface; or the first communication interface is an I2C interface, and the second communication interface is an SPI interface.
10. The communication interface conversion apparatus according to any one of claims 1 to 9, wherein the interface parameter includes at least one of a data transfer bit number, a data transfer rate, a data check bit, a data transfer size end, and a clock level change time of the communication interface.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114221699A (en) * | 2021-12-16 | 2022-03-22 | 黄冈师范学院 | Dial display method for communication information rate detection |
| CN117558241A (en) * | 2023-12-19 | 2024-02-13 | 北京显芯科技有限公司 | Backlight circuit and backlight system |
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2020
- 2020-07-24 CN CN202010722470.4A patent/CN111917752A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114221699A (en) * | 2021-12-16 | 2022-03-22 | 黄冈师范学院 | Dial display method for communication information rate detection |
| CN117558241A (en) * | 2023-12-19 | 2024-02-13 | 北京显芯科技有限公司 | Backlight circuit and backlight system |
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