CN116192624A

CN116192624A - Communication interface configuration method and communication interface

Info

Publication number: CN116192624A
Application number: CN202310027879.8A
Authority: CN
Inventors: 刘欣宇
Original assignee: Hangzhou Vango Technologies Inc
Current assignee: Hangzhou Vango Technologies Inc
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2023-05-30

Abstract

The embodiment of the invention discloses a configuration method of a communication interface and the communication interface. The configuration method of the communication interface comprises the following steps: the CSB signal of the communication interface is configured to be an active low signal so that the MCU reads and writes the register; the FCSB signal of the communication interface is configured to be an active-low signal so that the MCU can read and write the FIFO; the MOSI pin and the MISO pin of the communication interface are combined into a safe digital input/output port, so that the MCU and the wireless transceiver chip can perform data transmission. The scheme provided by the invention can realize the selection and switching of the RF mode and the FIFO mode through the configuration of the MCU to the register, replaces a communication mode of transmitting command type, and reduces the technical effects of decoding work and internal state reaction time of the wireless transceiver chip.

Description

Communication interface configuration method and communication interface

Technical Field

The present invention relates to the field of chip technology application, and in particular, to a method for configuring a communication interface and a communication interface.

Background

With the continuous development of the communication field, the application of the wireless transceiver chip in daily life is becoming wider and wider. The industry typically uses a variety of interface protocols to implement control of the micro control unit (Microcontroller Unit; MCU for short) to the wireless transceiver chip. The serial peripheral interface (Serial Peripheral Interface, abbreviated as SPI) is a common interface protocol between many MCUs and wireless transceiver chips due to its high speed, full duplex, and synchronous nature. The SPI can enable the MCU to realize configuration of various parameters and functions of the wireless transceiver chip, so that application of communication occasions is realized.

The SPI interface generally uses four wires: MOSI (master data out, slave data in, master Input Slave Output), MISO (master data in, slave data out, master Output Slave Input), SCLK (Clock signal generated by master), chip Select signal CSB (slave Chip Select signal, issued by master, low order 0 indicates valid, chip Select).

When the existing MCU performs register configuration or FIFO read-write on the wireless transceiver chip, the host computer must send an instruction corresponding to the operation, and the slave computer side can transmit data only after decoding the instruction. The complexity of the wireless transceiver chip is increased by the implementation of the decoding function, and the decoding and the switching of the internal states of the wireless transceiver chip take a certain time, so that the efficiency of data transmission is reduced. Meanwhile, the switching between the read-write slave register and the FIFO can be realized only by changing the type of the instruction to be sent on the host side, and the switching mode of the read-write slave register and the FIFO is not flexible enough. In addition, the SPI interfacing method does not support continuous reading and writing of the register or FIFO, and if a 32-bit register is to be read and written, 4 times of 8-bit data transmission or 2 times of 16-bit data transmission are required, which is not efficient.

Aiming at the problem of low data transmission efficiency caused by excessively high time consumption in the process of decoding and reading and writing when the MCU carries out register configuration or FIFO reading and writing on the wireless transceiver chip in the prior art, no effective solution is proposed at present.

Disclosure of Invention

In order to solve the above technical problems, it is desirable to provide a configuration method of a communication interface and a communication interface, so as to at least solve the problem of low data transmission efficiency caused by too high time consumption in the process of decoding and reading and writing when an MCU configures a register or reads and writes a FIFO on a wireless transceiver chip in the prior art.

The technical scheme of the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides a communication interface, including: the communication interface is connected with the wireless transceiver chip through an MOSI pin, a MISO pin, an SCLK pin and an NSS pin, wherein the MISO pin is a master device input/slave device output pin and is used for transmitting data in a slave mode and receiving data in the master mode; the MOSI pin is a master device output/slave device input pin and is used for transmitting data in a master mode and receiving data in a slave mode; the SCLK pin is a serial clock and is used for outputting the master device and inputting the slave device; the NSS pin is a main device or a slave device selection pin and is used for performing chip selection on a register of the wireless transceiver chip by setting NSS [0] as a CSB signal and performing chip selection on a FIFO of the wireless transceiver chip by setting NSS [1] as an FCSB signal; wherein one side generating the clock is called a master device, and the other side is called a slave device; the communication interface is in a single-wire bidirectional mode, and the MOSI pin and the MISO pin are combined into a safe digital input/output port.

Optionally, the communication interface further includes: a transmission buffer, a shift register, an STS register, and a first CTRL register, wherein the transmission buffer is used for writing data into the transmission buffer in a write operation; when the slave device receives a clock signal and a first data bit appears on the MOSI pin, starting a data transmission process, and storing the rest digital bits in a data frame format into a shift register; when the data in the sending buffer is transmitted to the shift register, setting the TE flag of the SPI_STS register; if the TEIE bit of the first CTRL register is set, an interrupt is generated.

Further, optionally, the communication interface further includes: a reception buffer for transmitting data in the shift register to the reception buffer when the data reception is completed, setting an RNE flag in the STS register; if the RNEIE bit in the first CTRL register is set, generating an interrupt; after the last sampling clock edge, setting the RNE bit to 1, and transmitting the data bytes received in the shift register to a receiving buffer; when the DT register is read, the communication interface returns the value of the receive buffer and clears the RNE bit.

Optionally, an rf_en bit and a fifo_mode bit are added in the first CTRL register, where the rf_en bit is used for the MCU to configure the communication interface to start a read-write register MODE for the wireless transceiver chip; and the FIFO_MODE bit is used for the MCU to configure the communication interface to start a read-write FIFO MODE of the wireless transceiver chip.

Further, optionally, the communication interface further includes: a main control circuit, wherein an NSS_SEL bit is added in the first CTRL register for enabling NSS [0] and NSS [1] in the main control circuit; when NSS_SEL bit is set to 0, NSS [0] is valid, NSS [0] is used as CSB signal to select register chip in wireless transceiver chip; when NSS_SLE bit is set to 1, NSS [1] is active, NSS [1] is used as FCSB signal to select register chip in wireless transceiver chip.

Optionally, the main control circuit includes: and the timer takes the bus clock as a reference clock, wherein the timer is used for starting counting when the CSB signal is pulled down in a read-write register mode, and when the timer reaches a counting threshold value, a first enabling signal is sent to start data transmission.

Further optionally, when the main control circuit detects that the data is transmitted to the preset data, a timer is started, and when the timer reaches the counting threshold value at regular time, a second enabling signal is generated, and the CSB signal is pulled up.

Optionally, the communication interface further includes: a delay counter; the first CTRL register is further added with a TIM_CYCLE bit for configuring delay time; the delay counter is used for counting from the falling edge of the last SCLK, and when the delay counter counts to delay time, the FCSB signal is pulled up; when the delay counter counts to a preset multiple of the delay time, if data are transmitted, the FCSB signal is pulled down; if no data is being transmitted, the FCSB signal is held high.

Optionally, the communication interface further includes: and the second CTRL register is used for detecting the address 0 sent by the MCU after the communication interface is configured into a read register mode and switching the level signal of the BDOE bit in the second CTRL register before the falling edge of SCLK so as to switch the IO port from output to input.

In a second aspect, an embodiment of the present invention provides a method for configuring a communication interface, which is applied to the communication interface, including: the CSB signal of the communication interface is configured to be an active low signal so that the MCU reads and writes the register; the FCSB signal of the communication interface is configured to be an active-low signal so that the MCU can read and write the FIFO; the MOSI pin and the MISO pin of the communication interface are combined into a safe digital input/output port, so that the MCU and the wireless transceiver chip can perform data transmission.

Optionally, the method further comprises: configuring a communication interface into a single-wire bidirectional mode, and setting a baud rate and a data frame format; wherein configuring the communication interface to be in a single-wire bidirectional mode, and setting the baud rate and the data frame format comprises: determining a serial clock baud rate by the MCLKP bit of the second CTRL register; and determining a phase relation between data transmission and a serial clock by configuring CPOL and CPHA bits of the second CTRL register to be 0, wherein the phase relation is as follows: transmitting data at the falling edge of the serial clock, and sampling the data at the rising edge of the serial clock; determining a data frame format as 8 bits or 16 bits by configuring DFF16 bits of the second CTRL register; determining the data frame format as the most significant bit MSB transmitted or received first by configuring the LSBEN bit of the second CTRL register to be 0; if the CSB pin is determined to work in an input mode, in a hardware mode, during data frame transmission, a level signal of the CSB pin is configured to be a high level signal; in software mode, the SWNSSEN bit and ISS bit of the second CTRL register are configured; if the CSB pin is operating in output mode, configuring NSSOE bit of the first CTRL register; by configuring the BDMODE bit of the second CTRL register, the communication interface enables a single-wire bidirectional mode, wherein the SCLK pin is used as a clock, the master device uses the MOSI pin, and the slave device uses the MISO pin for data communication; the transmission direction is controlled by the BDOE bit in the second CTRL register, and when the BDOE bit is 1, data is output; when the BDOE bit is 0, data input; through configuring DT register, writing in address of read-write wireless transceiver chip; and configuring the communication interface as a master device by setting the MSTEN bit of the second CTRL register.

Optionally, the method further comprises: configuring a communication interface into a read-write wireless receiving-transmitting register mode; wherein, the configuration of the communication interface as a read-write wireless receiving and transmitting register mode comprises: selecting the CSB signal as the chip select signal by configuring the NSS_SEL bit in the first CTRL register to be 0; by configuring the RF_EN bit in the first CTRL register to be 1, starting a read-write wireless receiving and transmitting register mode; the communication interface is enabled by configuring the EN bit in the second CTRL register to be 1.

Optionally, configuring the FCSB signal of the communication interface to be an active-low signal to enable the MCU to read and write the FIFO includes: selecting the FCSB as a chip select signal by configuring the nss_sel bit in the first CTRL register to be 1; determining delay time between continuous read-write operations in the FIFO mode by configuring TIM_CYCLE bits in the first CTRL register; starting the FIFO MODE by configuring the FIFO_MODE bit in the first CTRL register to be 1; the communication interface is enabled by configuring the SPI_EN bit in the second CTRL register to be 1.

The embodiment of the invention provides a configuration method of a communication interface and the communication interface. The CSB signal of the communication interface is configured to be an active low signal so that the MCU reads and writes the register; the FCSB signal of the communication interface is configured to be an active-low signal so that the MCU can read and write the FIFO; the MOSI pin and the MISO pin of the communication interface are configured to be combined into a safe digital input/output port, so that the MCU and the wireless transceiver chip perform data transmission, the selection and switching of an RF mode and a FIFO mode can be realized through the configuration of the MCU to a register, the communication mode of a sending command is replaced, and the technical effects of decoding work and internal state reaction time of the wireless transceiver chip are reduced.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

fig. 1 is a schematic diagram of a communication interface according to a first embodiment of the present invention;

fig. 2 is a flow chart of a configuration method of a communication interface according to a second embodiment of the present invention;

fig. 3 is a schematic diagram of an SPI read register timing sequence in a configuration method of a communication interface according to a second embodiment of the present invention;

fig. 4 is a schematic diagram of an SPI write register timing sequence in a configuration method of a communication interface according to a second embodiment of the present invention;

fig. 5 is a schematic diagram of an SPI read FIFO timing sequence in a configuration method of a communication interface according to a second embodiment of the present invention;

fig. 6 is a schematic diagram of an SPI write FIFO timing sequence in a configuration method of a communication interface according to a second embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and in the drawings are used for distinguishing between different objects and not for limiting a particular order.

It should be noted that, the following embodiments of the present invention may be implemented separately or in combination with each other, and the embodiments of the present invention are not limited thereto.

Technical terms related to the embodiments of the present application:

and a micro control unit: microcontroller Unit; MCU for short;

serial peripheral interface: serial Peripheral Interface, SPI for short;

MOSI: master data output, slave data input, master Input Slave Output;

MISO: master data input, slave data output, master Output Slave Input;

SCLK: a Clock signal generated by the master device, a Serial Clock;

chip select signal CSB: a slave chip select signal sent by the master, with low (active low) 0 indicating active, chip Select Below;

SDIO: secure Digital Input and Output, secure digital input and output;

MSB: most significant bit, most Significant Bit;

RF: radio Frequency.

Example 1

In a first aspect, an embodiment of the present invention provides a communication interface, and fig. 1 is a schematic diagram of a communication interface provided in a first embodiment of the present invention; as shown in fig. 1, a communication interface provided in an embodiment of the present application includes:

the communication interface is connected with the wireless transceiver chip through an MOSI pin, a MISO pin, an SCLK pin and an NSS pin, wherein the MISO pin is a master device input/slave device output pin and is used for transmitting data in a slave mode and receiving data in the master mode; the MOSI pin is a master device output/slave device input pin and is used for transmitting data in a master mode and receiving data in a slave mode; the SCLK pin is a serial clock and is used for outputting the master device and inputting the slave device; the NSS pin is a main device or a slave device selection pin and is used for performing chip selection on a register of the wireless transceiver chip by setting NSS [0] as a CSB signal and performing chip selection on a FIFO of the wireless transceiver chip by setting NSS [1] as an FCSB signal; wherein one side generating the clock is called a master device, and the other side is called a slave device; the communication interface is in a single-wire bidirectional mode, and the MOSI pin and the MISO pin are combined into a safe digital input/output port.

Specifically, in a preferred implementation scheme, the communication interface provided in the embodiment of the present application may be a serial peripheral interface (denoted as SPI), and in order to implement control of the MCU on the CMT2300A (i.e., the wireless transceiver chip in the embodiment of the present application), the communication interface may operate on a chip with an ARM Cortex-M series as a core. It should be noted that, the wireless transceiver chip provided in the embodiment of the present application is described by taking the CMT2300A as an example, and the implementation of a communication interface provided in the embodiment of the present application is not limited specifically.

As shown in fig. 1, MISO pin: master input/slave output pins. The MISO pin transmits data in the slave mode and receives data in the master mode.

MOSI pins for master output/slave input pins. The MOSI pin transmits data in a master mode and receives data in a slave mode.

The SCLK pin is used for serial port clock as output of the master device and input of the slave device.

NSS pin for slave device selection. This is an optional pin for selecting master/slave devices. The function of the device is to be used as a chip selection pin, so that the master device can independently communicate with a specific slave device, and the conflict on a data line is avoided. Wherein NSS [0] and NSS [1] are respectively used as CSB signal and FCSB signal to perform chip selection on the register or FIFO of the wireless transceiver chip.

Since the SPI is configured in a single-wire bi-directional mode when the MCU communicates with the wireless transceiver chip, the MISO and MOSI are both input and output at this time, and are combined into the same port SDIO (i.e., the secure digital input output port in the embodiment of the present application).

Based on the above, the communication interface provided in the embodiment of the application is configured in a single-wire bidirectional communication mode, and only one data line of the SDIO is used for transmission, so that data transmission is more visual.

Optionally, the communication interface provided in the embodiment of the present application further includes: a transmission buffer, a shift register, an STS register, and a first CTRL register, wherein the transmission buffer is used for writing data into the transmission buffer in a write operation; when the slave device receives a clock signal and a first data bit appears on the MOSI pin, starting a data transmission process, and storing the rest digital bits in a data frame format into a shift register; setting a TE flag of an STS register when data in a transmission buffer is transferred to the shift register; if the TEIE bit of the first CTRL register is set, an interrupt is generated.

Specifically, as shown in fig. 1, in the data transmission process, data is written into a transmission buffer in a write operation. The transmission process begins when a clock signal is received from the device and the first data bit appears on the MOSI pin (where the first bit is transmitted at this time). The remaining bits (7 bits for an 8 bit data frame format and 15 bits for a 16 bit data frame format) are loaded into the shift register. When data in the transmit buffer is transferred to the shift register, the TE flag of the SPI_STS register (i.e., STS register in the present embodiment) is set, and if the TEIE bit of the SPI_CTRL2 register (i.e., first CTRL register in the present embodiment) is set, an interrupt will be generated.

Further, optionally, the communication interface provided in the embodiment of the present application further includes: a reception buffer for transmitting data in the shift register to the reception buffer when the data reception is completed, setting an RNE flag in the STS register; if the RNEIE bit in the first CTRL register is set, generating an interrupt; after the last sampling clock edge, setting the RNE bit to 1, and transmitting the data bytes received in the shift register to a receiving buffer; when the DT register is read, the communication interface returns the value of the receive buffer and clears the RNE bit.

Specifically, as shown in fig. 1, in the data receiving process: when the data reception is completed: the data in the shift register is transferred to the receive buffer and the RNE flag in the spi_sts register is set. If the RNEIE bit in the SPI_CTRL2 register is set, an interrupt is generated. After the last sampling clock edge, the RNE bit is set to '1' and the data byte received in the shift register is transferred to the receive buffer. When the spi_dt register (i.e., DT register in the embodiments of the present application) is read, the SPI device returns the value of this receive buffer. The RNE bit is cleared when the spi_dt register is read.

Specifically, as shown in fig. 1, in the case where the wireless transceiver chip is a CMT2300A chip, special improvements are made to the CMT2300A chip, SPI: in order to replace the technology of the MCU sending command to switch the SPI transmission MODE, the CTRL2 register is added with rf_en and fifo_mode bits, which are used for the MCU to configure the SPI to turn on the read/write register MODE (RF MODE) and read/write FIFO MODE for CMT2300A, respectively.

Based on the above, the communication interface provided in the embodiment of the present application may implement selection and switching of the RF mode and the FIFO mode through the configuration of the MCU to the register, instead of the communication mode of transmitting the command, and reduce the decoding work and the internal state reaction time of the wireless transceiver chip.

Further, optionally, the communication interface provided in the embodiment of the present application further includes: a main control circuit, wherein an NSS_SEL bit is added in the first CTRL register for enabling NSS [0] and NSS [1] in the main control circuit; when NSS_SEL bit is set to 0, NSS [0] is valid, NSS [0] is used as CSB signal to select register chip in wireless transceiver chip; when NSS_SLE bit is set to 1, NSS [1] is active, NSS [1] is used as FCSB signal to select register chip in wireless transceiver chip.

Specifically, as shown in fig. 1, in the case where the wireless transceiver chip is a CMT2300A chip, special improvements are made to the CMT2300A chip, SPI: the SPI_CTRL2 register has the NSS_SEL bit added to enable NSS [0] and NSS [1] in the main control circuit. When NSS_SEL is set to 0, NSS [0] is active, and NSS [0] at this time is selected as a CSB signal for a register chip in CMT 2300A. When NSS_SLE is set to 1 and NSS [1] is active, NSS [1] at this time selects a register chip in CMT2300A as the FCSB signal.

Based on the above, the communication interface provided in the embodiment of the present application uses CSB and FCSB to perform the differentiated switching between the register read-write and FIFO read-write, which is very flexible.

Specifically, as shown in fig. 1, in the case where the wireless transceiver chip is a CMT2300A chip, special improvements are made to the CMT2300A chip, SPI:

in order to meet the timing requirements of the CMT2300A chip at the beginning and end of data transmission (the read/write register requires 0.5SCLK cycle, the read/write FIFO requires 1SCLK cycle), a dedicated timer (i.e., a timer with the bus clock as the reference clock in the embodiment of the present application) with the bus clock as the reference clock is designed in the main control circuit, and in the read/write register mode, the timer starts counting when CSB is pulled down, and the count threshold is set in advance to be greater than half the baud rate value (SCLK is the clock obtained by dividing the bus clock according to the baud rate).

When the timer reaches the counting threshold, an enabling signal (i.e., the first enabling signal in the embodiment of the application) is sent to start data transmission, so that the time sequence requirement that the waiting time of data transmission is greater than 0.5SCLK cycle after the MCU pulls down the CSB can be achieved. Similarly, after detecting that data is transmitted to data 7 (8 bit transmission)/data 15 (16 bit transmission) (i.e., preset data in the embodiment of the present application), the master control circuit starts a dedicated timer, and generates an enable signal (i.e., a second enable signal in the embodiment of the present application) after the timer reaches the count threshold at regular time, so that CSB is pulled high.

Optionally, the communication interface provided in the embodiment of the present application further includes: a delay counter; the first CTRL register is further added with a TIM_CYCLE bit for configuring delay time; the delay counter is used for counting from the falling edge of the last SCLK, and when the delay counter counts to delay time, the FCSB signal is pulled up; when the delay counter counts to a preset multiple of the delay time, if data are transmitted, the FCSB signal is pulled down; if no data is being transmitted, the FCSB signal is held high.

since the internal state time of the CMT2300A in FIFO mode requires a certain time to switch, the MCU pulls FCSB high after sending out the falling edge of the last SCLK for at least 2 us. And between two consecutive read and write operations, the FCSB must be pulled up by at least 4us. To achieve this function, a timcycle bit is added to the spi_ctrl2 register to configure the delay time. Inside the SPI is a special delay counter (i.e., delay counter in the embodiments of the present application). The delay counter counts from the falling edge of the last SCLK in half a clock cycle of SCLK. The delay calculation formula is as follows:

After the Delay counter counts to the Delay defined time (i.e., the Delay time in the embodiment of the present application), the FCSB is pulled high. To satisfy the FCSB pull-up time greater than 4us, a determination is made after the Delay counter counts to Delay 3 (i.e., a preset multiple of the Delay time in the embodiment of the present application) according to whether the next data transmission is performed, if so, the FCSB is pulled down, otherwise, the FCSB remains high.

Based on the above, the communication interface provided by the embodiment of the application can realize continuous data receiving and transmitting, so that the complexity caused by repeated configuration of repeated single data transmission and a large amount of delay caused by repeated transmission are avoided.

Optionally, the communication interface provided in the embodiment of the present application further includes: and the second CTRL register is used for detecting the address 0 sent by the MCU after the communication interface is configured into a read register mode and switching the level signal of the BDOE bit in the second CTRL register before the falling edge of SCLK so as to switch the IO port from output to input.

An address 0 bit detection mechanism in a read register mode is designed in a main control circuit of the SPI, when the SPI is configured into the read register mode, the address 0 sent by the MCU is detected, and before the falling edge of SCLK, BDOE bits in CTRL1 (namely a second CTRL register in the embodiment of the application) are switched from 1 to 0 so as to switch an IO port from output to input.

The embodiment of the invention provides a communication interface. The MISO pin is a master device input/slave device output pin and is used for transmitting data in a slave mode and receiving data in the master mode; the MOSI pin is a master device output/slave device input pin and is used for transmitting data in a master mode and receiving data in a slave mode; the SCLK pin is a serial clock and is used for outputting the master device and inputting the slave device; the NSS pin is a main device or a slave device selection pin and is used for performing chip selection on a register of the wireless transceiver chip by setting NSS [0] as a CSB signal and performing chip selection on a FIFO of the wireless transceiver chip by setting NSS [1] as an FCSB signal; wherein one side generating the clock is called a master device, and the other side is called a slave device; the communication interface is in a single-wire bidirectional mode, and the MOSI pin and the MISO pin are combined into a safe digital input/output port, so that the selection and switching of an RF mode and a FIFO mode can be realized through the configuration of an MCU to a register, the communication mode of a sending command type is replaced, and the technical effects of the decoding work and the internal state reaction time of a wireless transceiver chip are reduced.

Example two

In a second aspect, an embodiment of the present invention provides a method for configuring a communication interface, which is applied to the communication interface in the first embodiment, and fig. 2 is a schematic flow chart of a method for configuring a communication interface provided in the second embodiment of the present invention; as shown in fig. 2, the configuration method of the communication interface provided in the embodiment of the present application includes:

step S202, the CSB signal of the communication interface is configured to be an active low signal, so that the MCU reads and writes the register;

step S204, by configuring the FCSB signal of the communication interface to be an active-low signal, the MCU is enabled to read and write the FIFO;

in step S206, the MOSI pin and the MISO pin of the communication interface are configured to be combined into a secure digital input/output port, so that the MCU and the wireless transceiver chip can perform data transmission.

Specifically, the configuration method of the communication interface provided in the embodiment of the present application may be applied to the communication interface in the first embodiment, and by using two slave chip selection signals CSB and FCSB, the registers or FIFOs of the wireless transceiver chip are respectively selected to be read and written, without sending command switching, which is very flexible. And the transmission mode can be changed through different configurations of the SPI by the host without redundant processing on the slave side. The master-slave receiving and transmitting are carried out through one data line SDIO, so that the number of data transmission ports is reduced, continuous reading and writing of data are supported, multi-beat data can be transmitted at one time, and the transmission efficiency is improved.

Wherein, the low active CSB is a chip select signal for accessing registers, the low active FCSB is a chip select signal for accessing FIFO, and both cannot be set low at the same time. SCLK is a serial clock, the fastest speed can be up to 5MHz. The MCU itself or an external wireless transceiver chip sends out data on the falling edge of SCLK and collects data on the rising edge. SDIO is a bi-directional pin for inputting and outputting data. Both address and data portions are transferred from the MSB.

In summary, the configuration method of the communication interface provided in the embodiment of the present application configures the SPI in the read-write register and the read-write FIFO as follows:

1. configuration of SPI by read-write register:

when accessing the register, the CSB is pulled low. Then first send one R/W bit followed by 7 bits of register address. After pulling CSB low, the MCU must wait at least half a SCLK cycle before it can begin transmitting R/W bits. After the MCU sends out the falling edge of the last SCLK, it has to wait at least half a SCLK period and pull CSB high again.

For the register read operation of fig. 3, fig. 3 is a schematic diagram of the SPI read register timing sequence in the configuration method of the communication interface according to the second embodiment of the present invention, and both the MCU and the CMT2300A (i.e., the wireless transceiver chip in the embodiment of the present application) will generate the behavior of switching the IO (SDIO) port between address 0 and data 7. At this time, the CMT2300A will switch the IO port from input to output, and the MCU will switch the IO port from output to input. In the position of the middle broken line, before the MCU sends out the falling edge of SCLK, switching the IO port into input; CMT2300A switches IO to output after seeing a falling edge. This avoids the situation where both simultaneously set the SDIO to the output resulting in an electrical conflict. Fig. 4 is a schematic diagram of an SPI write register timing sequence in a configuration method of a communication interface according to a second embodiment of the present invention.

Optionally, the method for configuring a communication interface provided in the embodiment of the present application further includes: configuring a communication interface into a single-wire bidirectional mode, and setting a baud rate and a data frame format; wherein configuring the communication interface to be in a single-wire bidirectional mode, and setting the baud rate and the data frame format comprises: determining a serial clock baud rate by the MCLKP bit of the second CTRL register; and determining a phase relation between data transmission and a serial clock by configuring CPOL and CPHA bits of the second CTRL register to be 0, wherein the phase relation is as follows: transmitting data at the falling edge of the serial clock, and sampling the data at the rising edge of the serial clock; determining a data frame format as 8 bits or 16 bits by configuring DFF16 bits of the second CTRL register; determining the data frame format as the most significant bit MSB transmitted or received first by configuring the LSBEN bit of the second CTRL register to be 0; if the CSB pin is determined to work in an input mode, in a hardware mode, during data frame transmission, a level signal of the CSB pin is configured to be a high level signal; in software mode, the SWNSSEN bit and ISS bit of the second CTRL register are configured; if the CSB pin is operating in output mode, configuring NSSOE bit of the first CTRL register; by configuring the BDMODE bit of the second CTRL register, the communication interface enables a single-wire bidirectional mode, wherein the SCLK pin is used as a clock, the master device uses the MOSI pin, and the slave device uses the MISO pin for data communication; the transmission direction is controlled by the BDOE bit in the second CTRL register, and when the BDOE bit is 1, data is output; when the BDOE bit is 0, data input; through configuring DT register, writing in address of read-write wireless transceiver chip; and configuring the communication interface as a master device by setting the MSTEN bit of the second CTRL register.

Specifically, configuring the SPI to be in a single-wire bidirectional mode, and setting the baud rate and the data frame format includes:

first, MCLKP [3 ] through SPI_CTRL1 register (i.e., second CTRL register in the embodiments of the application): the 0 bit defines the serial clock baud rate.

Second, CPOL and CPHA bits configuring the SPI_CTRL1 register are 0, defining the phase relationship between the data transfer and the serial clock (trailing edge transmit data, leading edge sample data).

Third, the DFF16 bits of the spi_ctrl1 register are configured to define an 8-bit or 16-bit data frame format.

Fourth, the LSBEN bit configuring the spi_ctrl1 register is 0, defining the frame format as first transmitting/receiving MSB.

Fifth, if the CSB pin is required to operate in the input mode, in the hardware mode, the CSB pin should be connected to a high level during the entire data frame transmission; in software mode, SWNSSEN bit and ISS bit of SPI_CTRL1 register are set. If the CSB pin is operating in output mode, then only the NSSOE bit needs to be set.

Sixth, the BDMODE bit of the SPI_CTRL1 register is set, enabling a single-wire bidirectional mode in which the SCLK pin is clocked, the master device uses the MOSI pin and the slave device uses the MISO pin as data communications. The direction of transmission is controlled by the BDOE in the SPI_CTRL1 register, with the data line being the output when this bit is a '1' or the input otherwise. (whether read or write is determined by BDOE).

Seventh, an spi_dt register is set, and the address of the wireless transceiver chip to be read and written is written.

Eighth, MSTEN of SPI_CTRL1 register is set, and SPI is configured as master device.

Optionally, the method for configuring a communication interface provided in the embodiment of the present application further includes: configuring a communication interface into a read-write wireless receiving-transmitting register mode; wherein, the configuration of the communication interface as a read-write wireless receiving and transmitting register mode comprises: selecting the CSB signal as the chip select signal by configuring the NSS_SEL bit in the first CTRL register to be 0; by configuring the RF_EN bit in the first CTRL register to be 1, starting a read-write wireless receiving and transmitting register mode; the communication interface is enabled by configuring the EN bit in the second CTRL register to be 1.

Specifically, configuring the SPI to the RF mode includes:

first, NSS_SEL is configured to be 0 in SPI_CTRL2 (i.e., the first CTRL register in the embodiments of the application), and CSB is selected for use as the chip select signal.

Second, RF_EN in SPI_CTRL2 is configured to be 1, and the RF mode is started (the wireless transceiver register is read and written).

Third, SPI_CTRL1 (i.e., the second CTRL register in the embodiments of the application) is configured with SPI_EN (i.e., the EN bit in the embodiments of the application) to be 1, enabling the SPI device.

2. Configuration of SPI by read-write FIFO:

When the MCU needs to access the FIFO, firstly, some registers are configured to set the read/write mode of the FIFO, the timing diagrams of the read/write FIFO are shown in fig. 5 and 6, and fig. 5 is a schematic diagram of the SPI read FIFO timing in the configuration method of the communication interface according to the second embodiment of the invention; fig. 6 is a schematic diagram of an SPI write FIFO timing sequence in a configuration method of a communication interface according to a second embodiment of the present invention. It should be noted that there is a slight difference between the control of the FCSB and the control of the CSB when accessing the registers. At the beginning of the access, the FCSB is pulled down by 1 clock cycle before sending out the rising edge of SCLK. After the last falling edge of SCLK is sent out, the FCSB is pulled high for at least 2 us. Between two consecutive read and write operations, the FCSB must be pulled up by at least 4us. In writing to the FIFO, the first bit of data must be ready 0.5 clock cycles before the rising edge of the first SCLK is sent out.

In the process of reading and writing the FIFO, the SPI is configured to be in a single-line bidirectional mode, and the baud rate and the data frame format are set to be the same as those of the read/write register, which will not be described again.

Optionally, the step S204 of configuring the FCSB signal of the communication interface to be an active-low signal to enable the MCU to perform the read/write FIFO includes: selecting the FCSB as a chip select signal by configuring the nss_sel bit in the first CTRL register to be 1; determining delay time between continuous read-write operations in the FIFO mode by configuring TIM_CYCLE bits in the first CTRL register; starting the FIFO MODE by configuring the FIFO_MODE bit in the first CTRL register to be 1; the communication interface is enabled by configuring the EN bit in the second CTRL register to be 1.

Specifically, configuring the SPI to FIFO mode includes:

NSS_SEL in SPI_CTRL2 is configured to be 1, and FCSB is selected to be used as the chip select signal.

Timcycle in spi_ctrl2 is configured to an appropriate value to satisfy a delay time of 2us and 4us between successive read and write operations in FIFO mode. The delay time is counted from the falling edge of the last SCLK, the counting unit is half clock period of SCLK, and the calculation formula of the delay time is as follows:

the FIFO MODE in spi_ctrl2 is configured to be 1, and the FIFO MODE (read/write FIFO) is turned on.

SPI_EN in SPI_CTRL1 is configured to be 1, enabling SPI devices.

The embodiment of the invention provides a configuration method of a communication interface. The CSB signal of the communication interface is configured to be an active low signal so that the MCU reads and writes the register; the FCSB signal of the communication interface is configured to be an active-low signal so that the MCU can read and write the FIFO; the MOSI pin and the MISO pin of the communication interface are configured to be combined into a safe digital input/output port, so that the MCU and the wireless transceiver chip perform data transmission, the selection and switching of an RF mode and a FIFO mode can be realized through the configuration of the MCU to a register, the communication mode of a sending command is replaced, and the technical effects of decoding work and internal state reaction time of the wireless transceiver chip are reduced.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A communication interface, comprising:

the communication interface is connected with the wireless transceiver chip through a MOSI pin, a MISO pin, a SCLK pin and a NSS pin, wherein,

the MISO pin is a master device input/slave device output pin and is used for sending data in a slave mode and receiving data in a master mode;

the MOSI pin is a master device output/slave device input pin and is used for sending data in the master mode and receiving data in the slave mode;

the SCLK pin is a serial clock and is used for outputting the master device and inputting the slave device;

the NSS pin is a main device or a slave device selection pin and is used for performing chip selection on a register of the wireless transceiver chip by setting NSS [0] as a CSB signal and performing chip selection on a FIFO of the wireless transceiver chip by setting NSS [1] as an FCSB signal;

Wherein one side generating the clock is called a master device, and the other side is called a slave device; the communication interface is in a single-wire bidirectional mode, and the MOSI pin and the MISO pin are combined into a safe digital input/output port.

2. The communication interface of claim 1, wherein the communication interface further comprises: a transmit buffer, a shift register, an STS register, and a first CTRL register, wherein,

the sending buffer is used for writing data into the sending buffer in a writing operation; when the slave device receives a clock signal and a first data bit appears on the MOSI pin, starting a data transmission process, and storing the rest digital bits in a data frame format into the shift register; setting a TE flag of the STS register when data in the transmission buffer is transmitted to the shift register; if the TEIE bit of the first CTRL register is set, an interrupt is generated.

3. The communication interface of claim 2, wherein the communication interface further comprises: a receive buffer, wherein,

the receiving buffer is used for transmitting the data in the shift register to the receiving buffer when the data receiving is completed, and setting an RNE flag in the STS register; if the RNEIE bit in the first CTRL register is set, generating an interrupt; setting an RNE bit to 1 after the last sampling clock edge, the data bytes received in the shift register being transferred to the receive buffer; when reading the DT register, the communication interface returns the value of the receive buffer and clears the RNE bit.

4. The communication interface of claim 2, wherein a rf_en bit and a fifo_mode bit are added to the first CTRL register, the rf_en bit being used for the MCU to configure the communication interface to enable a read-write register MODE for the wireless transceiver chip; the FIFO_MODE bit is used for the MCU to configure the communication interface to start a read-write FIFO MODE of the wireless transceiver chip.

5. A communication interface according to claim 3, wherein the communication interface further comprises: a main control circuit, wherein,

adding an NSS_SEL bit to the first CTRL register for enabling NSS [0] and NSS [1] in the main control circuit; when the NSS_SEL bit is set to 0, NSS [0] is valid, and the NSS [0] is used as the CSB signal to select a register chip in the wireless transceiver chip; when the NSS_SLE bit is set to 1, NSS [1] is valid, and the NSS [1] is used as the FCSB signal to select a register chip in the wireless transceiver chip.

6. The communication interface of claim 5, wherein the main control circuit comprises: and the timer is used for starting counting when the CSB signal is pulled down in a read-write register mode, and when the timer reaches a counting threshold value, a first enabling signal is sent to start data transmission.

7. The communication interface of claim 6, wherein the timer is started when the main control circuit detects that data is transferred to preset data, and wherein a second enable signal is generated to pull up the CSB signal when the timer times the count threshold.

8. The communication interface of claim 4, further comprising: a delay counter; wherein, the liquid crystal display device comprises a liquid crystal display device,

the first CTRL register is further added with a TIM_CYCLE bit for configuring delay time;

the delay counter is used for counting from the falling edge of the last SCLK, and when the delay counter counts the delay time, the FCSB signal is pulled up; when the delay counter counts to a preset multiple of the delay time, if data are transmitted, the FCSB signal is pulled down; if the data is not transmitted, the FCSB signal is kept high.

9. The communication interface of claim 1, wherein the communication interface further comprises: and the second CTRL register is used for detecting the address 0 sent by the MCU after the communication interface is configured into a register reading mode, and switching the level signal of the BDOE bit in the second CTRL register before the falling edge of SCLK so as to switch the IO port from output to input.

10. A method of configuring a communication interface as claimed in any one of claims 1 to 9, comprising:

the CSB signal of the communication interface is configured to be an active low signal so that the MCU reads and writes the register;

the FCSB signal of the communication interface is configured to be an active-low signal so that the MCU can read and write the FIFO;

and combining the MOSI pin and the MISO pin of the communication interface into a safe digital input/output port so that the MCU and the wireless transceiver chip perform data transmission.

11. The method for configuring a communication interface according to claim 10, wherein the method further comprises:

configuring the communication interface into a single-wire bidirectional mode, and setting a baud rate and a data frame format; wherein the configuring the communication interface to be in a single-wire bidirectional mode, and setting the baud rate and the data frame format comprises:

determining a serial clock baud rate by the MCLKP bit of the second CTRL register;

and determining a phase relation between data transmission and a serial clock by configuring CPOL and CPHA bits of the second CTRL register to be 0, wherein the phase relation is as follows: transmitting data by the falling edge of the serial clock, and sampling the data by the rising edge of the serial clock;

Determining the data frame format as 8 bits or 16 bits by configuring DFF16 bits of the second CTRL register;

determining the data frame format as first transmitting or receiving a most significant bit MSB by configuring an LSBEN bit of the second CTRL register to be 0;

if the CSB pin is determined to work in an input mode, in a hardware mode, during data frame transmission, a level signal of the CSB pin is configured to be a high level signal; in software mode, configuring SWNSSEN bits and ISS bits of the second CTRL register; if the CSB pin is operating in output mode, configuring NSSOE bit of the first CTRL register;

the communication interface enables a single-wire bidirectional mode by configuring a BDMODE bit of the second CTRL register, wherein an SCLK pin is used as a clock, a master device uses the MOSI pin, and a slave device uses a MISO pin for data communication; the transmission direction is controlled by the BDOE bit in the second CTRL register, and when the BDOE bit is 1, data is output; the data input when the BDOE bit is 0;

through configuring DT register, writing in address of read-write wireless transceiver chip;

and configuring the communication interface as a master device by setting an MSTEN bit of the second CTRL register.

12. The method for configuring a communication interface according to claim 11, wherein the method further comprises:

configuring the communication interface into a read-write wireless receiving-transmitting register RF mode; wherein, the configuring the communication interface to read and write the wireless receiving and transmitting register mode includes:

selecting a CSB signal as a chip select signal by configuring an nss_sel bit in the first CTRL register to be 0;

by configuring an RF_EN bit in the first CTRL register to be 1, starting a read-write wireless receiving and transmitting register mode;

the communication interface is enabled by configuring an EN bit in the second CTRL register to be 1.

13. The method according to claim 11, wherein the configuring the FCSB signal of the communication interface to be an active-low signal to cause the MCU to perform the read-write FIFO comprises:

selecting an FCSB as a chip select signal by configuring an nss_sel bit in the first CTRL register to be 1;

determining delay time between continuous read-write operations in a FIFO mode by configuring a TIM_CYCLE bit in the first CTRL register;

starting a FIFO MODE by configuring a FIFO_MODE bit in the first CTRL register to be 1;