CN110795369B - Method and terminal for realizing MDIO slave function based on GPIO pin - Google Patents
Method and terminal for realizing MDIO slave function based on GPIO pin Download PDFInfo
- Publication number
- CN110795369B CN110795369B CN201910887579.0A CN201910887579A CN110795369B CN 110795369 B CN110795369 B CN 110795369B CN 201910887579 A CN201910887579 A CN 201910887579A CN 110795369 B CN110795369 B CN 110795369B
- Authority
- CN
- China
- Prior art keywords
- mdio
- slave
- slave cpu
- bits
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Information Transfer Systems (AREA)
- Electrotherapy Devices (AREA)
- Microcomputers (AREA)
Abstract
The invention discloses a method and a terminal for realizing MDIO slave functions based on GPIO pins, wherein the method comprises the following steps: setting GPIO1 as a clock signal and setting GPIO2 as a data signal; the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a double-wire way between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU. The invention realizes the MDIO slave function through the GPIO pin, and can be accessed by the MDIO host.
Description
Technical Field
The present invention relates to the field of computer application technologies, and in particular, to a method, a terminal, and a storage medium for implementing an MDIO slave function based on a GPIO pin.
Background
The MDIO (Management Data Input/Output) interface is a very simple serial interface with only two wires, and is generally used for connecting with a physical layer chip of a network port. MDIO is also divided into a master device and a slave device, wherein the master device initiates MDIO time sequence, and the slave device receives the MDIO time sequence and reacts to a certain degree. Most CPUs with network ports support the function of an MDIO host, and GPIO (general purpose input/output ports for short, namely STM32 controllable pins, are simply called) can be used, and GPIO pins of STM32 chips are connected with external equipment, so that the functions of communication, control and data acquisition with the outside are realized to simulate MDIO time sequences, and the MDIO protocol is realized by software. The driving of MDIO host mode by GPIO is very simple and mature, and the driving is very much used.
If the MDIO slave function is to be implemented on the current general-purpose CPU and accessed by the MDIO host, hardware support is generally required, or a CPLD (Complex Programmable Logic Device ) is used to implement the protocol, and it is difficult to implement the MDIO slave function in software.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
The invention mainly aims to provide a method, a terminal and a storage medium for realizing an MDIO slave function based on GPIO pins, and aims to solve the problem that the MDIO slave function cannot be realized through software in the prior art.
In order to achieve the above object, the present invention provides a method for implementing an MDIO slave function based on a GPIO pin, the method for implementing an MDIO slave function based on a GPIO pin includes the following steps:
setting GPIO1 as a clock signal and setting GPIO2 as a data signal;
the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a double-wire way between the host MCU and the slave CPU;
when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.
Optionally, the method for implementing the MDIO slave function based on the GPIO pin further includes:
when the clock signal is pulled up to be high level by the host MCU, the slave CPU sends out an interrupt through the GPIO1, the slave CPU enters an interrupt processing program, and the level of the MDIO pin of the GPIO2 is read and stored in the interrupt processing program.
Optionally, the method for implementing the MDIO slave function based on the GPIO pin, wherein the setting GPIO1 is a clock signal, and setting GPIO2 is a data signal, further includes:
setting GPIO1 as an input function, setting GPIO2 as an input/output function, and setting GPIO1 as an edge interrupt attribute;
mounting a GPIO1 interrupt processing function;
the number of the received bits is 0, and the number of the transmitted bits is 0;
enabling GPIO1 interrupts, setting the MDIO device address to 0x08.
Optionally, the method for implementing MDIO slave functions based on GPIO pins, where the interrupt processing function is configured to process a read-write request sent by the host MCU;
when the host MCU writes the slave CPU, the level of the clock signal is read in the interrupt processing function, one bit is read for each interrupt, and 5 bits are read as a device address and a 5-bit register internal address according to a protocol PHY address.
Optionally, in the method for implementing MDIO slave functions based on GPIO pins, two states are predefined, namely an idle state and a busy state;
the idle state indicates that no request is currently required, the bus is empty, and 32 synchronous frames are waited for;
the busy state indicates that the current state has entered into the MDIO timing.
Optionally, the method for implementing the MDIO slave function based on the GPIO pin further includes:
when entering the entry of the interrupt processing function, judging whether the current state is an idle state or not;
when in an idle state, reading the GPIO2 level to a receiving buffer, receiving the bit number, and judging whether the bit number is 46;
and when the state is yes, judging whether a synchronous frame with 32 bits, 2 start bits, 2 operation codes and 2 bit read-write bits exist, when any one of the synchronous frame with 32 bits, the 2 operation codes and the 2 bit read-write bits is no, the whole state machine enters an idle state, and when the state is yes, the whole state machine enters a busy state, the receiving bit length is 0, and the sending bit length is 0.
Optionally, the method for implementing MDIO slave functions based on GPIO pins, wherein the determining whether the current state is an idle state further includes:
when not in the idle state, a read operation or a write operation is entered;
the read operation is: writing the register value of the A address into GPIO2 according to the bit, transmitting the bit length to be added with 1, enabling the final state to enter an idle state, and receiving the bit length to be 0;
the write operation is: and reading the high-low level value of the GPIO2 to a receiving buffer, adding 1 to the number of receiving bits, writing 16-bit data of the receiving buffer into a register address A, and enabling the final state to enter an idle state and receiving the bit length of 0.
In addition, to achieve the above object, the present invention further provides a system for implementing MDIO slave functions based on GPIO pins, where the system includes: a host MCU and a slave CPU;
the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted by two wires between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.
In addition, to achieve the above object, the present invention also provides a terminal, wherein the terminal includes: the method comprises the steps of a memory, a processor and a program which is stored in the memory and can run on the processor and realizes the MDIO slave function based on the GPIO pin, wherein the program which realizes the MDIO slave function based on the GPIO pin realizes the method for realizing the MDIO slave function based on the GPIO pin when being executed by the processor.
In addition, in order to achieve the above object, the present invention further provides a storage medium, where the storage medium stores a program for implementing an MDIO slave function based on a GPIO pin, and the program for implementing the MDIO slave function based on the GPIO pin implements the steps of the method for implementing the MDIO slave function based on the GPIO pin as described above when the program for implementing the MDIO slave function based on the GPIO pin is executed by a processor.
The invention sets GPIO1 as clock signal and GPIO2 as data signal; the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a double-wire way between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU. The invention realizes the MDIO slave function through the GPIO pin, and can be accessed by the MDIO host.
Drawings
FIG. 1 is a flow chart of a preferred embodiment of a method of the present invention for implementing MDIO slave functions based on GPIO pins;
FIG. 2 is a functional schematic diagram of a preferred embodiment of the system of the present invention implementing MDIO slave functions based on GPIO pins;
FIG. 3 is a schematic flow chart of an initialization stage in the method for implementing MDIO slave functions based on GPIO pins;
FIG. 4 is a schematic diagram of a state judgment and execution process in the method for implementing MDIO slave functions based on GPIO pins;
FIG. 5 is a schematic diagram of the operating environment of a preferred embodiment of the terminal of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clear and clear, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The method for implementing the MDIO slave function based on the GPIO pin according to the preferred embodiment of the present invention, as shown in fig. 1 and 2, comprises the following steps:
step S10, setting GPIO1 as a clock signal (MDC signal) and setting GPIO2 as a data signal (MDIO signal);
step S20, the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted by two wires between the host MCU and the slave CPU;
and step S30, when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.
Further, the GPIO1 pin of the selected MDC can support to send an interrupt to the slave CPU, and the interrupt type can be set as an edge starting; once the MDC is pulled up by the host MCU to be effective, the GPIO1 of the slave CPU sends an interrupt to the CPU, the slave CPU enters an interrupt processing program, then the level of a GPIO2MDIO pin is read in the interrupt processing program, the high level represents data 1, and the low level represents data 0; and storing each read bit into a variable, and carrying out corresponding processing according to the time sequence requirement of the MDIO protocol.
As shown in the following table (data frame structure of MDIO interface), the MDIO protocol format is as follows:
the specific meaning of each domain is as follows:
PRE: frame sync codes, in which state the MAC will drive the MDIO to send 32 consecutive "1's" to the PHY device for synchronous communication by the device, but this field is not necessary, and some PHY devices do not operate in this field for efficiency,
ST: the frame start flag, the MAC output "01" bit informs the PHY that frame operation starts.
OP: the frame opcode, bit "01" indicates that the frame is a write once request, and bit "10" indicates that the frame is a read once request.
PHY AD: the address of each PHY device is 5 bits wide, each PHY device compares the address of each PHY device with the 5 bits, if the address of each PHY device is matched with the 5 bits, the subsequent operation is responded, if the address of each PHY device is not matched with the address of each PHY device, the subsequent operation is ignored, and the configuration of 32 PHY chips can be supported at most by the 5 bits of each PHY device.
REG AD: PHY register address, 5 bits wide; the PHY is a physical layer interface, and each PHY interface contains 32 registers of 16 bits, wherein the first 16 registers (corresponding to addresses 5'b00000 to 5' b 11111) are the registers required to be provided by the 802.3 protocol, and the last 16 registers are registers with functions which can be specified by a manufacturer. The contents of the first 16 registers of different PHY chips should generally be identical.
TA: state transition field, 2 bits total. If the read operation is performed, the 1 st bit is sent out to the high impedance state by the MDIO module, and the 2 nd bit is set to be 0 by the PHY chip to the MDIO signal. If the operation is writing operation, the MDIO signal is controlled by the MDIO module, and two bits of 10 are continuously output.
DATA: the register data field of the frame is 16 bits in total. If the data is read, the serial data sent to the MDIO module by the PHY is written, and if the data is write, the serial data sent to the PHY by the MDIO module is written.
IDLE: and an idle state after the end of the frame. At this time, the MDIO is passively driven and is in a high-resistance state, but is generally made to be in a high level by using a pull-up resistor.
Furthermore, the whole process of the method for realizing the MDIO slave function based on the GPIO pin is divided into an initialization stage, a reading operation and a writing operation. The initialization flow is shown in fig. 3, and specifically includes:
s1: setting GPIO1 as an input function;
s2: setting GPIO2 as an input and output function;
s3: setting GPIO1 as an edge interrupt attribute;
s4: mounting GPIO1 interrupt handling function gpio1_irs ();
s5: the number of the received bits is 0, and the number of the transmitted bits is 0;
s6: enabling GPIO1 interrupts;
s7: the MDIO device address is set to 0x08.
The core part is an interrupt processing function gpio1_irs (), which is used for processing a read-write request sent by the host MCU, if the host MCU is to write the slave CPU, the level of MDC is read in gpio1_irs (), one bit is read per interrupt (bit is the minimum unit for representing information, is the information contained in one bit of binary number or the required information quantity of 1 in 2 options) and 5 bits are read as device addresses according to a protocol PHY address, and then the internal addresses of a 5-bit register are read.
Further, as shown in fig. 4, two states are predefined, namely an idle state and a busy state; the idle state indicates that no request is currently required, the bus is empty, and 32 synchronous frames are waited for; the busy state indicates that the current state has entered into the MDIO timing.
Specifically, when entering the entry of the interrupt handling function gpio1_irs (), judging whether the current state is an idle state (N represents no, and the other represents yes), when in the idle state, reading the GPIO2 level to the reception buffer, and receiving the bit number l=l+1, judging whether the bit number is 46, when no, entering the exit of gpio1_irs (), when yes, judging whether bits [0-31] = all 1, bits [32-33] = 0b01, when no, then controlling the current state to be in the idle state, and receiving the bit length=0, and transmitting the bit length=0, when yes, then judging whether bits [36-41] = device address 0x08, when no, then controlling the current state to be in the idle state, and receiving the bit length=0, when yes, register address a=bits [42-46], operation code o=bits [34-35], controlling the current state to be in the busy state, and receiving the bit length=0, and judging whether the bit length=0=01; and after the initial determination, when not in the idle state, also enter to determine if opcode= 01; entering a write operation when yes, and entering a read operation when no; write operation: reading the high-low level value of GPIO2 to a receiving buffer, adding 1 to the number of receiving bits, judging whether the number of receiving bits L= =16, entering an outlet of GPIO1_irs (), and writing the 16-bit data of the receiving buffer into a register address A when the number of receiving bits is not equal to the number of receiving bits L= 16, entering an idle state in a final state, receiving the bit length of 0, and entering the outlet of GPIO1_irs (); read operation: and writing the register value of the A address into GPIO2 according to the bits, adding 1 to the transmission bit length, judging whether the transmission bit number L= =16, entering the outlet of gpio1_irs () if not, and entering the idle state in the final state if yes, and receiving the bit length of 0.
The slave CPU is continuously interrupted at 46, reads 46-bit data, and respectively judges whether the data is a synchronous frame with 32 bits, 2 start bits, 2 operation codes and 2 bits read-write bits; as long as there is a judgment error, the whole state machine enters an idle transition state, and continues to read 46 bits.
If the operation is a read operation, writing one bit into the GPIO2MDIO by each interrupt in 16 continuous interrupts, and continuing to enter an idle state after finishing the operation; if the operation is writing, in the 16 continuous interrupts, each interrupt reads one bit from GPIO2MDIO, and after the 16-bit data is spliced, the data is written into the A address register, and after the completion, the idle state is continuously entered.
Further, as shown in fig. 2, the present invention further provides a system for implementing MDIO slave functions based on GPIO pins, where the system includes: a host MCU and a slave CPU; setting GPIO1 as a clock signal (MDC signal) and setting GPIO2 as a data signal (MDIO signal); the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted by two wires between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.
Further, as shown in fig. 5, based on the method for implementing the MDIO slave function based on the GPIO pin, the present invention further provides a terminal correspondingly, where the terminal includes a processor 10, a memory 20 and a display 30. Fig. 5 shows only some of the components of the terminal, but it should be understood that not all of the illustrated components are required to be implemented and that more or fewer components may be implemented instead.
The memory 20 may in some embodiments be an internal storage unit of the terminal, such as a hard disk or a memory of the terminal. The memory 20 may in other embodiments also be an external storage device of the terminal, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the terminal. Further, the memory 20 may also include both an internal storage unit and an external storage device of the terminal. The memory 20 is used for storing application software installed in the terminal and various data, such as program codes of the installation terminal. The memory 20 may also be used to temporarily store data that has been output or is to be output. In an embodiment, the memory 20 stores a program 40 for implementing the MDIO slave function based on the GPIO pin, and the program 40 for implementing the MDIO slave function based on the GPIO pin may be executed by the processor 10, so as to implement the method for implementing the MDIO slave function based on the GPIO pin in the present application.
The processor 10 may be, in some embodiments, a central processing unit (Central Processing Unit, CPU), microprocessor or other data processing chip for executing program code or processing data stored in the memory 20, such as executing the method for implementing MDIO slave functions based on GPIO pins.
The display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch, or the like in some embodiments. The display 30 is used for displaying information at the terminal and for displaying a visual user interface. The components 10-30 of the terminal communicate with each other via a system bus.
In one embodiment, the following steps are implemented when the processor 10 executes the program 40 for implementing the MDIO slave function based on the GPIO pin in the memory 20:
setting GPIO1 as a clock signal and setting GPIO2 as a data signal;
the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a double-wire way between the host MCU and the slave CPU;
when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.
The method for realizing MDIO slave function based on GPIO pin further comprises:
when the clock signal is pulled up to be high level by the host MCU, the slave CPU sends out an interrupt through the GPIO1, the slave CPU enters an interrupt processing program, and the level of the MDIO pin of the GPIO2 is read and stored in the interrupt processing program.
The setting of the GPIO1 as a clock signal and the setting of the GPIO2 as a data signal also include:
setting GPIO1 as an input function, setting GPIO2 as an input/output function, and setting GPIO1 as an edge interrupt attribute;
mounting a GPIO1 interrupt processing function;
the number of the received bits is 0, and the number of the transmitted bits is 0;
enabling GPIO1 interrupts, setting the MDIO device address to 0x08.
The interrupt processing function is used for processing a read-write request sent by the host MCU;
when the host MCU writes the slave CPU, the level of the clock signal is read in the interrupt processing function, one bit is read for each interrupt, and 5 bits are read as a device address and a 5-bit register internal address according to a protocol PHY address.
Two states are predefined, namely an idle state and a busy state;
the idle state indicates that no request is currently required, the bus is empty, and 32 synchronous frames are waited for;
the busy state indicates that the current state has entered into the MDIO timing.
The method for realizing MDIO slave function based on GPIO pin further comprises:
when entering the entry of the interrupt processing function, judging whether the current state is an idle state or not;
when in an idle state, reading the GPIO2 level to a receiving buffer, receiving the bit number, and judging whether the bit number is 46;
and when the state is yes, judging whether a synchronous frame with 32 bits, 2 start bits, 2 operation codes and 2 bit read-write bits exist, when any one of the synchronous frame with 32 bits, the 2 operation codes and the 2 bit read-write bits is no, the whole state machine enters an idle state, and when the state is yes, the whole state machine enters a busy state, the receiving bit length is 0, and the sending bit length is 0.
The step of judging whether the current state is an idle state further comprises the following steps:
when not in the idle state, a read operation or a write operation is entered;
the read operation is: writing the register value of the A address into GPIO2 according to the bit, transmitting the bit length to be added with 1, enabling the final state to enter an idle state, and receiving the bit length to be 0;
the write operation is: and reading the high-low level value of the GPIO2 to a receiving buffer, adding 1 to the number of receiving bits, writing 16-bit data of the receiving buffer into a register address A, and enabling the final state to enter an idle state and receiving the bit length of 0.
Further, the present invention also provides a storage medium, where the storage medium stores a program for implementing an MDIO slave function based on a GPIO pin, and the program for implementing the MDIO slave function based on the GPIO pin implements the steps of the method for implementing the MDIO slave function based on the GPIO pin as described above when the program for implementing the MDIO slave function based on the GPIO pin is executed by a processor.
In summary, the present invention provides a method and a terminal for implementing MDIO slave functions based on GPIO pins, where the method includes: setting GPIO1 as a clock signal and setting GPIO2 as a data signal; the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a double-wire way between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU. The invention realizes the MDIO slave function through the GPIO pin, and can be accessed by the MDIO host.
Of course, those skilled in the art will appreciate that implementing all or part of the above-described methods may be implemented by a computer program for instructing relevant hardware (such as a processor, a controller, etc.), where the program may be stored in a computer-readable storage medium, and where the program may include the steps of the above-described method embodiments when executed. The storage medium may be a memory, a magnetic disk, an optical disk, or the like.
It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (4)
1. The method for realizing the MDIO slave function based on the GPIO pin is characterized by comprising the following steps of:
setting GPIO1 for transmitting clock signals and GPIO2 for transmitting data signals on a slave CPU;
the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a double-wire way between the host MCU and the slave CPU;
when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU;
the method for realizing MDIO slave function based on GPIO pin further comprises:
when the clock signal is pulled up to be high level by the host MCU, the slave CPU sends out an interrupt through the GPIO1, the slave CPU enters an interrupt processing program, and the level of an MDIO pin of the GPIO2 is read and stored in the interrupt processing program;
the method comprises the steps that GPIO1 is set on a slave CPU and used for transmitting clock signals, GPIO2 is set on the slave CPU and used for transmitting data signals, and the method further comprises the following steps:
setting GPIO1 with an input function, setting GPIO2 with an input and output function, and setting GPIO1 with an edge interrupt attribute;
mounting a GPIO1 interrupt processing function;
the number of the received bits is 0, and the number of the transmitted bits is 0;
enabling GPIO1 interrupt, and setting the MDIO device address to 0x08;
the interrupt processing function is used for processing a read-write request sent by the host MCU;
when the host MCU writes the slave CPU, the level of the clock signal is read in the interrupt processing function, one bit is read for each interrupt, and 5 bits are read as a device address and a 5-bit register internal address according to a protocol PHY address;
two states are predefined, namely an idle state and a busy state;
the idle state indicates that no request is currently required, the bus is empty, and 32 synchronous frames are waited for;
the busy state indicates that the current state has entered into the MDIO timing sequence;
the method for realizing MDIO slave function based on GPIO pin further comprises:
when entering the entry of the interrupt processing function, judging whether the current state is an idle state or not;
when in an idle state, reading the GPIO2 level to a receiving buffer, receiving the bit number, and judging whether the bit number is 46;
if yes, judging whether a synchronous frame with 32 bits, 2 start bits, 2 operation codes and 2 bits read-write bits exist, if any one of the synchronous frames is not, the whole state machine enters an idle state, if yes, the whole state machine enters a busy state, the receiving bit length is 0, and the sending bit length is 0;
the step of judging whether the current state is an idle state further comprises the following steps:
when not in the idle state, a read operation or a write operation is entered;
the read operation is: writing the register value of the A address into GPIO2 according to the bit, transmitting the bit length to be added with 1, enabling the final state to enter an idle state, and receiving the bit length to be 0;
the write operation is: and reading the high-low level value of the GPIO2 to a receiving buffer, adding 1 to the number of receiving bits, writing 16-bit data of the receiving buffer into a register address A, and enabling the final state to enter an idle state and receiving the bit length of 0.
2. A system for implementing MDIO slave functions based on GPIO pins, the system comprising: a host MCU and a slave CPU;
setting GPIO1 for transmitting clock signals and GPIO2 for transmitting data signals on a slave CPU; the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted by two wires between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU;
when the clock signal is pulled up to be high level by the host MCU, the slave CPU sends out an interrupt through the GPIO1, the slave CPU enters an interrupt processing program, and the level of an MDIO pin of the GPIO2 is read and stored in the interrupt processing program;
the method comprises the steps that GPIO1 is set on a slave CPU and used for transmitting clock signals, GPIO2 is set on the slave CPU and used for transmitting data signals, and the method further comprises the following steps:
setting GPIO1 with an input function, setting GPIO2 with an input and output function, and setting GPIO1 with an edge interrupt attribute;
mounting a GPIO1 interrupt processing function;
the number of the received bits is 0, and the number of the transmitted bits is 0;
enabling GPIO1 interrupt, and setting the MDIO device address to 0x08;
the interrupt processing function is used for processing a read-write request sent by the host MCU;
when the host MCU writes the slave CPU, the level of the clock signal is read in the interrupt processing function, one bit is read for each interrupt, and 5 bits are read as a device address and a 5-bit register internal address according to a protocol PHY address;
two states are predefined, namely an idle state and a busy state;
the idle state indicates that no request is currently required, the bus is empty, and 32 synchronous frames are waited for;
the busy state indicates that the current state has entered into the MDIO timing sequence;
when entering the entry of the interrupt processing function, judging whether the current state is an idle state or not;
when in an idle state, reading the GPIO2 level to a receiving buffer, receiving the bit number, and judging whether the bit number is 46;
if yes, judging whether a synchronous frame with 32 bits, 2 start bits, 2 operation codes and 2 bits read-write bits exist, if any one of the synchronous frames is not, the whole state machine enters an idle state, if yes, the whole state machine enters a busy state, the receiving bit length is 0, and the sending bit length is 0;
the step of judging whether the current state is an idle state further comprises the following steps:
when not in the idle state, a read operation or a write operation is entered;
the read operation is: writing the register value of the A address into GPIO2 according to the bit, transmitting the bit length to be added with 1, enabling the final state to enter an idle state, and receiving the bit length to be 0;
the write operation is: and reading the high-low level value of the GPIO2 to a receiving buffer, adding 1 to the number of receiving bits, writing 16-bit data of the receiving buffer into a register address A, and enabling the final state to enter an idle state and receiving the bit length of 0.
3. A terminal, the terminal comprising: the method comprises the steps of a memory, a processor and a program which is stored in the memory and can run on the processor and is used for realizing the MDIO slave function based on GPIO pins, wherein the program which is used for realizing the MDIO slave function based on the GPIO pins is executed by the processor and is used for realizing the method for realizing the MDIO slave function based on the GPIO pins according to claim 1.
4. A storage medium storing a program for implementing an MDIO slave function based on a GPIO pin, the program for implementing the MDIO slave function based on the GPIO pin implementing the steps of the method for implementing the MDIO slave function based on the GPIO pin according to claim 1 when executed by a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910887579.0A CN110795369B (en) | 2019-09-19 | 2019-09-19 | Method and terminal for realizing MDIO slave function based on GPIO pin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910887579.0A CN110795369B (en) | 2019-09-19 | 2019-09-19 | Method and terminal for realizing MDIO slave function based on GPIO pin |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110795369A CN110795369A (en) | 2020-02-14 |
| CN110795369B true CN110795369B (en) | 2023-05-30 |
Family
ID=69438574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910887579.0A Active CN110795369B (en) | 2019-09-19 | 2019-09-19 | Method and terminal for realizing MDIO slave function based on GPIO pin |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110795369B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112269338A (en) * | 2020-10-23 | 2021-01-26 | 阳光电源股份有限公司 | GPIO-based digital controller communication method and system |
| CN115834282B (en) * | 2022-11-07 | 2024-08-06 | 交控科技股份有限公司 | CAN bus communication method, device, equipment and readable storage medium |
| CN117076352A (en) * | 2023-08-22 | 2023-11-17 | 深圳市飞宇光纤股份有限公司 | Method and system for realizing access to PHY chip by simulating SMI protocol through GPIO port |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6532533B1 (en) * | 1999-11-29 | 2003-03-11 | Texas Instruments Incorporated | Input/output system with mask register bit control of memory mapped access to individual input/output pins |
| US7376780B2 (en) * | 2005-10-31 | 2008-05-20 | Lsi Corporation | Protocol converter to access AHB slave devices using the MDIO protocol |
| US8531286B2 (en) * | 2007-09-05 | 2013-09-10 | Stanley Convergent Security Solutions, Inc. | System and method for monitoring security at a premises using line card with secondary communications channel |
| CN102291423B (en) * | 2011-05-12 | 2013-08-14 | 福建星网锐捷网络有限公司 | Method for controlling physical layer (PHY) chip and control circuit |
| US9852101B2 (en) * | 2014-05-26 | 2017-12-26 | Mediatek Inc. | Electronic device with enhanced management data input/output control |
| CN105677599A (en) * | 2014-11-19 | 2016-06-15 | 中兴通讯股份有限公司 | Host and method and system for managing slaves by host |
| CN106020888B (en) * | 2016-05-24 | 2019-04-09 | 武汉虹信通信技术有限责任公司 | A kind of method and apparatus of ten thousand mbit ethernet of fast driving |
| CN107426118B (en) * | 2017-07-24 | 2020-05-12 | 西安微电子技术研究所 | Gigabit Ethernet switching circuit access device based on MDC/MDIO interface |
| CN110175145B (en) * | 2019-05-23 | 2021-07-06 | 深圳市易飞扬通信技术有限公司 | MDIO interface communication method and circuit |
-
2019
- 2019-09-19 CN CN201910887579.0A patent/CN110795369B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110795369A (en) | 2020-02-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110795369B (en) | Method and terminal for realizing MDIO slave function based on GPIO pin | |
| US9747237B2 (en) | Methods and apparatus for reliable detection and enumeration of devices | |
| US8898358B2 (en) | Multi-protocol communication on an I2C bus | |
| US10204065B2 (en) | Methods and apparatus for a multiple master bus protocol | |
| JP2018533120A (en) | Bridging and virtualization of input / output signals in multi-node networks | |
| EP1764703A1 (en) | A system for providing access to multiple data buffers of a data retaining and processing device | |
| CN211376201U (en) | Command read-write device and memory | |
| US20070088874A1 (en) | Offload engine as processor peripheral | |
| US20100064083A1 (en) | Communications device without passive pullup components | |
| JP2008539496A (en) | Simultaneous control of multiple I / O banks of I2C slave devices | |
| KR100919159B1 (en) | Multimedia card interface method, computer program product and apparatus | |
| CN106066842A (en) | A kind of method of switch mode, SOC(system on a chip) and base station | |
| CN111948971A (en) | Intelligent card management device and data switching method thereof | |
| US20070168580A1 (en) | Apparatus to improve the firmware efficiency for a multiframe serial interface | |
| CN117056249B (en) | MDIO-to-AHB conversion method, system, equipment and medium | |
| CN110795373B (en) | I2C bus-to-parallel bus conversion method, terminal and storage medium | |
| CN110990310B (en) | Device side SD controller, control method and electronic device | |
| CN106649187B (en) | Method for selecting chip automation peripheral protocol | |
| JP3477306B2 (en) | Extended input / output interface | |
| CN116192624A (en) | Communication interface configuration method and communication interface | |
| US20070131767A1 (en) | System and method for media card communication | |
| CN111427813A (en) | Inter-core communication method based on serial port, terminal and storage medium | |
| CN112732176A (en) | SSD (solid State disk) access method and device based on FPGA (field programmable Gate array), storage system and storage medium | |
| CN106874230B (en) | Daughter board applied to PC/104 bus interface and method applied to daughter board | |
| CN218886572U (en) | Simple peripheral bus system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |