CN211376201U - Command read-write device and memory - Google Patents

Abstract

The embodiment of the utility model provides a command read-write equipment, include: the system comprises a bus interface module, a cache control module, a cache module and a read-write module; the cache control module comprises: the system comprises a first cache control module and a second cache control module; the cache module comprises: at least two read buffers, at least two write buffers; the bus interface module is used for receiving a bus read/write command; the first cache control module is used for writing the received bus write commands which belong to the same Burst DDR Burst access into the same write cache region; the second cache control module is used for returning data of a read cache region accessed by the same DDR Burst as the bus read command; the read-write module is used for reading the read buffer area or the write buffer area to execute DDR Burst read or write operation. By combining a plurality of small data read-write operation commands together, the frequency of DDR Burst read-write operation is reduced, and the data read-write efficiency is improved.

Description

Command read-write device and memory

Technical Field

The embodiment of the utility model provides a but, relate to but not limited to DDR memory data read-write field, particularly, relate to but not limited to a command read-write device, memory.

Background

DDR SDRAM is a synchronous dynamic random access memory, which adopts double-rate access, and data are sampled at the rising edge and the falling edge of a working clock, so that the access rate is effectively improved.

The data access of DDR SDRAM is in Burst unit, when the data access amount is less than 1 Burst, the data access is still in Burst unit. The Burst access characteristic of the DDR SDRAM makes the DDR controller of the AXI bus or similar bus interface very inefficient for multiple small data accesses from the host to non-consecutive addresses. The AXI bus, unlike the AHB bus, can support the continuous transmission of multiple read and write commands.

Taking reading and writing 1Byte data as an example, the DDR controller receives reading and writing commands of three non-consecutive addresses 0x01, 0x03 and 0x05 of the bus, the three commands are all used for completing reading and writing of 1Byte, and the data access amount is less than one DDR Burst. And the conventional DDR controller only realizes the direct conversion of time sequences, and for the read-write commands of the three addresses, the DDR controller needs to initiate 3 DDR Burst transmissions to complete data access.

In the related art, one method for improving the read-write efficiency of the DDR is to achieve seamless read-write of data. The premise of seamless reading and writing is that the burst length of DDR is a fixed value, and the interval between two reading commands is well controlled. For the case that the burst length is set to 4, one NOP command needs to be inserted between two read commands to achieve seamless reading and writing of data. For the case where the burst length is set to 8, three NOP commands need to be inserted between two read commands. The method has no obvious improvement on efficiency for small data volume read-write access of non-continuous addresses, and 3 DDR Burst transmissions still need to be sent for the above-mentioned scenes of reading and writing 1Byte commands of three non-continuous addresses 0x01, 0x03 and 0x05, and only the effective data of the data line is continuous and uninterrupted. In addition, in order to realize seamless transmission, the complexity of the control logic of the DDR controller for initiating the read-write command is increased.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a command read-write method, device and computer storage medium, the main technical problem who solves leads to reading/writing the problem of inefficiency to the continuous a plurality of little data volume reading/writing commands of DDR to and the correlation technique improves the obscure condition to efficiency.

In order to solve the above technical problem, an embodiment of the utility model provides a command read-write device, include: the system comprises a bus interface module, a cache control module, a cache module and a read-write module; the cache control module comprises: the system comprises a first cache control module and a second cache control module; the cache module comprises: at least two read buffers, at least two write buffers;

the bus interface module is used for receiving a bus read/write command;

the first cache control module is used for writing the received bus write commands which belong to the same Burst DDR Burst access into the same write cache region;

the second cache control module is used for returning data of a read cache region accessed by the same DDR Burst as the bus read command;

the read-write module is used for reading the read buffer area or the write buffer area to execute DDR Burst read or write operation.

Optionally, each read buffer includes the following information: the system comprises a starting address, a command valid identifier, a data register and a data valid identifier.

Each write buffer includes the following information: the system comprises a starting address, a command valid identifier, a data register and a data valid identifier.

Optionally, the first cache control module includes: the device comprises a first writing module and a first judging module;

the first write-in module is used for writing a first bus write command into a first write cache region when the bus interface module receives the first bus write command, so that the first write cache region and the first bus write command belong to the same DDR Burst access;

the first judging module is used for judging whether the second write command of the bus and the first write cache region belong to the same DDR Burst access or not when the bus interface module receives the second write command of the bus;

the first write-in module is also used for writing the second write command of the bus into the first write cache region when the second write command of the bus and the first write cache region belong to the same DDR Burst access;

the first write-in module is further used for writing the second bus write command into the second write cache region when the second bus write command and the first write cache region do not belong to the same DDR Burst access.

Optionally, the second cache control module includes: the second judgment module and the data return module;

the second judging module is used for judging whether a used read cache region which belongs to the same DDR Burst access with the bus read command exists or not;

and the data return module is used for taking the used read cache region which belongs to the same DDR Burst access with the bus read command as a first read cache region and returning the data of the first read cache region when the used read cache region which belongs to the same DDR Burst access with the bus read command exists.

Optionally, the used read buffer 120 includes: either the data valid flag or the command valid flag is valid read buffer 120.

Optionally, the second determining module is further configured to: judging whether the data valid identification of the first read cache region is valid;

the data returning module is used for returning the data of the first read cache region when the data valid identification of the first read cache region is valid;

the data returning module is used for returning the data of the first read cache region when the data valid identification of the first read cache region is changed from invalid to valid.

Optionally, the second cache control module further includes: a second write module;

the second write-in module is used for marking the valid identification of the bus read command write-in command as an invalid read cache region, using the read cache region of the write-in bus read command as a second read cache region, and marking the valid identification of the command of the second read cache region after the write-in bus read command as valid.

Optionally, the bus interface module is further configured to:

judging whether a bus read/write command crosses DDR Burst transmission or not;

if so, splitting the bus read/write command into a plurality of sub-bus read/write commands according to the DDR Burst address rule, and enabling each split sub-bus read/write command not to be transmitted across the DDR Burst.

Optionally, the cache control module is further configured to:

judging whether the read cache region with the effective data identification belongs to the same DDR Burst access as the write cache region read by the read-write module;

if yes, setting the data valid identification of the read buffer area which belongs to the same DDR Burst access with the read write buffer area and is valid as the valid data valid identification as the invalid data valid identification.

Further, the present embodiment also provides a memory, including the command read/write device as described in any one of the above.

The utility model has the advantages that:

the embodiment of the utility model provides a command read-write equipment, include: the system comprises a bus interface module 10, a cache control module 11, a cache module 12 and a read-write module 13; the cache control module 11 includes: a first cache control module 110 and a second cache control module 111; the cache module 12 includes: at least two read buffers 120, at least two write buffers 121; the bus interface module 10 is used for receiving a bus read/write command; the first buffer control module 110 is configured to write the received bus write commands belonging to the same burst DDRBurst access into the same write buffer 121; the second cache control module 111 is further configured to return data of the read cache region 120 that belongs to the same DDR Burst access as the bus read command; the read/write module 13 is configured to read the read buffer 120 or the write buffer 121 to perform a DDR Burst read or write operation. By the command read-write device, a plurality of small data read-write operation commands are combined together, the number of times of DDR Burst read-write operation needs to be initiated is reduced, the data read-write efficiency of the DDR memory is improved, and the waste of system resources is reduced.

Drawings

Fig. 1 is a schematic diagram of a basic structure of a command read/write apparatus according to a first embodiment of the present invention;

fig. 2 is a schematic diagram of a basic structure of a cache area according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a basic structure of a first cache control module according to a first embodiment of the present invention;

fig. 4 is a schematic diagram of a basic structure of a second cache control module according to a first embodiment of the present invention;

fig. 5 is a schematic diagram illustrating a plurality of bus commands being merged into one bus command according to a second embodiment of the present invention;

fig. 6 is a schematic diagram of splitting a read command transmitted across DDR bursts into two DDR Burst transmission read commands in the third embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are described in further detail below with reference to the accompanying drawings by way of specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The first embodiment is as follows:

the method aims to solve the problem that the efficiency of reading and writing a plurality of continuous small data volumes is low and the condition that the efficiency is not obviously improved by related technologies.

Referring to fig. 1, fig. 1 is a schematic diagram of a basic structure of a command reading/writing device according to an embodiment of the present invention; the command read-write device includes: the system comprises a bus interface module 10, a cache control module 11, a cache module 12 and a read-write module 13; the cache control module 11 includes: a first cache control module 110 and a second cache control module 111; the cache module 12 includes: at least two read buffers 120, at least two write buffers 121; the bus interface module 10 is configured to receive a bus read/write command; the first cache control module 110 is configured to write the received bus write commands belonging to the same Burst DDR Burst access into the same write cache area 121; the second cache control module 111 is configured to return data of the read cache region 120 that belongs to the same DDR Burst access as the bus read command; the read/write module 13 is configured to read the read buffer 120 or the write buffer 121 to perform a DDR Burst read or write operation.

In this embodiment, the number of the write buffers 121 in the cache module 12 is not limited, and preferably, there may be 16 write buffers 121, and each write buffer 121 includes but is not limited to the following information: the starting address addr, the command valid id c _ valid, the data register data, and the data valid id d _ valid, as shown in fig. 2. The data register data and the data valid flag d _ valid have an association relationship, and specifically, for example, when valid data exists in the data register data2, the data valid flag d _ valid2 is correspondingly set to be valid.

In this embodiment, the number of the read buffer areas 120 in the cache module 12 is not limited, and preferably, the number of the read buffer areas 120 is equal to the number of the write buffer areas 121, and there are 16 read buffer areas 120; each read cache 120 includes, but is not limited to, the following information: the starting address addr, the command valid id c _ valid, the data register data, and the data valid id d _ valid, as shown in fig. 2. It should be understood that only one data valid id d _ valid exists in one read buffer 120.

In this embodiment, the bus interface module 10 is connected to a bus and configured to receive a bus read/write command; wherein a bus includes but is not limited to: an AXI bus; the embodiment is not limited to the AXI bus, and may be a bus that can be used to send a read/write command to a cache region; it should be noted that the data length of each command in each read/write command sent by the bus is not limited; for example: the AXI bus may send a command with a data length of 2 first, and then the bus sends a command with a data length of 4; i.e. the data length of the commands sent by the bus may vary. In this embodiment, the bus interface module 10 is further configured to determine whether the received bus read/write command is transmitted across the DDRBurst, if so, split the received bus command into a plurality of sub-bus commands according to the DDRBurst address rule, and each split sub-bus command is no longer transmitted across the DDR Burst; specifically, for example, when the length of the DDR Burst data stored in the buffer is 8, the bus interface module 10 receives a bus command that 3 Byte data are sequentially read to an address starting from 0x06, and at this time, the bus interface module 10 determines that the command is transmitted across DDR bursts, and splits the command into: sequentially reading 2 Byte data to the address starting from 0x 06; and sequentially reading 1Byte datum from the address starting at 0x08, wherein the split command is not transmitted across DDR Burst. And sequentially executing the subsequent steps by the modules according to the split command.

It should be understood that the DDR Burst length of the read/write module 13 may be any one of 4, 8, and 16, and only the DDRBurst length setting rule is met, and it should be understood that the DDR Burst length of the read/write module 13 remains unchanged after the DDR Burst length setting is completed; it should be understood that the length of the DDR Burst data stored in each buffer of the buffer module 12 may be any one of 4, 8, and 16, the length of the DDR Burst data stored in each buffer is the same, and the length of the DDR Burst data stored in each buffer is also unchanged after the setting of the length of the DDR Burst data stored in each buffer is completed; preferably, the length of the DDR Burst data stored in each buffer is consistent with the DDRBurst length of the read-write module 13.

In this embodiment, as shown in fig. 3, the first cache control module 110 includes: a first writing module 1101, a first judging module 1102;

the first write module 1101 is configured to write a first bus write command into the first write buffer 121 when the bus interface module 10 receives the first bus write command, so that the first write buffer 121 and the first bus write command belong to the same DDR Burst access;

in this embodiment, specifically, for example, when the DDR Burst data length stored in the buffer is 8, the bus first write command is received: writing data d1 of 1Byte to 0x01 address; at this time, the bus first write command is to initiate a DDR Burst access to the address segment 0x0-0x07, that is, the DDR Burst start address of the bus first command is 0x 0; when the first determining module determines that there is no write cache region belonging to the same DDR Burst as the first write command, the first write module 1101 writes the first write command of the bus into the first write cache region 121, and it is necessary to execute the following steps, it should be understood that the following steps are not in order, and a specific execution order may be flexibly set by a relevant designer, and the steps are as follows:

the command valid flag c _ valid of the first write buffer 121 is set to valid; the start address addr of the first write buffer 121 is set to the same start address as the bus first write command: 0x 0; setting the data register data1 of the first write buffer 121 to d 1; setting the data valid identification d _ valid1 to valid; after the above operations are completed, the first bus write command is successfully written into the first write buffer 121.

It should be understood that, when setting each valid flag, it may be: when the level of the effective mark is low, the effective mark is judged to be effective, and when the level of the effective mark is high, the effective mark is judged to be invalid; the following steps can be also included: when the level of the valid flag is low, it is determined as invalid, and when the level of the valid flag is high, it is determined as valid. And are not limited herein.

In this embodiment, the first determining module 1102 is configured to determine whether the bus second write command and the first write buffer 121 belong to the same DDR Burst access when the bus interface module 10 receives the bus second write command;

in this embodiment, the first write module 1101 is further configured to, when the bus second write command belongs to the same DDR Burst access as the first write buffer 121, instruct the bus second write command to the first write buffer 121; specifically, for example, when the data length of the DDR Burst stored in the buffer area is 8, the start address addr of the first write buffer area 121 is: at 0x0, the second write command is to write 1Byte of data d3 to the address 0x03, and the starting address of the second write command is: 0x 0; after the bus interface module 10 receives the second bus write command, the first determining module 1102 determines that the second bus write command overlaps with the start address of the first write cache region 121, that is, the second bus write command and the first write cache region 121 belong to the same DDR Burst access, and at this time, the first write module 1101 writes the second bus write command into the first write cache region 121;

specifically, for example, when the length of the DDR Burst data stored in the buffer is 8, the starting address of the first write buffer 121 is: 0x 0; the bus interface module 10 receives a bus second write command: writing data d2 of 1Byte to 0x06 address; at this time, the bus second write command is to initiate DDR Burst access to the address segment 0x0-0x07, that is, the starting address of the bus second write command is 0x 0; when the first write module 1101 writes the second bus write command into the first write cache region 121, the following steps need to be executed, it should be understood that the following steps are not in sequence, and a specific execution sequence may be flexibly set by a relevant designer, and the steps are as follows:

setting the data register data6 of the first write buffer 121 to d 2; setting the data valid identification d _ valid6 to valid; after the above operations, the second bus write command is successfully written into the first write buffer 121. It should be understood that, in the second write of the bus write command, the command valid id c _ valid and the start address of the write buffer 121 do not need to be set again in the same write buffer.

In this embodiment, when the first determining module 1102 determines that the second bus write command and the first write buffer 121 do not belong to the same DDR Burst access, the first writing module 1101 writes the second bus write command into the second write buffer 121; specifically, for example, when the length of the DDR Burst data stored in the buffer area is 8, the start address addr of the first write buffer area 121 is: at 0x0, the second write command is to write 1Byte of data d3 to the address 0x09, and the starting address of the second write command is: 0x 8; after the bus interface module 10 receives the second bus write command, the first determining module 1102 determines that the second bus write command does not overlap with the start address of the first write cache region 121, and the second bus write command and the first write cache region 121 do not belong to the same DDR Burst access, at this time, the first write module 1101 writes the second bus write command into the second write cache region 121;

specifically, for example, when the length of the DDR Burst data stored in the buffer is 8, the bus interface module 10 receives a second write command: writing data d9 of 1Byte to 0x09 address; at this time, the bus second write command is to initiate DDR Burst access to the address segment 0x08-0x0f, that is, the starting address of the bus second command is 0x 08; when the first write module 1101 writes the second bus write command into the second write cache region 121, the following steps need to be executed, it should be understood that the following steps are not in sequence, and a specific execution sequence may be flexibly set by a relevant designer, and the steps are as follows:

the command valid flag c _ valid of the second write buffer 121 is set to valid; the start address addr of the second write buffer 121 is set to the same start address as the bus second write command: 0x 08; the data register data1 of the second write buffer 121 is set to d 9; setting the data valid identification d _ valid1 to valid; after the above operations, the second bus write command is successfully written into the second write buffer 121.

It should be understood that, when the bus interface module 10 receives a bus write command, the first determining module 1102 needs to sequentially perform whether the start addresses of all the write cache regions 121 with valid command flags c _ valid are overlapped, until a write cache region 121 with the same start address is found, and the first writing module 1101 adds the received bus write command to the write cache region 121 with the overlapped start addresses; or after the first determining module 1102 determines that all the write buffers 121 with valid command flags c _ valid are valid, and if there is no write buffer 121 overlapping with the start address of the bus write command, the first writing module 1101 adds the received bus write command to the write buffer 121 with invalid command flags c _ valid.

Specifically, for example, when 16 write cache regions 121 exist in the cache module 12, wherein the command valid identifiers c _ valid of the first write cache region 121 to the eighth write cache region 121 are valid, and the bus interface module 10 receives a third bus write command, the first determining module 1102 needs to sequentially determine whether the start address of the third bus write command overlaps with the start addresses of the first write cache region 121 to determine whether the start addresses overlap, and if the write cache regions 121 with the same start address, that is, overlapping are found, the first determining module 1102 adds the third bus write command to the write cache regions 121 with the same start address; or the first determining module 1102 sequentially determines whether the start address of the third bus write command overlaps with the start addresses of the first to eighth write buffers 121, and if no write buffer 121 with the same start address is found, the first writing module adds the third bus write command to any unused ninth to sixteenth write buffers 121.

In this embodiment, as shown in fig. 4, the second cache control module 111 includes: a second judgment module 1111 and a data return module 1112; the second determining module 1111 is configured to determine whether there is a used read buffer 120 that belongs to the same DDRBurst access as the bus read command;

in the present embodiment, the used read buffers 120 include, but are not limited to, any of the following read buffers 120: the data valid id d _ valid is valid for the read buffer 120, and the command valid id c _ valid is valid for the read buffer 120. That is, when a bus read command is received, it is only compared with the start address of the used read buffer 120, and it is not required to be compared with the start address of the unused read buffer 120.

In this embodiment, the data returning module 1112 is configured to, when there is a used read buffer 120 belonging to the same DDR Burst access as the bus read command, take the used read buffer 120 belonging to the same DDR Burst access as the bus read command as the first read buffer 120, and return the data of the first read buffer 120.

In this embodiment, the second determining module 1111 is further configured to determine whether the data valid flag of the first read buffer 120 is valid; the data returning module 1112 is configured to return the data of the first read buffer 120 when the data valid identifier of the first read buffer 120 is valid; the data returning module 1112 is further configured to return the data of the first read buffer 120 when the data valid flag of the first read buffer 120 changes from invalid to valid.

In this embodiment, after the second determining module 1111 takes the used read buffer 120 that belongs to the same DDR Burst access as the bus read command as the first read buffer 120, and before the data returning module 1112 returns the data of the first read buffer 120, the second determining module 1111 is further configured to determine whether the data valid identifier d _ valid of the first read buffer 120 is valid; if so, the data return module 1112 may immediately return the data in the first read buffer 120 corresponding to the read address of the bus read command message; if not, the data returning module 1112 waits for the valid data flag of the first read buffer 120 to be valid, and returns the data corresponding to the read address of the bus read command message in the first read buffer 120.

Specifically, for example, when the length of the DDRBurst data stored in the buffer is 8, the bus interface module 10 receives a bus read command to read 1Byte data to an address of 0x03, where the starting address of the bus read command is: 0x 0; after the bus interface module 10 receives the bus read command, the second determining module 1111 determines that the bus read command overlaps with the start address of the first read buffer 120, that is, the bus read command and the first read buffer 120 belong to the same DDR Burst access, and when determining that the data valid identifier d _ valid of the first read buffer 120 is valid, the data returning module 1112 directly returns the data of the data register data3 in the first read buffer 120 as the read data; if the second determining module 1111 determines that the data valid id d _ valid of the first read buffer 120 is invalid, the data returning module 1112 waits for the data valid id d _ valid of the first read buffer 120 to become valid, and then returns the data of the data register data3 in the first read buffer 120 as the read data.

The second cache control module 111 further includes: a second write module 1113, where the second write module 1113 is configured to identify a valid bus read command as the invalid read buffer 120, identify the read buffer 120 written with the bus read command as the second read buffer 120, and identify a valid bus read command of the second read buffer 120 as valid after the bus read command is written;

in this embodiment, when the second determining module 1111 determines that there is no used read buffer 120 that belongs to the same DDRBurst access as the bus read command, the second writing module 1113 identifies the valid bus read command write command as the invalid read buffer 120, and identifies the read buffer 120 in which the bus read command is written as the second read buffer 120, and the valid bus read command of the second read buffer 120 is identified as valid;

specifically, for example, when the length of the DDR Burst data stored in the buffer is 8, the bus interface module 10 receives a bus read command: sequentially reading 3 Byte data from 0x01 address, wherein the bus read command initiates DDR Burst access to 0x0-0x07 address segment, and the starting address of the bus read command is 0x 0; when the second determining module 1111 determines that there is no used read buffer 120 with the start address of 0x0, the second writing module 1113 needs to add the bus read command with the read buffer 120 with the invalid command valid identifier c _ valid; when the bus read command is written into the read cache region 120, the following steps need to be executed, it should be understood that the following steps are not in sequence, and the specific execution sequence can be flexibly set by a relevant designer, and the following steps are executed:

setting the command valid flag c _ valid of the second read cache 120 to valid; the start address addr of the second read cache region 120 is set to the same start address as the bus read command: 0x 0.

It is to be understood that, in some embodiments, the second write module 1113 preferentially writes the bus read command into the unused read buffer 120 when the bus read command adds the read buffer 120 whose command valid identifier c _ valid is invalid; when there is no unused read buffer 120 in the cache module 12, the write command valid id c _ valid is an invalid used read buffer 120.

It should be understood that, when the read/write module 13 reads the read buffer 120 or the write buffer 121 to perform the DDR Burst read or write operation, at the same time, only the read buffers 120 in the read buffer or the write buffers 121 in the read/write buffer 121 can be read, for example, one write buffer 121 in the read/write buffer 121 performs the corresponding DDR Burst write operation; or one read buffer 120 in the read buffer 120 performs the corresponding DDR Burst read operation.

In this embodiment, the read/write module 13 reads the write buffer 121 where only the read command valid identifier c _ valid is valid when the write buffer 121 executes the DDR Burst write operation; specifically, for example, there are 16 write buffers 121, where only the command valid id c _ valid of the first write buffer 121 is valid, the read/write module 13 reads the first write buffer 121 where the command valid id c _ valid is valid, when the data valid ids d _ valid1 and d _ valid3 in the first write buffer 121 are valid, the read/write module 13 reads the data in the data registers data1 and data3 to perform a DDR Burst write operation, after the read by the read/write module 13 is completed, the command valid id c _ valid of the first write buffer 121 is set to invalid, and the data valid ids d _ valid1 and d _ valid3 of the first write buffer 121 are set to invalid.

In this embodiment, when the read/write module 13 reads the read cache region 120 and performs the DDR Burst read operation, only the command valid identifier c _ valid is valid, specifically, for example, there are 16 read cache regions 120, where only the command valid identifier c _ valid of the first read cache region 120 is valid, the read/write module 13 reads the command valid identifier c _ valid as the valid first read cache region 120, and performs the read operation according to the starting address addr of the first read cache region 120, and after the read/write module 13 completes the read operation, the following steps need to be performed, it needs to be understood that the following steps are not ordered, and the specific execution order may be flexibly set by a relevant designer, and the steps are as follows:

the read data are sequentially added to the data register data of the first read buffer 120, the command valid identifier c _ valid of the first read buffer 120 is set to invalid, and the data valid identifier d _ valid of the first read buffer 120 is set to valid.

It should be understood that, after the read/write module 13 reads the read buffer 120 to perform the DDR Burst read operation, the read data is sequentially added to the data register data of the first read buffer 120, the command valid identifier c _ valid of the first read buffer 120 is set to be invalid, and after the data valid identifier d _ valid of the first read buffer 120 is set to be valid, the data corresponding to each read command in the data register data needs to be returned.

It should be understood that, the read/write module 13 takes the information of the valid command identifier c _ valid as an effective buffer area, and when a corresponding DDR Burst read or write operation is executed, the information of the valid command identifier c _ valid as an effective buffer area may be taken according to the sequence of the valid command identifiers c _ valid of the buffer areas to execute a corresponding command, or the information of the valid command identifiers c _ valid as an effective buffer area may be taken according to the sequence of other bus-tagged commands to execute a corresponding command; it should be understood that, this embodiment is not used to limit the fetching sequence of the cache area in which the specific fetching command valid identifier c _ valid is valid, and may be flexibly set by the relevant designer.

In this embodiment, when the read/write module 13 takes away the write buffer 121 whose command valid identifier c _ valid is valid, the buffer control module 11 is further configured to determine whether the write buffer 121 and any read buffer 120 whose data valid identifier is valid belong to the same DDR Burst access; if so, the cache control module 11 clears the data valid flag of the read cache 120 belonging to the same DDR Burst access as the write cache 121. Specifically, for example, when the read/write module 13 takes away the first write cache region 121, the cache control module 11 compares the start address addr of the first write cache region 121 with the start address addr of the read cache region 120, and when the cache control module 11 determines that the start address addr of the read cache region 120 is the same as the start address addr of the taken-away write cache region 121 and the data valid identifier of the read cache region 120 is valid, the cache control module 11 clears the data valid identifier of the read cache region 120 or sets the data valid identifier as invalid.

The embodiment of the utility model provides a command read-write equipment, include: the system comprises a bus interface module 10, a cache control module 11, a cache module 12 and a read-write module 13; the cache control module 11 includes: a first cache control module 110 and a second cache control module 111; the cache module 12 includes: at least two read buffers 120, at least two write buffers 121; the bus interface module 10 is used for receiving a bus read/write command; the first buffer control module 110 is configured to write the received bus write commands belonging to the same burst DDRBurst access into the same write buffer 121; the second cache control module 111 is further configured to return data of the read cache region 120 that belongs to the same DDR Burst access as the bus read command; the read/write module 13 is configured to read the read buffer 120 or the write buffer 121 to perform a DDR Burst read or write operation. By the command read-write device, a plurality of small data read-write operation commands are combined together, the number of times of DDR Burst read-write operation needs to be initiated is reduced, the data read-write efficiency of the DDR memory is improved, and the waste of system resources is reduced.

Example two:

for convenience of understanding, the present embodiment describes a command read/write apparatus by using a more specific example, specifically, the command read/write apparatus includes: the system comprises a bus interface module 10, a cache control module 11, a cache module 12 and a read-write module 13; the cache control module 11 includes: a first cache control module 110; the cache module 12 includes: at least two write buffers 121; the first cache control module 110 includes: a first writing module 1101, a first judging module 1102;

the bus interface module 10 is configured to receive a bus write command, when the read-write module 13 of the DDR memory is in a non-idle state, the first determining module 1102 determines whether a write address region in the bus write command overlaps with an address region in a write cache region write, and the first write-in module 1101 is configured to set a write cache region write slice used according to the bus write command when the first determining module 1102 determines that the bus write command overlaps with a write cache region write slice address region used; the first writing module 1101 is further configured to set an unused write buffer write slice according to the bus write command when the first determining module 1102 determines that the bus write command does not overlap with an address area of the used write buffer write slice. Preferably, in this embodiment, there are 16 write buffer slices, and each write buffer stores the following information: the starting address addr, the command valid identifier c _ valid, the data register data and the data valid identifier d _ valid; the write buffer write slice is determined as a valid write buffer write slice if the command valid id c _ valid in the write buffer write slice is valid, that is, the write buffer write slice is used, the write buffer write slice is determined as an invalid write buffer write slice if the command valid id c _ valid is invalid, that is, the write buffer write slice is not used, and the sum of the number of the used write buffer write slices and the number of the unused write buffer write slices is 16.

In this embodiment, the following may be specifically mentioned: when the DDR SDRAM read-write control logic is in a busy state, that is, the read-write module 13 is in a busy state, for example, in a phase of sending an active command, the bus interface module 10 receives bus write commands with three non-consecutive addresses successively, where the first write command of the bus is to write 1Byte data d1 to 0x01 address, the second write command of the bus is to write 1Byte data d3 to 0x03 address, and the third write command of the bus is to write 1Byte data d5 to 0x05 address. As shown in fig. 5, the cache control module 11 adds three bus write commands to one write buffer write slice, so that the three bus write commands are merged into 1 DDR Burst write command, which is as follows: the first determining module 1102 determines that there is a write buffer write slice0 overlapping the first write command address region of the bus, where the starting address addr of the write buffer write slice0 is 0x00, the first writing module 1101 is configured to store the data register data of 0x01 address in the write buffer write slice0 into the data d1 according to the first write command of the bus and set the data valid flag 63d valid1 of 0x01 address as valid when the first determining module 1102 determines that there is a write buffer write slice writen 25 overlapping the first write command address region of the bus, and the first writing module 1101 is configured to store the data register data of 0x03 address in the write buffer write slice0 into the data valid register 3 according to the second write command of the bus and set the data flag data valid flag 3884 as valid data register data when the first determining module 1102 determines that the write address region of the second write command overlaps the address region of the write buffer write slice0, the first write module 1101 is configured to, when the first determining module 1102 determines that the write address area of the third write command of the bus overlaps with the address area of the write buffer slice0, store the data register data of 0x05 address in the write buffer slice0 into the data d5 according to the third bus write command, and set the data valid flag d _ valid5 of 0x05 address as valid, when the DDR SDRAM read-write control logic is in an idle state, that is, when the read-write module 13 is in an idle state, the read-write module 13 recognizes that the command valid flag c _ valid of the write buffer slice0 is valid, obtain data in the data register data according to the valid data valid flags d _ valid in the write buffer slice0, and control the analog circuit PHY to implement write the DDR Burst according to the write buffer slice0, where the write valid data in the write buffer slice0 is written immediately after the ddrsrs cache control logic takes the write buffer information away, while the command valid flag c _ valid is set to invalid. The DDR Burst write operation is initiated once, the original write command needing to initiate three DDR bursts is processed, and the efficiency is greatly improved;

it should be noted that the first writing module 1101 is further configured to set the unused write buffer write slice1 according to the bus first write command when the first determining module 1102 determines that the write buffer write slice does not have an address area overlapping with the write address area of the bus first write command, so that the start address of the write buffer write slice1 is 0x00, and at this time, the first determining module 1102 can determine that the write address areas of the second and third bus write commands overlap with the write buffer write 1 address area.

The embodiment of the utility model provides a command read-write equipment, include: the system comprises a bus interface module 10, a cache control module 11, a cache module 12 and a read-write module 13; the cache control module 11 includes: a first cache control module 110; the cache module 12 includes: at least two write buffers 121; the bus interface module 10 is used for receiving a bus read/write command; the first cache control module 110 is configured to write the received bus write commands belonging to the same Burst DDR Burst access into the same write cache area 121; the read/write module 13 is configured to read the write buffer 121 and perform a DDR Burst write operation. By the command read-write device, a plurality of small data write operation commands are combined together, the number of times of DDR Burst write operation needs to be initiated is reduced, the data write efficiency of the DDR memory is improved, and the waste of system resources is reduced.

EXAMPLE III

For convenience of understanding, the present embodiment describes, by using a more specific example, a command read/write apparatus, where the command read/write apparatus includes: the system comprises a bus interface module 10, a cache control module 11, a cache module 12 and a read-write module 13; the cache control module 11 includes: a second cache control module 111; the cache module 12 includes: at least two read buffers 120; the second cache control module comprises: a second determination module 1111, a data return module 1112, and a second write module 1113.

The bus interface module 10 receives a bus read command, the second judging module 1111 is configured to judge whether a read address region in the bus read command overlaps with an address region in a read slice of a read buffer, and the data returning module 1112 is configured to obtain data return of the read slice address region when the read address region in the bus read command overlaps with the read slice address region of the used read buffer; the second write module 1113 is configured to set an unused read buffer read slice according to the DDR Burst read command when there is no overlap between a read address region in the bus read command and a read buffer read slice address region already used. Preferably, in this implementation, there are 16 read buffers, and each read buffer stores DDR Burst read operation information, where the DDR Burst read operation information includes: the starting address addr, the command valid identifier c _ valid, the data register data and the data valid identifier d _ valid; the method includes that a command valid identifier c _ valid or a data valid flag d _ valid in a read slice of a read cache is valid read slice, namely the read slice of the read cache is used, the command valid identifier c _ valid and the data valid flag d _ valid are both invalid read slice of the invalid read cache, namely the read slice of the unused read cache, and the sum of the number of the used read slice and the number of the unused read slice of the read cache is 16. In this embodiment, the following may be specifically mentioned: the bus interface module 10 receives two bus read commands sequentially, wherein the first bus read command is to read 3 bytes of data sequentially from the beginning address of 0x06, and the second bus read command is to read 1Byte of data from the beginning address of 0x 03.

As shown in fig. 6, after receiving the two commands, the bus interface module 10 determines that the address of the first read command of the bus is transmitted across the DDR Burst, so that the first read command is split into the sub-bus read command 1: reading the data of 2 bytes in sequence to the address starting at 0x06, sub-bus read command 2: reading 1Byte of data to an address of 0x 08;

the second judging module 1111 judges that there is no read buffer read slice whose address region overlaps with the read address region of the sub-bus read command 1, and there is a read buffer readslice0 whose address region overlaps with the read address region of the sub-bus read command 2;

the second write-in module 1113 is configured to set, according to the sub-bus read command 1, the unused read slice1 of the read buffer, set the command valid identifier c _ valid of the read slice1 to be valid, and set the starting address of the read slice1 to be 0x 00; according to the sub-bus read command 2, the data returning module 1112 waits for the read operation of the read buffer slice0 to be completed and then returns the data of the buffer as read data.

The second writing module 1113 is further configured to, when the second determining module 1111 determines that the address area of the read buffer read slice1 is overlapped with the bus second read command read address area, return the data of the read buffer read slice1 as read data after the read operation of the read buffer read slice1 is completed.

When the DDR SDRAM read-write control logic is in an idle state, that is, when the read-write module 13 is idle, the read-write module 13 recognizes that c _ valid of the read buffer 0 is valid, then takes away the DDR Burst read information, initiates a read operation with a DDR Burst length of 8 starting addresses of 0x00 to the DDR SDRAM according to the DDR Burst read information, sets the command valid identifier c _ valid in the read buffer 0 to invalid after the read operation is completed, sets the data valid identifier d _ valid in the read buffer 0 to valid, and sequentially adds the read data to the data register data of the read buffer 0. Then, the DDR SDRAM read-write control logic determines that c _ valid of the read slice1 buffer is valid, so a read operation with a DDR Burst length of 8 and an initial address of 0x08 is initiated again, after the read operation is completed, the command valid identifier c _ valid in the read slice1 of the read buffer is set to invalid, and meanwhile, the data valid identifier d _ valid in the read buffer 1 is set to valid, and the read data are sequentially added to the data register data of the read buffer readslice 1. Thus, the data of the first bus read command and the second bus read command are all read back.

The embodiment of the utility model provides a command read-write equipment includes: the system comprises a bus interface module 10, a cache control module 11, a cache module 12 and a read-write module 13; the cache control module 11 includes: a second cache control module 111; the cache module 12 includes: at least two read buffers 120; the bus interface module 10 is used for receiving a bus read command; the second cache control module 111 is configured to return data of the read cache region 120 that belongs to the same DDR Burst access as the bus read command; the read-write module 13 is configured to read the read buffer 120 to perform a DDR Burst read operation. By the command read-write device, a plurality of small data read operation commands are combined together, so that the frequency of DDR Burst read operation is reduced, the data read efficiency of a DDR memory is improved, and the waste of system resources is reduced.

It will be apparent to those skilled in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software (which may be implemented in computer program code executable by a computing device), firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.

In addition, communication media typically embodies computer readable instructions, data structures, computer program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to one of ordinary skill in the art. Thus, the present invention is not limited to any specific combination of hardware and software.

The foregoing is a more detailed description of embodiments of the present invention, and the specific embodiments are not to be considered in a limiting sense. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.

Claims (10)

1. A command read/write apparatus comprising: the system comprises a bus interface module, a cache control module, a cache module and a read-write module; the cache control module comprises: the system comprises a first cache control module and a second cache control module; the cache module comprises: at least two read buffers, at least two write buffers;

the bus interface module is used for receiving a bus read/write command;

the first cache control module is used for writing the received bus write commands which belong to the same Burst DDR Burst access into the same write cache region;

the second cache control module is used for returning data of a read cache region accessed by the same DDR Burst as the bus read command;

the read-write module is used for reading the read cache region or the write cache region and executing DDR Burst read or write operation.

2. The command read/write apparatus of claim 1, wherein each read buffer includes the following information: the system comprises a starting address, a command valid identifier, a data register and a data valid identifier;

each write buffer includes the following information: the system comprises a starting address, a command valid identifier, a data register and a data valid identifier.

3. The command read/write apparatus according to claim 2, wherein the first cache control module comprises: the device comprises a first writing module and a first judging module;

the first write-in module is used for writing a first bus write command into a first write cache region when the bus interface module receives the first bus write command, so that the first write cache region and the first bus write command belong to the same DDRBurst access;

the first judging module is used for judging whether the bus second write command and the first write cache region belong to the same DDR Burst access or not when the bus interface module receives the bus second write command;

the first write-in module is further configured to write the second bus write command into the first write cache region when the second bus write command and the first write cache region belong to the same DDRBurst access;

the first write-in module is further configured to write the second bus write command into a second write cache region when the second bus write command and the first write cache region do not belong to the same DDRBurst access.

4. The command read/write apparatus according to claim 2, wherein the second cache control module comprises: the second judgment module and the data return module;

the second judging module is used for judging whether a used read cache region which belongs to the same DDR Burst access with the bus read command exists or not;

and the data return module is used for taking the used read cache region which belongs to the same DDR Burst access with the bus read command as a first read cache region and returning the data of the first read cache region when the used read cache region which belongs to the same DDR Burst access with the bus read command exists.

5. The command read/write apparatus of claim 4, wherein the used read buffer includes: and any one of the data valid identifier or the command valid identifier is a valid read buffer.

6. The command read-write apparatus according to claim 5, wherein the second determining module is further configured to: judging whether the data valid identification of the first read cache region is valid;

the data returning module is used for returning the data of the first read cache region when the data valid identification of the first read cache region is valid;

the data returning module is used for returning the data of the first read cache region when the data valid identification of the first read cache region is changed from invalid to valid.

7. The command read-write apparatus according to claim 6, wherein the second cache control module further comprises: a second write module;

the second write-in module is configured to write the bus read command into a read cache area with an invalid valid identifier, use the read cache area written into the bus read command as a second read cache area, and write the bus read command into the second read cache area with a valid identifier as a valid identifier.

8. The command read-write apparatus according to any one of claims 1 to 7, wherein the bus interface module is further configured to:

judging whether the bus read/write command crosses DDR Burst transmission or not;

if yes, the bus read/write command is split into a plurality of sub-bus read/write commands according to the DDRBurst address rule, and the split sub-bus read/write commands are not transmitted across the DDR Burst.

9. The command read-write apparatus according to claim 8, wherein the cache control module is further configured to:

judging whether the read cache region with the effective data identification belongs to the same DDRBurst access as the write cache region read by the read-write module;

if yes, setting the data valid identification of the read buffer area which belongs to the same DDR Burst access with the read write buffer area and is valid as the valid data valid identification as the invalid data valid identification.

10. A memory comprising a command read/write apparatus according to any one of claims 1 to 9.

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