CN114817114B

CN114817114B - MIPI interface, control method, device and medium thereof

Info

Publication number: CN114817114B
Application number: CN202210520091.6A
Authority: CN
Inventors: 王锐; 张齐; 王亚波; 李建军; 莫军
Original assignee: Guangxin Microelectronics Suzhou Co ltd
Current assignee: Guangxin Microelectronics Suzhou Co ltd
Priority date: 2022-05-13
Filing date: 2022-05-13
Publication date: 2023-08-15
Anticipated expiration: 2042-05-13
Also published as: CN114817114A

Abstract

The application relates to the technical field of integrated circuits, and provides an MIPI interface aiming at the problem that an MCU resource is occupied by an MIPI signal which is analyzed and simulated in a software mode through an MCU at present, comprising the following steps: MIPI bus, multiple buffers, state machine, transmitting data processing module, receiving data processing module and SRAM; when external equipment inputs data, a received data processing module analyzes and obtains serial data and state codes; the state machine performs state jump according to the state code, and the received data processing module converts serial data into byte data according to the current state of the state machine; when the MCU outputs data, the transmitting data processing module obtains the data written by the MCU from the SRAM and outputs the data through the MIPI bus. The application realizes the conversion of MIPI signals and byte data through the hardware device, and does not need MCU to simulate and analyze MIPI signals in a software mode, thereby saving the running resources of MCU and improving the efficiency.

Description

MIPI interface, control method, device and medium thereof

Technical Field

The present application relates to the field of integrated circuits, and in particular, to an MIPI interface, and a control method, apparatus, and medium thereof.

Background

With the high-speed development of information technology and mobile portable devices, the requirements of people on the mobile devices are higher and higher, and the power consumption of the mobile devices is reduced as much as possible on the premise of meeting the high-performance display effect. Currently, a video interface which is the mainstream in the mobile field uses a mobile industry processor (Mobile Industry Processor Interface, MIPI) interface, wherein MIPI defines an interface specification for high-speed data transmission and low-power transmission, and MIPI D-PHY is a physical layer standard of MIPI interface. In the practical application of MIPI, there is an application occasion that only needs to support MIPI low power consumption mode data, where the application occasion needs to operate in a low speed mode, at present, a micro control unit (Microcontroller Unit, MCU) generally uses a General-purpose input/output (GPIO) to simulate a bus signal of MIPI to output, and obtains edge information of GPIO when data is received, and uses an MCU timer to obtain a manner of MIPI timing, that is, the MCU analyzes the low speed signal of the MIPI bus in a pure software manner.

The method for analyzing the low-speed signal of the MIPI bus by the MCU in a pure software mode can occupy a large amount of resources of the MCU and influence the processing efficiency and the processing speed of the MCU.

Therefore, a need exists for an MIPI interface that solves the problem that resolving the low-speed signal of the MIPI bus by the MCU in a pure software manner occupies a lot of resources of the MCU and affects the processing efficiency and rate of the MCU in low cost applications where only MIPI low power modes need to be supported.

Disclosure of Invention

The application aims to provide an MIPI interface, and a control method, a device and a medium thereof, which solve the problems that the low-speed signal of an MIPI bus is analyzed by an MCU in a pure software mode, so that a large amount of resources of the MCU are occupied and the processing efficiency and the speed of the MCU are affected.

In order to solve the above technical problems, the present application provides an MIPI interface, including: MIPI bus, multiple buffers, state machine, transmitting data processing module, receiving data processing module and SRAM;

the MIPI bus is connected with external equipment, is connected with a receiving data module through at least one buffer, is connected with a transmitting data processing module through other buffers, is connected with the output end of the buffer, and is connected with the input end of the buffer; the enabling end of each buffer is connected with the state machine and is used for receiving a direction control signal sent by the state machine; the receiving data processing module is connected with the state machine and the SRAM, and is used for analyzing the data sent by the MIPI bus to obtain serial data and state codes, converting the serial data into byte data according to the state of the state machine and sending the byte data to the SRAM; the transmitting data processing module is connected with the SRAM and is used for transmitting data to be transmitted in the SRAM to the MIPI bus; the SRAM is connected with the MCU.

Preferably, the method further comprises: the receiving matching registers are connected with the receiving data processing module and the SRAM, and each receiving matching register is used for matching MIPI long packets or MIPI short packets; when one path of receiving matching register is successfully matched, the receiving matching register is also used for generating an interrupt signal and a matching mark, wherein the interrupt signal is used for interrupting the current process of the MCU, and the matching mark is used for indicating the MCU to find the memory address of the MIPI signal successfully matched in the SRAM.

Preferably, the method further comprises: an SRAM configuration register storing SRAM space configuration information; the SRAM configuration register is connected with the MCU, and the MCU can divide the space of the SRAM into a plurality of groups according to the space configuration information of the SRAM.

Preferably, the connection between the SRAM and the MCU is specifically: the SRAM is connected with an AHB interface of the MCU through an AHB bus.

Preferably, the method further comprises: the ECC calculation module is connected with the SRAM, is used for calculating the header ECC value of the byte data, compares the header ECC value with the received ECC value, and generates a corresponding state identifier according to a comparison result, so that the MCU can conveniently and correspondingly process the byte data according to the state identifier; the ECC calculation module is also used for calculating the header ECC value of the data to be transmitted and replacing the data of the ECC bits.

Preferably, the method further comprises: a transmission configuration register storing transmission data configuration information; the transmitting configuration register is connected with the MCU and the transmitting data processing module.

Preferably, the SRAM is powered independently.

In order to solve the technical problem, the present application further provides a control method of an MIPI interface, which is applied to the MIPI interface, including: when receiving data input by an external device, the state machine sends a direction control signal to control a buffer arranged between the MIPI bus and the received data processing module to be in an enabling state; the received data processing module analyzes data input by external equipment to obtain serial data and state codes; the state machine performs state jump according to the state code, and the receiving data processing module converts serial data into byte data according to the current state of the state machine and sends the byte data to the SRAM so that the MCU can acquire the byte data by reading the SRAM; when receiving data sent by the MCU, the transmitting data processing module acquires the data sent by the MCU from the SRAM; the state machine sends a direction control signal to control a buffer disposed between the MIPI bus and the transmit data processing module to an enabled state.

In order to solve the technical problem, the present application further provides a control device of an MIPI interface, including: a memory for storing a computer program; and a processor for implementing the steps of the MIPI interface control method when executing the computer program.

In order to solve the above technical problem, the present application further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the control method of the MIPI interface as described above.

The MIPI interface provided by the application controls the enabling states of different buffers to switch the MIPI bus to be in an input state or an output state through a state machine so as to receive data input by external equipment or output data to the external equipment; when external equipment inputs data, the MIPI bus sends the data to a received data processing module, and the received data processing module analyzes the data to obtain analyzed serial data and state codes; the state machine performs state jump according to the state code, and the received data processing module converts serial data into byte data according to the current state of the state machine and sends the byte data to a Static Random-Access Memory (SRAM) for storage; since the MCU is directly connected with the SRAM, the MCU can freely read data from the SRAM or write data into the SRAM; when the MCU writes data into the SRAM, the state machine controls the buffer to enable the MIPI bus to be switched into an output state, and the transmitting data processing module obtains the data written by the MCU from the SRAM and outputs the data to the external device through the MIPI bus, so that the effect of data transmission between the external device and the MCU through the MIPI interface is achieved. Meanwhile, according to the MIPI interface provided by the application, the externally input data based on the MIPI interface protocol is converted into the byte data which can be directly read by the MCU and stored in the SRAM through hardware devices such as the state machine, the receiving data processing module and the like, the MCU can directly perform read-write operation on the SRAM, the MCU does not need to simulate a MIPI bus signal in a software mode when sending the data, and the low-speed signal of the MIPI bus is not needed to be analyzed through the edge information of the GPIO and the MIPI time sequence when receiving the data, so that the running resources of the MCU are greatly saved, and the working efficiency of the MCU is improved. The MIPI interface provided by the application can be designed by RTL, and a final circuit is generated by a comprehensive tool, so that the MIPI interface can be reused on different process platforms, and MCU integration is facilitated.

The MIPI interface control method, device and computer readable storage medium provided by the application correspond to the MIPI interface, and have the same effects.

Drawings

For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

Fig. 1 is a schematic structural diagram of an MIPI interface provided by the present application;

fig. 2 is a flowchart of a data receiving method of an MIPI interface provided by the present application;

fig. 3 is a flowchart of a data transmission method of an MIPI interface provided by the present application;

fig. 4 is a block diagram of a data transmitting apparatus of an MIPI interface provided by the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.

The application provides an MIPI interface, a control method, a control device and a medium thereof.

In order to better understand the aspects of the present application, the present application will be described in further detail with reference to the accompanying drawings and detailed description.

In the current field of mobile devices, MIPI-based interfaces are commonly used in order to achieve high performance display effects and to reduce the power consumption of the mobile device as much as possible. The typical application is the processor of the mobile phone, integrates the MIPI interface module, and supports the complete interface protocol of MIPI. And a specially designed MIPI interface conversion chip which can also support the complete interface protocol of MIPI and convert MIPI signals into parallel data. However, in an application occasion that only needs to support the data of the MIPI low power consumption mode, the MIPI interface module and the MIPI interface conversion chip cannot meet the requirements of low cost and low power consumption, so at present, a mode that an MCU simulates and analyzes a low-speed signal of a MIPI bus in a pure software mode is generally adopted, and the mode needs to occupy a large amount of running resources of the MCU, so that the processing efficiency and the processing speed of the MCU are greatly affected.

Accordingly, the present application provides an MIPI interface, as shown in fig. 1, comprising: MIPI bus 101, a plurality of buffers (i.e., MIPI bus direction switch module 102), state machine 103, transmit data processing module 104, receive data processing module 105, and SRAM106;

the MIPI bus 101 is connected with the external device 107, and is connected with a receiving data module through at least one buffer, and is connected with a transmitting data processing module 104 through other buffers, and the receiving data module is connected with the output end of the buffer, and the transmitting data module is connected with the input end of the buffer; the enabling end of each buffer is connected with the state machine 103 and is used for receiving a direction control signal sent by the state machine 103; the received data processing module 105 is connected with the state machine 103 and the SRAM106, and is used for analyzing the data sent by the MIPI bus 101 to obtain serial data and state codes, converting the serial data into byte data according to the current state of the state machine 103 and sending the byte data to the SRAM106; the transmitting data processing module 104 is connected with the SRAM106 and is used for transmitting data to be transmitted in the SRAM106 to the MIPI bus 101; SRAM106 is connected to MCU 108.

MCU108 is connected with external device 107 through the MIPI interface, when external device 107 inputs data to MCU108, state machine 103 sends direction control signal to control corresponding buffer to enable so that MIPI bus 101 data flow is from external device 107 to received data processing module 105, i.e. MIPI bus 101 is switched to input mode; while when MCU108 outputs data to external device 107, state machine 103 sends a direction control signal to control the further buffer enable such that the data flow of MIPI bus 101 is switched from transmit data processing module 104 to external device 107, i.e. MIPI bus 101 is switched to output mode. The buffers mainly play a role of controlling the data flow direction of the MIPI bus 101 according to the direction control signal sent by the state machine 103, so in fig. 1, a plurality of buffers are denoted by MIPI bus direction switching module 102.

When the direction of the MIPI bus 101 can be switched as required and the external device 107 inputs data, the received data processing module 105 receives and parses the input MIPI signal to obtain serial data and a status code of the MIPI signal, the state machine 103 performs a status jump according to the received status code, and the received data processing module 105 converts the parsed serial data into byte data according to the current status of the state machine 103 and outputs the byte data to store in the SRAM106;

the SRAM106 is directly connected to the MCU108, and the MCU108 can freely read data from or write data to the SRAM106, so as to receive the MIPI signal input from the external device 107. When the MCU108 needs to output to the external device 107, it is only necessary to write data into the SRAM106, and the transmission data processing module 104 obtains data from the SRAM106 and sends the data to the external device 107 through the MIPI bus 101.

It should be noted that, since the received data processing module 105 stores data in the SRAM106, as shown in fig. 1, a possible implementation manner is that the state code resolved by the received data processing module 105 is also stored in the SRAM106, and the state machine 103 is connected to the SRAM106 for obtaining the state code.

The present example also provides a preferred embodiment of the connection of SRAM106 to MCU108, with SRAM106 being connected to the AHB interface of MCU108 via AHB bus 109.

Since in the current field of mobile portable devices, high performance modules such as MCU108 are typically integrated with an advanced high performance bus (Advanced High Performance Bus, AHB) interface, the connection to other high performance modules is through AHB bus 109. So the SRAM106 can be directly connected with the MCU108 through the AHB bus 109, which is convenient for integrating the MIPI interface and the chip provided by the application. Further, for the same purpose, SRAM106 may also be connected to MCU108 through a peripheral bus (Advanced Peripheral Bus, APB), wishbone bus, or the like.

Wishbone: a bus protocol completes the interconnection by establishing a generic interface between IP cores. Can be used for interconnection among soft cores, solid cores and hard cores.

The MIPI interface disclosed by the application firstly analyzes signals input by external equipment based on MIPI protocol into serial data through a receiving data processing module, then converts the serial data obtained through analysis into byte data which can be directly processed by an MCU according to the current state of a state machine, and stores the byte data in an SRAM, so that the MCU can freely read corresponding data from the SRAM according to the requirement; when the MCU needs to output data, the corresponding data to be sent is written into the SRAM, and then the data to be sent is obtained from the SRAM by the transmitting data processing module and is output to the external equipment through the MIPI bus. The receiving and transmitting of the whole MIPI signal and the data conversion are realized by the MIPI interface provided by the application, a pure software simulation analysis mode is not needed to be adopted by the MCU, the running resources of the MCU are liberated, and the processing efficiency and the processing speed of the MCU are not influenced.

Meanwhile, the MIPI interface circuit provided by the application has a simple structure, can be designed by RTL, and generates a final circuit through a comprehensive tool, so that the MIPI interface circuit can be repeatedly realized on different process platforms, is convenient for MCU integration, and is more beneficial to implementation.

RTL: register-transfer level, register conversion stage circuit. It is an abstraction level used to describe the operation of synchronous digital circuits. At the RTL level, an IC is made up of a set of registers and logical operations between registers. This is so because most circuits can be seen as storing binary data by registers, completing the processing of the data by logical operations between registers, the flow of the data processing being controlled by a sequential state machine, these processes and controls being described in a hardware description language.

From the above, the MIPI interface provided by the present application converts the MIPI signal input by the external device into byte data that can be directly processed by the MCU, and stores the byte data in the SRAM, and when the MCU needs, the byte data can be read from the SRAM, so as to realize that the external data is transmitted to the MCU based on MIPI. However, how to remind the MCU to process data in time after the data is stored in the SRAM is still an urgent problem to be solved. Thus, the present example provides a preferred embodiment based on the above example, as shown in fig. 1, the MIPI interface further includes:

a plurality of reception match registers 110 connected to the reception data processing module 105 and the SRAM106, and each of the reception match registers 110 is used for matching MIPI long packets or for matching MIPI short packets; when one path of receiving match register 110 is successfully matched, it is also used to generate an interrupt signal for interrupting the current process of MCU108 and a match flag for indicating to MCU108 to find a matching successful MIPI signal at the memory address of SRAM 106.

It should be noted that, in this embodiment, the number of the receiving match registers 110 is not limited, and it is not limited whether each receiving match register 110 is used for matching a MIPI long packet or a MIPI short packet, and besides an implementation manner in which the receiving match registers 110 for matching a MIPI long packet and for matching a MIPI short packet exist, all the multiple receiving match registers 110 may be used for matching a MIPI long packet, or all the multiple receiving match registers 110 may be used for matching a MIPI short packet, which may be freely determined according to actual needs.

In practical applications, MIPI signals matched by different receiving and matching registers 110 are stored at different addresses in SRAM106, and when MIPI signals are successfully matched by a certain receiving and matching register 110, receiving and matching register 110 generates a matching flag to indicate that byte data corresponding to MIPI signals successfully matched by MCU108 are stored at the address of SRAM106, so that MCU108 can read conveniently. Meanwhile, after matching is successful, the receiving match register 110 also generates an interrupt signal, which can interrupt the current process of the MCU108, so that the MCU108 processes the MIPI signal successfully matched first, and thus the MCU108 can process the data received by the MIPI interface in time.

In addition, as can be seen from the above embodiments, the SRAM106 is mainly used for storing data so as to be read or written by the MCU108, so how to prevent the data from being lost is an important requirement in practical applications. In this regard, this embodiment provides a preferred implementation, as shown in fig. 1, where the MIPI interface provided by the present application further includes: an SRAM configuration register 111 storing SRAM space configuration information; SRAM configuration register 111 is connected to MCU108, and MCU108 may divide the space of SRAM106 into multiple groups according to the SRAM space configuration information. It should also be noted that the process of spatial division of the SRAM106 by the MCU108 may be performed once when the SRAM spatial configuration information is unchanged, for example, when the MCU108 detects that the SRAM configuration register 111 is inserted each time, the SRAM spatial division may be performed once by reading the SRAM spatial configuration information therein, or further, when the SRAM spatial configuration information is detected to change, the SRAM spatial division may be performed once, depending on the actual requirement.

The SRAM configuration register 111 stores pre-configured SRAM space configuration information, and the MCU108 may divide the space inside the SRAM106 into multiple groups according to the SRAM space configuration information, and the multiple groups are respectively used for storing data of different frames, so as to reduce the probability of data loss.

Specifically, the SRAM space configuration information may include: the number of groups into which SRAM106 is partitioned, and the length of each group of receivable data packets. In another preferred embodiment, the two types of information may be stored in different registers, that is, there are multiple SRAM configuration registers 111, respectively for storing different SRAM space configuration information.

Likewise, in another possible implementation manner, the SRAM configuration register 111 may be further connected to the received data processing module 105, where when the received data processing module 105 stores the converted byte data in the SRAM106, the data may be stored in a frame cycle according to the above-mentioned SRAM space configuration information, and each receiving group of the SRAM106 may also have a receiving completion indication and a receiving data length readable; when MCU108 needs to read data from SRAM106, the address of the corresponding data in SRAM106 can be calculated according to the above-mentioned SRAM space configuration information.

The preferred scheme provided in this embodiment is connected to the MCU108 through the SRAM configuration register 111 storing the SRAM space configuration information, so that the MCU108 can divide the internal space of the SRAM106 into multiple receiving groups according to the SRAM space configuration information, and is used for receiving data of different frames, so that the SRAM106 can buffer multiple frames of data, to avoid data packet loss, and further improve the reliability of the MIPI interface provided in the present application.

Considering that the packet header error correction code (Error Correcting Code, ECC) of the received data is calculated by the MCU at present and the received ECC value is compared to judge whether the current data is missed, the MCU is required to calculate the ECC value and write the packet header of the data during data transmission, so that a part of resources of the MCU are still occupied. Accordingly, the present embodiment further provides a preferred embodiment based on the above embodiment, as shown in fig. 1, where the MIPI interface provided by the present application further includes:

the ECC calculation module 112 is connected with the SRAM106, and the ECC calculation module 112 is used for calculating the header ECC value of the byte data, comparing the header ECC value with the received ECC value, and generating a corresponding state identifier according to the comparison result, so that the MCU108 can conveniently and correspondingly process the byte data according to the state identifier; the ECC calculation module 112 is further configured to calculate a header ECC value of data to be transmitted and replace data of ECC bits.

According to the preferred scheme provided by the embodiment, the ECC calculation module is used for realizing ECC calculation, ECC comparison and ECC replacement originally carried out by the MCU by the other hardware modules, so that the running resources of the MCU are further liberated, and the data processing efficiency of the MCU is improved.

Based on the above embodiment, this embodiment also provides a preferred implementation manner, as shown in fig. 1, the MIPI interface provided by the present application further includes:

a transmission configuration register 113 storing transmission data configuration information; transmit configuration register 113 is coupled to MCU108 and transmit data processing module 104.

Wherein transmitting the data configuration information includes: address information of data to be transmitted and length information of data to be transmitted. And as with the SRAM space configuration information, the two different transmit data configuration information may be stored in different registers.

When the configuration of the transmission data configuration information is completed, the transmission data processing module 104 may obtain the data to be transmitted from the SRAM106 according to the configuration information of the transmission data, and output the data to the external device 107. Thus, MCU108 can control when data is output to external device 107 by controlling when data configuration information is transmitted after configuration.

According to the embodiment, through the transmitting configuration register stored with the transmitting data configuration information, the transmitting data processing module can accurately acquire data to be transmitted from the SRAM according to the transmitting data configuration information and output the data, and meanwhile, the MCU can control when the transmitting data configuration information is configured to control when the MIPI interface outputs the data to the external device because the transmitting data processing module outputs the data after the transmitting data configuration information is configured.

Furthermore, the relationship between the MCU and the SRAM, which is a direct connection, has been clearly explained in the above embodiments, so that the SRAM may be used as an extended general-purpose SRAM of the MCU in addition to the MIPI interface to improve the resources of the MCU. Accordingly, the present embodiment provides a preferred solution:

the power supply of the SRAM is independent.

The power supply of the SRAM is independent of the power supply of other hardware modules in the MIPI interface provided by the application, so that when the MIPI interface is not powered on and does not work, the SRAM can still be powered on, at the moment, the SRAM is equivalent to an MCU directly connected with an SRAM, and the SRAM is equivalent to an external expansion SRAM of the MCU, thereby achieving the effect of improving MCU resources.

The present example also provides another preferred embodiment: the power supply of the SRAM and the power supply of the MCU are the same power supply.

Because the SRAM is used as a part of the MIPI interface or used as an external expansion SRAM of the MCU, the MCU is required to be in a working state, when the power supply of the SRAM and the MCU share the same power supply, the SRAM can be ensured to work when the MCU works, and a new power supply is not required to be additionally added, so that the MCU is more beneficial to practical implementation.

Based on the foregoing MIPI interface provided by the foregoing embodiment, in order to further explain the scheme of the present application, the present embodiment provides a control method of a MIPI interface, which is applied to the foregoing MIPI interface, as shown in fig. 2 and fig. 3, and includes:

s21: and judging whether data input by the external equipment are received, if so, proceeding to step S22.

S22: the state machine sends a direction control signal to control a buffer disposed between the MIPI bus and the receive data processing module to an enabled state.

S23: the received data processing module analyzes the data input by the external equipment to obtain serial data and state codes.

S24: the state machine performs state jump according to the state code, and the received data processing module converts serial data into byte data according to the current state of the state machine and sends the byte data to the SRAM so that the MCU can acquire the byte data by reading the SRAM.

S31: and judging whether data sent by the MCU are received, if so, proceeding to step S32.

S32: the transmitting data processing module acquires data sent by the MCU from the SRAM.

S33: the state machine sends a direction control signal to control a buffer disposed between the MIPI bus and the transmit data processing module to an enabled state.

It should be noted that there is no sequence between the steps S21 to S24 and the steps S31 to S33, and when the conditions of S21 or S31 are satisfied, the process goes to the corresponding step, and the whole method is completed.

The control method of the MIPI interface, provided by the embodiment, is applied to the MIPI interface, so that the MIPI interface can complete data interaction between the MCU and the external equipment based on the MIPI protocol, and can bring the same effect as the MIPI interface, liberate the running resources of the MCU, and avoid affecting the efficiency and the speed of the MCU.

Fig. 4 is a block diagram of a control device of an MIPI interface according to another embodiment of the present application, and as shown in fig. 4, a control device of an MIPI interface includes: a memory 40 for storing a computer program;

a processor 41 for implementing the steps of a control method of the MIPI interface according to the above embodiment when executing a computer program.

The control device of the MIPI interface provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.

Processor 41 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc., among others. The processor 41 may be implemented in hardware in at least one of a digital signal processor (Digital Signal Processor, DSP), a Field programmable gate array (Field-Programmable Gate Array, FPGA), a programmable logic array (Programmable Logic Array, PLA). The processor 41 may also comprise a main processor, which is a processor for processing data in an awake state, also called central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 41 may be integrated with an image processor (Graphics Processing Unit, GPU) for taking care of rendering and rendering of the content that the display screen is required to display. In some embodiments, the processor 41 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.

Memory 40 may include one or more computer-readable storage media, which may be non-transitory. Memory 40 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 40 is at least used for storing a computer program 401, where the computer program, after being loaded and executed by the processor 41, can implement the relevant steps of a control method of an MIPI interface disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 40 may further include an operating system 402, data 403, and the like, where the storage manner may be transient storage or permanent storage. Operating system 402 may include, among other things, windows, unix, linux. The data 403 may include, but is not limited to, a control method of the MIPI interface, etc.

In some embodiments, a MIPI interface control device may further include a display 42, an input/output interface 43, a communication interface 44, a power supply 45, and a communication bus 46.

Those skilled in the art will appreciate that the configuration shown in fig. 4 is not limiting of a MIPI interface control device and may include more or fewer components than shown.

The control device of the MIPI interface provided by the embodiment of the application comprises a memory and a processor, wherein the processor can realize the following method when executing a program stored in the memory: a control method of MIPI interface.

Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.

It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The MIPI interface, the control method, the device and the medium thereof provided by the application are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims

1. An MIPI interface, comprising: MIPI bus, multiple buffers, state machine, transmitting data processing module, receiving data processing module and SRAM;

the MIPI bus is connected with external equipment, is connected with the receiving data module through at least one buffer, is connected with the transmitting data processing module through other buffers, is connected with the output end of the buffer, and is connected with the input end of the buffer; the enabling end of each buffer is connected with the state machine and is used for receiving a direction control signal sent by the state machine; the received data processing module is connected with the state machine and the SRAM, and is used for analyzing the data sent by the MIPI bus to obtain serial data and state codes, converting the serial data into byte data according to the state of the state machine and sending the byte data to the SRAM; the transmitting data processing module is connected with the SRAM and is used for transmitting data to be transmitted in the SRAM to the MIPI bus; the SRAM is connected with the MCU.

2. The MIPI interface of claim 1, further comprising: the receiving matching registers are connected with the receiving data processing module and the SRAM in multiple paths, and each path of receiving matching register is used for matching MIPI long packets or MIPI short packets; and after one path of the receiving matching registers is successfully matched, the receiving matching registers are also used for generating an interrupt signal and a matching mark, wherein the interrupt signal is used for interrupting the current process of the MCU, and the matching mark is used for indicating the MCU to find the memory address of the MIPI signal successfully matched in the SRAM.

3. The MIPI interface of claim 1, further comprising: an SRAM configuration register storing SRAM space configuration information; the SRAM configuration register is connected with the MCU, and the MCU can divide the space of the SRAM into a plurality of groups according to the space configuration information of the SRAM.

4. The MIPI interface of claim 1, wherein the SRAM and MCU connections are specifically: the SRAM is connected with an AHB interface of the MCU through an AHB bus.

5. The MIPI interface of claim 1, further comprising: the ECC calculation module is used for calculating the packet header ECC value of the byte data, comparing the packet header ECC value with the received ECC value, and generating a corresponding state identifier according to a comparison result so as to facilitate the MCU to perform corresponding processing on the byte data according to the state identifier; the ECC calculation module is also used for calculating the header ECC value of the data to be transmitted and replacing the data of ECC bits.

6. The MIPI interface according to any one of claims 1-5, further comprising: a transmission configuration register storing transmission data configuration information; the transmission configuration register is connected with the MCU and the transmission data processing module.

7. The MIPI interface of claim 6, wherein the SRAM is powered independently.

8. A control method of an MIPI interface, applied to the MIPI interface of claims 1-7, comprising:

when receiving data input by an external device, the state machine sends a direction control signal to control a buffer arranged between the MIPI bus and the received data processing module to be in an enabling state;

the received data processing module analyzes the data input by the external equipment to obtain serial data and state codes;

the state machine performs state jump according to the state code, the received data processing module converts the serial data into byte data according to the current state of the state machine and sends the byte data to the SRAM so that the MCU can acquire the byte data by reading the SRAM;

when receiving the data sent by the MCU, a transmitting data processing module acquires the data sent by the MCU from the SRAM;

the state machine sends a direction control signal to control a buffer arranged between the MIPI bus and the transmission data processing module to be in an enabling state.

9. A control device of an MIPI interface, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the control method of the MIPI interface according to claim 8 when executing the computer program.

10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the MIPI interface control method according to claim 8.