CN114817114A

CN114817114A - MIPI interface, control method, device and medium thereof

Info

Publication number: CN114817114A
Application number: CN202210520091.6A
Authority: CN
Inventors: 王锐; 张齐; 王亚波; 李建军; 莫军
Original assignee: Guangxin Microelectronics Suzhou Co ltd
Current assignee: Guangxin Microelectronics Suzhou Co ltd
Priority date: 2022-05-13
Filing date: 2022-05-13
Publication date: 2022-07-29
Anticipated expiration: 2042-05-13
Also published as: CN114817114B

Abstract

The application relates to the technical field of integrated circuits, to the problem that MCU resources are occupied through software mode analysis, simulation MIPI signal for MCU at present, provide a MIPI interface, include: the system comprises an MIPI bus, a plurality of buffers, a state machine, a transmitting data processing module, a receiving data processing module and an SRAM; when the external equipment inputs data, the receiving data processing module analyzes to obtain serial data and state codes; the state machine skips the state according to the state code, and the received data processing module converts the serial data into byte data according to the current state of the state machine; when the MCU outputs data, the transmitting data processing module acquires data written by the MCU from the SRAM and outputs the data through the MIPI bus. The conversion of MIPI signal and byte data is realized through hardware device to this application, need not MCU and passes through software form simulation, analytic MIPI signal to save MCU's operating resource, raise the efficiency.

Description

MIPI interface, control method, device and medium thereof

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to an MIPI interface, and a method, an apparatus, and a medium for controlling the same.

Background

With the rapid development of information technology and mobile portable devices, people have higher and higher requirements on mobile devices, and on the premise of meeting the high-performance display effect, the power consumption of the mobile devices is required to be reduced as much as possible. Currently, a mainstream video Interface in the Mobile field uses a Mobile Industry Processor (MIPI) Interface, the MIPI defines Interface specifications of high-speed data transmission and low-power transmission, and the MIPI D-PHY is a physical layer standard of the MIPI Interface. In practical application of MIPI, there is an application occasion that only MIPI low power consumption mode data needs to be supported, the application occasion needs to operate in a low speed mode, and currently, a General-purpose input/output (GPIO) is used by a Micro Control Unit (MCU) to simulate a bus signal of MIPI for output when data is transmitted, edge information of the GPIO is obtained when data is received, and an MCU timer is used to obtain a MIPI timing sequence, that is, the MCU analyzes a low speed signal of a MIPI bus in a pure software manner.

The method for analyzing the low-speed signal of the MIPI bus by the MCU in a pure software mode occupies a large amount of resources of the MCU, and influences the processing efficiency and the speed of the MCU.

Therefore, those skilled in the art need an MIPI interface to solve the problem that in a low-cost application scenario that only the MIPI low-power mode needs to be supported, a large amount of resources of the MCU will be occupied by the MCU by analyzing the low-speed signal of the MIPI bus in a pure software manner, and the processing efficiency and the rate of the MCU will be affected.

Disclosure of Invention

The application aims to provide an MIPI (mobile industry processor interface), and a control method, a device and a medium thereof, and solve the problems that a large number of resources of an MCU (micro control unit) are occupied and the processing efficiency and the processing speed of the MCU are influenced when the MCU analyzes a low-speed signal of an MIPI bus in a pure software mode at present.

In order to solve the above technical problem, the present application provides an MIPI interface, including: the system comprises an MIPI bus, a plurality of buffers, a state machine, a transmitting data processing module, a receiving data processing module and an SRAM;

the MIPI bus is connected with external equipment, is connected with the data receiving module through at least one buffer, is connected with the data transmitting processing module through other buffers, is connected with the output end of the buffer, and is connected with the input end of the buffer; the enabling end of each buffer is connected with the state machine and used for receiving the direction control signal sent by the state machine; the receiving data processing module is connected with the state machine and the SRAM and used for analyzing data sent by the MIPI bus to obtain serial data and state codes, converting the serial data into byte data according to the state of the state machine and sending the byte data to the SRAM; the transmission data processing module is connected with the SRAM and used for sending data to be sent in the SRAM to the MIPI bus; the SRAM is connected with the MCU.

Preferably, the method further comprises the following steps: the receiving matching registers are connected with the receiving data processing module and the SRAM in multiple ways, and each receiving matching register is used for matching the MIPI long packet or the MIPI short packet; and when the matching of the receiving matching register is successful, the receiving matching register is also used for generating an interrupt signal and a matching mark, wherein the interrupt signal is used for interrupting the current process of the MCU, and the matching mark is used for indicating the MCU to find out the MIPI signal successfully matched with the memory address of the SRAM.

Preferably, the method further comprises the following steps: the SRAM configuration register stores SRAM space configuration information; the SRAM configuration register is connected with the MCU, and the MCU can divide the space of the SRAM into a plurality of groups according to the SRAM space configuration information.

Preferably, the connection between the SRAM and the MCU specifically comprises: the SRAM is connected with the AHB interface of the MCU through an AHB bus.

Preferably, the method further comprises the following steps: the ECC calculation module is connected with the SRAM and is used for calculating a packet header ECC value of the byte data, comparing the packet header ECC value with the received ECC value and generating a corresponding state identifier according to a comparison result, so that the MCU can conveniently perform corresponding processing on the byte data according to the state identifier; the ECC calculation module is further used for calculating a packet header ECC value of the data to be sent and replacing the data of the ECC bit.

Preferably, the method further comprises the following steps: a transmission configuration register storing transmission data configuration information; and the transmitting configuration register is connected with the MCU and the transmitting data processing module.

Preferably, the power supply of the SRAM is independent.

In order to solve the above technical problem, the present application further provides a control method for an MIPI interface, which is applied to the MIPI interface, and includes: when receiving data input by external equipment, the state machine sends a direction control signal to control a buffer arranged between an MIPI bus and a received data processing module to be in an enabling state; the receiving data processing module analyzes data input by external equipment to obtain serial data and state codes; the state machine skips the state according to the state code, the received data processing module converts serial data into byte data according to the current state of the state machine and sends the byte data to the SRAM, so that the MCU can obtain the byte data by reading the SRAM; when receiving data sent by the MCU, the transmission data processing module acquires the data sent by the MCU from the SRAM; the state machine sends a direction control signal to control a buffer arranged between the MIPI bus and the transmission data processing module to be in an enabling state.

In order to solve the above technical problem, the present application further provides a control device of an MIPI interface, including: a memory for storing a computer program; and the processor is used for realizing the steps of the control method of the MIPI when executing the computer program.

In order to solve the above technical problem, the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the control method for the MIPI interface are implemented.

According to the MIPI, the enable states of different buffers are controlled by the state machine to switch the MIPI bus into an input state or an output state so as to receive data input by external equipment or output data to the external equipment; when external equipment inputs data, the MIPI bus sends the data to the received data processing module, and the received data processing module analyzes the data to obtain analyzed serial data and state codes; the state machine skips the state according to the state code, and the received data processing module converts the serial data into byte data according to the current state of the state machine and sends the byte data to a Static Random-Access Memory (SRAM) for storage; because the MCU is directly connected with the SRAM, the MCU can freely read data from the SRAM or write data into the SRAM; when the MCU writes data into the SRAM, the state machine controls the buffer to enable the MIPI bus to be switched into an output state, and the transmitting data processing module acquires the data written by the MCU from the SRAM and outputs the data to the external equipment through the MIPI bus so as to achieve the effect of data transmission between the external equipment and the MCU through the MIPI interface. Simultaneously, the MIPI interface that this application provided, through the state machine, hardware devices such as receipt data processing module convert the data of external input based on MIPI interface protocol into the direct readable byte data of MCU and save in SRAM, MCU can directly carry out read-write operation to SRAM, the bus signal of MIPI need not MCU through the form simulation of software during the sending data, the low-speed signal of MIPI bus also need not to be analyzed out through the border information of GPIO and MIPI's chronogenesis during the receipt data, MCU's operating resource has been saved greatly, MCU's work efficiency has been improved. And the MIPI interface that this application provided can be by RTL design to produce final circuit through synthesizing the instrument, so can used repeatedly on different technology platforms, make things convenient for MCU integration.

The control method, device and computer readable storage medium of the MIPI interface provided by the application correspond to the MIPI interface, and the effect is the same as above.

Drawings

In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.

Fig. 1 is a schematic structural diagram of an MIPI interface provided in the present invention;

fig. 2 is a flowchart of a data receiving method of an MIPI interface according to the present invention;

fig. 3 is a flowchart of a data transmission method of an MIPI interface according to the present invention;

fig. 4 is a structural diagram of a data transmitting apparatus of an MIPI interface provided in the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.

The core of the application is to provide an MIPI interface, a control method, a device and a medium thereof.

In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.

In the field of current mobile devices, to achieve a high-performance display effect and reduce power consumption of the mobile device as much as possible, an MIPI-based interface is generally used. The typical application is a processor of a mobile phone, which is integrated with an MIPI interface module and supports a complete interface protocol of MIPI. And a specially designed MIPI interface conversion chip which can also support the complete interface protocol of the MIPI and analyze and convert the MIPI signals into parallel data. However, in an application situation that only MIPI low-power-consumption mode data needs to be supported, the MIPI interface module and the MIPI interface conversion chip cannot meet the requirements of low cost and low power consumption, so that a mode that an MCU simulates and analyzes a low-speed signal of an MIPI bus in a pure software mode is usually adopted at present, and this mode needs to occupy a large amount of running resources of the MCU, and greatly affects the processing efficiency and the speed of the MCU.

Therefore, the present application provides an MIPI interface, as shown in fig. 1, including: a MIPI bus 101, a plurality of buffers (i.e., MIPI bus direction switching module 102), a state machine 103, a transmission data processing module 104, a reception data processing module 105, and an SRAM 106;

the MIPI bus 101 is connected with an external device 107, is connected with a data receiving module through at least one buffer, is connected with a data transmitting processing module 104 through other buffers, is connected with an output end of the buffer, and is connected with an input end of the buffer; the enabling end of each buffer is connected with the state machine 103 and used for receiving the direction control signal sent by the state machine 103; the received data processing module 105 is connected with the state machine 103 and the SRAM106, and is configured to parse data sent by the MIPI bus 101 to obtain serial data and state codes, convert the serial data into byte data according to the current state of the state machine 103, and send the byte data to the SRAM 106; the transmission data processing module 104 is connected to the SRAM106, and is configured to send data to be sent in the SRAM106 to the MIPI bus 101; the SRAM106 is connected to the MCU 108.

The MCU108 is connected to the external device 107 through the MIPI interface, and when the external device 107 inputs data to the MCU108, the state machine 103 sends a direction control signal to control enabling of the corresponding buffer, so that the data flow of the MIPI bus 101 is from the external device 107 to the received data processing module 105, that is, the MIPI bus 101 is switched to the input mode; when the MCU108 outputs data to the external device 107, the state machine 103 sends a direction control signal to control the enabling of another buffer, so that the data flow of the MIPI bus 101 is from the transmission data processing module 104 to the external device 107, that is, the MIPI bus 101 is switched to the output mode. The above-mentioned buffers mainly play a role of controlling the data flow of the MIPI bus 101 according to the direction control signal sent by the state machine 103, so in fig. 1, a plurality of buffers are represented by the MIPI bus direction switching module 102.

After the direction of the MIPI bus 101 can be switched as needed, when the external device 107 inputs data, the received data processing module 105 receives and analyzes the input MIPI signal to obtain serial data and state coding of the MIPI signal, the state machine 103 performs state skip according to the received state coding, and meanwhile, the received data processing module 105 also converts serial data obtained by analysis into byte data to be output according to the current state of the state machine 103 so as to be stored in the SRAM 106;

the SRAM106 is directly connected to the MCU108, and the MCU108 can freely read data from the SRAM106 or write data into the SRAM106, so as to receive the MIPI signal input from the external device 107. When the MCU108 needs to output data to the external device 107, the data is written into the SRAM106, and the transmission data processing module 104 obtains the data from the SRAM106 and transmits the data to the external device 107 through the MIPI bus 101.

It should be noted that, since the received data processing module 105 stores the data in the SRAM106, in a possible implementation as shown in fig. 1, the state code parsed by the received data processing module 105 is also stored in the SRAM106, and the state machine 103 is connected to the SRAM106 for obtaining the state code.

This embodiment also provides a preferred implementation of the connection between the SRAM106 and the MCU108, wherein the SRAM106 is connected to the AHB interface of the MCU108 via the AHB bus 109.

In the field of current mobile portable devices, High Performance modules such as the MCU108 are usually integrated with an Advanced High Performance Bus (AHB) interface, and are connected to other High Performance modules through an AHB Bus 109. Therefore, the SRAM106 can be directly connected with the MCU108 through the AHB bus 109, which is convenient for the integration of the MIPI interface and the chip provided by the present application. Further, for the same purpose, the SRAM106 may be connected to the MCU108 via an Advanced Peripheral Bus (APB), Wishbone Bus, or the like.

Wishbone: a bus protocol that completes an interconnect by establishing a generic interface between IP cores. Can be used for interconnection among the soft core, the solid core and the hard core.

According to the MIPI, signals input by external equipment based on an MIPI protocol are firstly analyzed into serial data through a received data processing module, then the serial data obtained through analysis are converted into byte data which can be directly processed by an MCU according to the current state of a state machine, and the byte data are stored in an SRAM, so that the MCU can freely read corresponding data from the SRAM as required; and when the MCU needs to output data, writing the corresponding data to be transmitted into the SRAM, acquiring the data from the SRAM by the transmitting data processing module, and outputting the data to the external equipment through the MIPI bus. The whole MIPI signal receiving and transmitting and the data conversion are realized by the MIPI interface provided by the application, a pure software simulation analysis mode is not needed to be adopted by the MCU, the running resources of the MCU are liberated, and the processing efficiency and the speed of the MCU are not influenced.

Simultaneously, the MIPI interface circuit that this application provided simple structure can be designed by RTL to produce final circuit through synthesizing the instrument, so can realize repeatedly on different technology platforms, make things convenient for MCU integration, more be favorable to implementing.

RTL: register-transfer level, register conversion level circuit. Which is an abstraction level used to describe the operation of synchronous digital circuits. At the RTL level, the IC is made up of a set of registers and logical operations between the registers. This is so because most circuits can be viewed as storing binary data by registers, processing data by logic operations between registers, and the flow of data processing is controlled by a sequential state machine, and these processes and controls can be described by a hardware description language.

Therefore, the MIPI interface converts MIPI signals input by external equipment into byte data which can be directly processed by an MCU (microprogrammed control unit) and stores the byte data in the SRAM, and the byte data can be read from the SRAM when the MCU is needed, so that the external data are transmitted to the MCU based on the MIPI. However, after the data is stored in the SRAM, how to remind the MCU to process the data in time is still an urgent problem to be solved. Therefore, this embodiment further provides a preferred implementation scheme based on the above embodiment, and as shown in fig. 1, the MIPI interface further includes:

a plurality of reception matching registers 110 connected to the reception data processing module 105 and the SRAM106, and each reception matching register 110 is used for matching a MIPI long packet or for matching a MIPI short packet; when the matching of the receiving matching register 110 is successful, the receiving matching register 110 is further configured to generate an interrupt signal and a matching flag, where the interrupt signal is used to interrupt the current process of the MCU108, and the matching flag is used to instruct the MCU108 to find a storage address of the SRAM106 where the MIPI signal successfully matched is located.

It should be noted that, in this embodiment, the number of the receiving matching registers 110 is not limited, and at the same time, whether each receiving matching register 110 is used for matching a MIPI long packet or a MIPI short packet is not limited, except for an implementation where the receiving matching registers 110 for matching a MIPI long packet and for matching a MIPI short packet are both present, the receiving matching registers 110 may be all used for matching a MIPI long packet, or the receiving matching registers 110 may be all used for matching a MIPI short packet, and may be determined freely according to actual needs.

In practical application, MIPI signals matched with different receiving matching registers 110 are stored in different addresses of the SRAM106, and when a MIPI signal is successfully matched with a certain receiving matching register 110, the receiving matching register 110 generates a matching flag to indicate that byte data corresponding to the MIPI signal successfully matched by the MCU108 is stored in the address of the SRAM106, so that the MIPI signal can be read by the MCU 108. Meanwhile, after the matching is successful, the receiving matching register 110 also generates an interrupt signal, and the interrupt signal can interrupt the current process of the MCU108, so that the MCU108 processes the successfully matched MIPI signal first, thereby enabling the MCU108 to process the data received by the MIPI interface in time.

In addition, as can be seen from the above embodiments, the SRAM106 is mainly used for storing data to facilitate reading or writing by the MCU108, so how to prevent data loss is an important requirement in practical applications. In this regard, this embodiment provides a preferred implementation, and as shown in fig. 1, the MIPI interface provided in this application further includes: an SRAM configuration register 111 storing SRAM spatial configuration information; the SRAM configuration register 111 is connected to the MCU108, and the MCU108 can divide the space of the SRAM106 into a plurality of groups according to the SRAM space configuration information. It should also be noted that the MCU108 may perform the space division process on the SRAM106 once when the SRAM space configuration information is not changed, for example, the MCU108 may perform the SRAM space division by reading the SRAM space configuration information when detecting that the SRAM configuration register 111 is inserted once, or perform the SRAM space division once when detecting that the SRAM space configuration information is changed, depending on actual needs.

The SRAM configuration register 111 stores preconfigured SRAM spatial configuration information, and the MCU108 can divide the internal space of the SRAM106 into a plurality of groups according to the SRAM spatial configuration information, where the groups are respectively used to store data of different frames, so as to reduce the probability of data loss.

Specifically, the SRAM spatial configuration information may include: the number of groups into which the SRAM106 is divided, and the length of the data packet that can be received per group. In another preferred scheme, the two kinds of information may be stored in different registers, that is, there are multiple SRAM configuration registers 111, which are respectively used for storing different SRAM space configuration information.

Similarly, in another possible embodiment, the SRAM configuration register 111 may be further connected to the received data processing module 105, and when the received data processing module 105 stores the converted byte data in the SRAM106, the data may be stored according to the above SRAM space configuration information in a frame cycle, and each receiving group of the SRAM106 may also have a receiving completion indication and a receiving data length readable; when the MCU108 needs to read data from the SRAM106, the addresses of the corresponding data in the SRAM106 can be calculated according to the SRAM space configuration information.

In the preferred scheme provided by this embodiment, the SRAM configuration register 111 storing the SRAM spatial configuration information is connected to the MCU108, so that the MCU108 can divide the internal space of the SRAM106 into a plurality of receiving groups according to the SRAM spatial configuration information for receiving data of different frames, and thus the SRAM106 can buffer multi-frame data to avoid data packet loss, thereby further improving the reliability of the MIPI interface provided by this application.

Considering that, currently, the MCU calculates a header Error Correction Code (ECC) of received data and compares the received ECC values to determine whether the current data is faulty or not, and similarly, the MCU also needs to calculate the ECC values and write the header of the data when the data is transmitted, so that a part of MCU resources are still occupied. Therefore, this embodiment further provides a preferred implementation scheme based on the above embodiment, and as shown in fig. 1, the MIPI interface provided in this application further includes:

the ECC computation module 112 is connected to the SRAM106, and the ECC computation module 112 is configured to compute a packet header ECC value of the byte data, compare the packet header ECC value with the received ECC value, and generate a corresponding status identifier according to a comparison result, so that the MCU108 performs corresponding processing on the byte data according to the status identifier; the ECC computation module 112 is further configured to compute a header ECC value of data to be sent and replace data of ECC bits.

In the preferred scheme provided by this embodiment, the ECC computation module is used to implement ECC computation, ECC comparison, and ECC replacement, which are originally performed by the MCU, by another hardware module, so as to further liberate the operating resources of the MCU and be more beneficial to improving the data processing efficiency of the MCU.

On the basis of the above example, this example also provides a preferred implementation, and as shown in fig. 1, the MIPI interface provided by the present application further includes:

a transmission configuration register 113 storing transmission data configuration information; the transmission configuration register 113 is connected to the MCU108 and the transmission data processing module 104.

Wherein transmitting the data configuration information comprises: address information of data to be transmitted and length information of the data to be transmitted. And the two different transmission data configuration information can be stored in different registers, similar to the SRAM space configuration information.

After the configuration information of the transmission data is configured, the transmission data processing module 104 may obtain data to be transmitted from the SRAM106 according to the configuration information of the transmission data to output the data to the external device 107. Also, therefore, the MCU108 can control when to output data to the external device 107 by controlling when the configuration is completed to transmit data configuration information.

In this embodiment, the transmission configuration register storing the transmission data configuration information enables the transmission data processing module to accurately obtain and output data to be transmitted from the SRAM according to the transmission data configuration information, and meanwhile, since the transmission data processing module outputs data after the transmission data configuration information is configured, the MCU can control when the transmission data configuration information is configured to control when the MIPI interface outputs data to the external device.

In addition, in the above embodiment, it has been clearly illustrated that the MCU and the SRAM are directly connected, so that the SRAM can be used as an extended general SRAM for the MCU in addition to the MIPI interface, so as to improve the resources of the MCU. Correspondingly, the present embodiment provides a preferred solution:

the power supply of the SRAM is independent.

The power supply of SRAM is independent of the power supply of other hardware modules in the MIPI interface that this application provided, so, when the MIPI interface does not work at the switch-on power supply, SRAM still can the power supply, is equivalent to SRAM of MCU lug connection this moment, and SRAM is equivalent to MCU's an external extension SRAM, reaches the effect that improves the MCU resource.

This example also provides another preferred embodiment: the power supply of the SRAM and the power supply of the MCU are the same.

Because no matter the SRAM works as a part of the MIPI interface or as the external extension SRAM of the MCU, the MCU is required to be in a working state, when the power supply of the SRAM and the MCU share the same power supply, the SRAM can work when the MCU works, a new power supply does not need to be additionally added, and the practical implementation is facilitated.

Based on the MIPI interface provided by the above embodiment, to further explain the scheme of the present application, the embodiment provides a control method of the MIPI interface, which is applied to the MIPI interface, as shown in fig. 2 and fig. 3, and includes:

s21: it is determined whether data input from the external device is received, and if so, the process proceeds to step S22.

S22: the state machine sends a direction control signal to control a buffer arranged between the MIPI bus and the received data processing module to be in an enabling state.

S23: the receiving data processing module analyzes data input by the external equipment to obtain serial data and state codes.

S24: the state machine skips the state according to the state code, the received data processing module converts the serial data into byte data according to the current state of the state machine and sends the byte data to the SRAM, so that the MCU can obtain the byte data by reading the SRAM.

S31: and judging whether the data sent by the MCU is received, if so, entering the step S32.

S32: and the transmitting data processing module acquires data transmitted by the MCU from the SRAM.

S33: the state machine sends a direction control signal to control a buffer arranged between the MIPI bus and the transmission data processing module to be in an enabling state.

It should be noted that there is no sequence between steps S21 to S24 and steps S31 to S33, and when the condition of S21 or S31 is satisfied, the corresponding step is performed, and the entire method is completed.

The control method of the MIPI interface provided in this embodiment is applied to the MIPI interface, so that the MIPI interface can complete data interaction between the MCU and the external device based on the MIPI protocol, and can bring about the same effect as the MIPI interface, liberate operating resources of the MCU, and avoid affecting the efficiency and rate of the MCU.

Fig. 4 is a structural diagram of a control device of a MIPI interface according to another embodiment of the present application, and as shown in fig. 4, the control device of the MIPI interface includes: a memory 40 for storing a computer program;

the processor 41 is configured to implement the steps of the control method for the MIPI interface according to the above embodiment when executing the computer program.

The control device of the MIPI interface provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.

Processor 41 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so forth. The Processor 41 may be implemented in hardware using at least one of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA). The processor 41 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 41 may be integrated with a Graphics Processing Unit (GPU) which is responsible for rendering and drawing the content required to be displayed by the display screen. In some embodiments, processor 41 may also include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.

Memory 40 may include one or more computer-readable storage media, which may be non-transitory. Memory 40 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 40 is at least used for storing the computer program 401, wherein after being loaded and executed by the processor 41, the computer program can implement the relevant steps of a control method of an MIPI interface disclosed in any one of the foregoing embodiments. In addition, the resources stored in the memory 40 may also include an operating system 402, data 403, and the like, and the storage manner may be a transient storage or a permanent storage. Operating system 402 may include, among other things, Windows, Unix, Linux, and the like. Data 403 may include, but is not limited to, a control method of the MIPI interface, etc.

In some embodiments, a control device of the MIPI interface may further include a display 42, an input/output interface 43, a communication interface 44, a power supply 45, and a communication bus 46.

It will be appreciated by those skilled in the art that the arrangement shown in figure 4 does not constitute a limitation of the control means of a MIPI interface and may include more or fewer components than those shown.

The control device of the MIPI interface provided in the embodiment of the present application includes a memory and a processor, and when the processor executes a program stored in the memory, the following method can be implemented: a control method of MIPI interface.

Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.

It is to be understood that if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The MIPI interface, the control method, the apparatus, and the medium provided by the present application are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Claims

1. An MIPI interface, comprising: the system comprises an MIPI bus, a plurality of buffers, a state machine, a transmitting data processing module, a receiving data processing module and an SRAM;

the MIPI bus is connected with external equipment, is connected with the data receiving module through at least one buffer, is connected with the data transmitting processing module through other buffers, is connected with the output end of the buffer, and is connected with the input end of the buffer; the enabling end of each buffer is connected with the state machine and used for receiving the direction control signal sent by the state machine; the received data processing module is connected with the state machine and the SRAM and used for analyzing data sent by the MIPI bus to obtain serial data and state codes, converting the serial data into byte data according to the state of the state machine and sending the byte data to the SRAM; the transmitting data processing module is connected with the SRAM and is used for sending data to be sent in the SRAM to the MIPI bus; and the SRAM is connected with the MCU.

2. The MIPI interface of claim 1, further comprising: the receiving matching registers are connected with the receiving data processing module and the SRAM in a multi-path mode, and each receiving matching register is used for matching MIPI long packets or MIPI short packets; and when the matching of the receiving matching register is successful, the receiving matching register is also used for generating an interrupt signal and a matching mark, wherein the interrupt signal is used for interrupting the current process of the MCU, and the matching mark is used for indicating the MCU to find out the storage address of the MIPI signal successfully matched with the MIPI signal in the SRAM.

3. The MIPI interface of claim 1, further comprising: the SRAM configuration register stores SRAM space configuration information; the SRAM configuration register is connected with the MCU, and the MCU can divide the space of the SRAM into a plurality of groups according to the SRAM space configuration information.

4. The MIPI interface of claim 1, wherein the connection between the SRAM and the MCU specifically is: and the SRAM is connected with the AHB interface of the MCU through an AHB bus.

5. The MIPI interface of claim 1, further comprising: the ECC calculation module is connected with the SRAM and is used for calculating a packet header ECC value of the byte data, comparing the packet header ECC value with the received ECC value and generating a corresponding state identifier according to a comparison result, so that the MCU can conveniently perform corresponding processing on the byte data according to the state identifier; the ECC calculation module is further used for calculating a packet header ECC value of the data to be sent and replacing data of ECC bits.

6. The MIPI interface of any one of claims 1 to 5, further comprising: a transmission configuration register storing transmission data configuration information; and the transmitting configuration register is connected with the MCU and the transmitting data processing module.

7. The MIPI interface of claim 6, wherein the SRAM has independent power supplies.

8. A control method of a MIPI interface, applied to the MIPI interface claimed in claims 1 to 7, comprising:

when receiving data input by external equipment, the state machine sends a direction control signal to control a buffer arranged between the MIPI bus and the received data processing module to be in an enabling state;

the received data processing module analyzes data input by the external equipment to obtain serial data and state codes;

the state machine skips states according to the state codes, and the received data processing module converts the serial data into byte data according to the current state of the state machine and sends the byte data to the SRAM so that the MCU can obtain the byte data by reading the SRAM;

when receiving the data sent by the MCU, the transmission data processing module acquires the data sent by the MCU from the SRAM;

the state machine sends a direction control signal to control a buffer arranged between the MIPI bus and the transmission data processing module to be in an enabling state.

9. A control device of an MIPI interface is characterized by comprising:

a memory for storing a computer program;

a processor for implementing the steps of the method of controlling a MIPI interface as claimed in claim 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, realizes the steps of the control method of the MIPI interface according to claim 8.