CN112540944B - Parallel bus protocol and method for realizing data interaction between boards based on protocol - Google Patents
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Abstract
The invention discloses a parallel bus protocol and a method for realizing data interaction between boards based on the protocol, which is applied to a scene of performing data interaction between two editable logic devices across single boards by using a parallel data bus and a localbus bus of a CPU (central processing unit) so as to complete the access of the single board with the CPU to the single board without the CPU, wherein the parallel data bus comprises a clock signal line, an initial signal line and n parallel signal lines; the n-bit parallel signal line is used for transmitting a read-write indicating signal, a multi-bit address signal and a 16-bit data signal; the read/write state machine cycle of the parallel signal line is related to the value of 16/n, when the value of n is larger, the cycle of the state machine is smaller, and when the value of n is smaller, the cycle of the state machine is larger. Compared with the IFC bus, the parallel bus saves the cost of the connector in the number of buses; compared with serial buses such as SMI and the like, the access efficiency is greatly improved, and the limitation of accessing an address space does not exist.
Description
Technical Field
The invention relates to a network communication technology, in particular to a parallel bus protocol and a method for realizing data interaction between boards based on the protocol.
Background
Today, with the rapid development of low-end communication devices, manufacturers of communication devices are increasingly competitive, and not only are functions required to meet requirements, but also the cost is required to be competitive. In the current architecture of communication equipment, the functions of a single board are divided into: single boards such as main control, line card, interface card, backboard, etc. The main control board must have a CPU for the configuration of each chip of the board, but the interface card may not use a CPU in order to save cost, and the number of interface cards in the system is large, if each interface card saves one CPU, the cost of the whole system shows an advantage. Interface card is when not using CPU, the configuration of each chip of this board still needs to be realized, this just needs main control board CPU's address, data, the chip selection, signals such as read-write enable send the interface card through the backplate, there is 20 multibit address lines after CPU's LOCALBUS bus decodes under the general condition, 16-bit data line and 4-bit reading, write, the chip selection, signals such as clock, if not encode and send the interface card through the backplate connector, can occupy 2-3 backplate connectors, so not only increased the connector cost but also can make the system device volume grow and then increase the cost of whole system device. At present, the most connector saving is that buses of two-wire coding and decoding such as SMI, I2C and the like are all serial, the data cycle of once reading and writing is long, for a huge system, more chips need to be configured for each single board, if the serial data bus is used for configuration for a long time, the version starting time of the whole system is long, the user experience is poor, and the performance requirements cannot be met in some scenes such as link switching.
In summary, the following steps: the problem that the cost of equipment is increased due to the fact that a CPU is used in the prior art is solved, and the problems that a system is started, link switching time is long and the like due to the fact that the period of data read and written once by a two-wire serial port protocol after the CPU is removed are solved.
Disclosure of Invention
The invention aims to solve the problems and provide a method for realizing the conversion of the parallel signal line into the code on a programmable logic device with a CPU single board and then realizing the conversion of the parallel signal line into the code on the programmable logic device without the CPU single board.
In order to achieve the purpose, the invention is realized by the following technical scheme: a parallel bus protocol is applied to a scene of performing data interaction between two editable logic devices crossing a single board by using a parallel data bus and a localbus bus of a CPU (central processing unit) so as to complete the access of the single board with the CPU to the single board without the CPU, wherein the parallel data bus comprises a clock signal line, an initial signal line and n parallel signal lines;
the clock signal line edge is used for reading and writing n-bit parallel signal lines;
the start signal line indicates the start of the read/write state machine with a low level or a high level;
the n-bit parallel signal line is used for transmitting a read-write indicating signal, a multi-bit address signal and a 16-bit data signal; the read-write state machine cycle of the parallel signal line is related to the value of 16/n, when the value of n is larger, the cycle of the state machine is smaller, and when the value of n is smaller, the cycle of the state machine is larger.
Further, n is a signal line greater than 1bit and less than or equal to 8 bits, and the assignment of n is based on the layout space and cost of the single board in the design.
Still further, n =4.
In addition, the invention also provides a method for converting a single-board localbus bus with a CPU (central processing unit) into a 6-wire parallel bus protocol in data interaction among boards based on the parallel bus protocol, wherein the 6-wire parallel bus refers to 1 CLK (clock) signal wire, 1 frame starting signal wire frame and 4 parallel signal wires are used for transmitting a read-write flag bit, an address signal and a data signal, and the method comprises the following steps:
102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 to indicate a read-write state machine, and triggering the counting of a counter by using the edges of the valid signals cs, rd and wr of localbus sent by a CPU; defining a 4-bit R _ ad [3:0] register, giving an initial value of 0, and transmitting information such as address data to 4 parallel signal lines; defining a 1bit r _frame, with an initial value of 1, for passing the signal to the frame start signal line frame;
103, when detecting that the cs, rd signal is valid, triggering the R _ cycle _ cnt counter to add 1, and meanwhile judging that when R _ cycle _ cnt =1, R _ frame is assigned with 0 to mark the beginning of the read-write cycle, and R _ ad is assigned with a read indication signal of 4' h0 to indicate CPU to read;
in step 104, when R _cycle _cnt =2 to 6, R _ ad is assigned with register address of 5 groups of 20 bits and sent to the slave device, and when R _ cycle _ cnt =2, R _ frame is assigned with 1;
in step 107, when R_cycle _cnt =2 to 6, R _ ad assigns a register address of 5 groups of 20 bits to the slave device;
and step 110, ending the read-write period, entering an Idle state, and after waiting for the start of the next read-write period, assigning the value of R _ frame to 1 and keeping R _ad.
Corresponding to the method, the invention also provides a method for realizing the conversion of 6-wire parallel bus protocol to localbus of the single board without CPU in the data interaction between the boards based on the parallel bus protocol, wherein the 6-wire parallel bus refers to 1 CLK signal wire, 1 frame starting signal wire frame and 4 parallel signal wires are used for transmitting read-write flag bits, address signals and data signals; the method comprises the following steps:
step S101, after the system is powered on, the whole board logic is reset and subjected to reset-releasing processing, and all the counters and the state machine are operated by taking clk clocks sent by a single board with a CPU as reference;
step S102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0, which is used for indicating a read-write state machine, defining a read enable R _ rd _ en _ n, a write enable R _ wr _ en _ n, a chip select R _ lb _ cs _ n, a read valid signal R _ lb _ rd _ n, a write valid signal R _ lb _ wr _ n all assigned 1, and defining a frame start signal R _ frame _ n assigned 1; defining a register R _ ad with 4 bits to be assigned with an initial value of 0, wherein the register R _ ad is used for butting 4-wire parallel signal wires with a CPU single board;
step S103, assigning a frame starting signal frame sent by a single board with a CPU to R _ frame _ n, when the R _ frame _ n is detected to be equal to 0, assigning 1 to R _ cycle _ cnt, triggering a counter, and simultaneously judging the value of R _ ad; if R _ ad is equal to 4' h0, assigning R _ rd _ en _ n to be equal to 0, entering a read state machine, and executing S104; if R _ ad is equal to 4' h1, assigning R _ wr _ en _ n to be equal to 0, entering a write state machine, and executing S108;
step S104, entering a read state machine, wherein R _ cycle _ cnt is equal to 1 to 5, the register address of the received 5 groups of 20 bits is assigned to R _ lb _ addr [19 0], and R _ lb _ cs _ n is assigned 0 when R _ cycle _ cnt = 5;
step S105, when R _ cycle _ cnt =6, assigning R _ lb _ rd _ n =0;
step S106, after waiting a certain period, namely after meeting the address establishment time of the board equipment, setting R _ lb _ cs _ n and R _ lb _ rd _ n to 1, simultaneously sending out the values of the corresponding address registers of the board to 1 group, and then sending out 3 groups, and totally 16-bit data;
step S107, when the R _ cycle _ cnt is other values, each defined register is in a holding state, and the reading cycle is finished;
step S108, entering a write state machine, assigning a register address of R _ cycle _ cnt equal to 1 to 5 to receive 5 sets of 20 bits to R _ lb _ addr [ 19;
step S109, when R _ cycle _ cnt =10, setting R _ lb _ wr _ n to 0;
step S110, after waiting a certain period, the setup holding time of the EPLD register of the board or the setup holding time of other slave devices of the board needs to be met, and then R _ lb _ wr _ n is set to 1; setting R _ lb _ cs _ n to 1 in the next clock cycle;
step S111, when the R _ cycle _ cnt is other values, each defined register is in a holding state, and the writing cycle is finished;
step S112, the read-write cycle is ended, the Idle state is entered to wait for the start of the next read-write cycle, the signals R _ rd _ en _ n, R _ wr _ en _ n, R _ lb _ cs _ n, R _ lb _ rd _ n, R _ lb _ wr _ n, and R _ frame _ n are all set to 1, indicating an invalid state, and R _ lb _ addr is maintained.
In conclusion, the invention has the following beneficial effects: compared with the existing IFC bus number output by the CPU and the serial bus access efficiency, the invention greatly improves. Compared with the IFC bus, the parallel bus saves the cost of the connector in the number of buses; compared with serial buses such as SMI and the like, the access efficiency is greatly improved, and the limitation of accessing an address space does not exist.
Drawings
FIG. 1 is a method for converting a single-board localbus bus with a CPU provided by the invention into a 6-wire parallel bus protocol of the invention;
FIG. 2 is a method for converting 6-wire parallel bus protocol to localbus on a single board without CPU provided by the present invention.
Detailed Description
The invention will be described in further detail with reference to examples of embodiments shown in the drawings, which should not be construed as limiting the invention in any way.
Based on the defects that the prior art has the defects that the cost of equipment is increased by accessing the localbus with the CPU, the bus access period is long without two lines of SMIs with the CPU and the like, the parallel coding and decoding bus provided by the invention has the advantages that the cost is saved, the access period is shortened, the access efficiency is improved and the like.
A parallel bus protocol is applied to a scene of performing data interaction between two editable logic devices crossing a single board by using a parallel data bus and a localbus bus of a CPU (central processing unit) so as to complete the access of the single board with the CPU to the single board without the CPU, wherein the parallel data bus comprises a clock signal line, an initial signal line and n parallel signal lines; the edge of the clock signal line is used for reading and writing the n-bit parallel signal line; the start signal line indicates the start of the read/write state machine with a low level or a high level; the n-bit parallel signal line is used for transmitting a read-write indicating signal, a multi-bit address signal and a 16-bit data signal; the period of a read-write state machine of the parallel signal line is related to the value of 16/n, when the value of n is larger, the period of the state machine is smaller, and when the value of n is smaller, the period of the state machine is larger;
in addition, n is a signal line with more than 1bit and less than or equal to 8 bits, the assignment of n is based on the layout space and cost of a single board in the design, and the application of the parallel bus protocol of the present invention is specifically discussed below with n = 4:
specifically, as shown in fig. 1, in the method for converting a single board localbus bus with a CPU into a 6-line parallel bus protocol of the present invention, a 6-line parallel bus in this example refers to 1 CLK signal line, 1 frame start signal line frame, and 4 parallel signal lines for transmitting read-write flag bits, address signals, data signals, and the like.
Firstly, 101 is executed, after the system is powered on, the whole board logic is reset, and the reset processing is carried out. After the reset is released, the Localbus clock output by the CPU is assigned to the CLK signal line of the invention and is sent to other single boards. And all counters and state machine operations in this example are referenced to this clock.
Then executing 102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 to indicate a read-write state machine, and triggering the counting of a counter by using the effective signal edges of the localbus signals cs, rd, wr and the like sent by a CPU; defining a 4-bit R _ ad [3:0] register, assigning an initial value of 0, and transmitting information such as address data to a 4-bit parallel signal line in the invention; a 1bit r _frameis defined, with an initial value of 1, for passing the signal to the frame start signal line frame in the present invention.
103 triggers the R _ cycle _ cnt counter to increment by 1 when the cs, rd signal is detected to be active, and determines that R _ frame is asserted to 0 when R _ cycle _ cnt =1, indicating the beginning of a read-write cycle, and R _ ad is asserted to read indication signal 4' h0, indicating CPU read.
When R _cycle _cnt =2 to 6 is executed 104, R _ ad is assigned a register address of 5 groups of 20 bits to be sent to the slave device, and when R _ cycle _ cnt =2, R _ frame is assigned 1.
And executing 105, after the address is sent, waiting for a certain number of clock cycles, specifically determining according to a slave device localbus reading time sequence, and after waiting for a certain period, sequentially receiving 4 groups of 16-bit data from the 4-bit parallel signal line to the CPU of the local board to finish the reading operation of the CPU.
106 when detecting that the cs, wr signal is valid, triggering the R _ cycle _ cnt counter to increment by 1, and meanwhile judging that when the R _ cycle _ cnt =1, the R _ frame is assigned with 0 to mark the beginning of the read-write cycle, and the R _ ad is assigned with a write indication signal of 4' h1 to indicate the CPU to write.
When 107R _cycle _cnt =2 to 6 are executed, R _ ad is assigned a register address of 5 groups of 20 bits to the slave device.
And executing 108, after the address is sent, immediately assigning 4 groups of 16-bit data to the R _ ad when the R _ cycle _ cnt =7 to 10, and sending the data to the slave device to finish the writing operation of the CPU.
And when the read-write period is ended, entering Idle to wait for the beginning of the next read-write period, assigning the value of R _ frame to be 1, and keeping R _ad.
As shown in FIG. 2, the method for converting 6-wire parallel bus protocol to localbus of a single board without CPU provided by the invention. The 6-wire parallel bus in this example refers to 1-bit CLK signal line, 1-bit frame start signal line frame, and 4-bit parallel signal lines for transmitting read-write flag bits, address signals, data signals, and the like.
First, S101 is executed, and after the system is powered on, the whole board logic is reset and reset is released. In this example, all the counters and the state machine are operated by referring to the clk clock sent from the board with the CPU.
Then executing S102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 for indicating a read-write state machine, defining a read enable R _ rd _ en _ n, a write enable R _ wr _ en _ n, a chip select R _ lb _ cs _ n, a read valid signal R _ lb _ rd _ n, a write valid signal R _ lb _ wr _ n and the like all assigned with 1, and defining a frame start signal R _ frame _ n assigned with 1; a register R _ ad with 4 bits is defined to be assigned with an initial value of 0 and is used for butting 4-wire parallel signal wires with a CPU single board.
S103, assigning a frame starting signal frame sent by the CPU single board to R _ frame _ n, and when the R _ frame _ n is detected to be equal to 0, assigning 1 to R _ cycle _ cnt, triggering a counter, and simultaneously judging the value of R _ ad. If R _ ad is equal to 4' h0, assigning R _ rd _ en _ n to be equal to 0, entering a read state machine, and executing S104; if R _ ad is equal to 4' h1, the value R _ wr _ en _ n is equal to 0, the writing state machine is entered, and S108 is executed.
Execution S104 enters the read state machine, R _ cycle _ cnt equals 1 to 5 receive 5 sets of 20-bit register address assignments to R _ lb _ addr [19 0], and R _ lb _ cs _ n assigns 0 when R _ cycle _ cnt = 5.
And S105, when the R _ cycle _ cnt =6, assigning the R _ lb _ rd _ n =0.
S106, after waiting a certain period, namely meeting the address establishment time of the local board equipment, setting the R _ lb _ cs _ n and the R _ lb _ rd _ n to be 1, simultaneously sending out 1 group of values of the corresponding address register of the local board, and then sending out 3 groups of data with 16 bits.
S107, when the R _ cycle _ cnt has another value, each defined register is in a hold state. The read cycle ends.
S108, entering a write state machine, assigning a register address of R _ cycle _ cnt equal to 1 to 5 to receive 5 sets of 20 bits to R _ lb _ addr [19 0], receiving 4 sets of 16bit data immediately after R _ cycle _ cnt equal to 6 to 9, and setting R _ lb _ cs _ n to 0 when R _ cycle _ cnt = 9.
And S109, setting R _ lb _ wr _ n to 0 when R _ cycle _ cnt = 10.
S110, after waiting a certain period, the setup holding time of the EPLD register of the board or the setup holding time of other slave devices of the board needs to be met, and then R _ lb _ wr _ n is set to be 1; the next clock cycle sets R _ lb _ cs _ n to 1.
S111, when the R _ cycle _ cnt has another value, each defined register is in a hold state. The write cycle ends.
And S112, the read-write period is ended, idle is started to wait for the start of the next read-write period, signals of R _ rd _ en _ n, R _ wr _ en _ n, R _ lb _ cs _ n, R _ lb _ rd _ n, R _ lb _ wr _ n, R _ frame _ n and the like are all set to be 1, an invalid state is indicated, and R _ lb _ addr is kept.
The above-mentioned embodiments are only for convenience of description, and are not intended to limit the present invention in any way, and those skilled in the art will understand that the technical features of the present invention can be modified or changed by other equivalent embodiments without departing from the scope of the present invention.
Claims (4)
1. A method for realizing data interaction between boards by a parallel bus protocol is characterized in that: the parallel bus protocol is applied to a scene of performing data interaction between two editable logic devices across single boards by using a parallel data bus and a localbus bus of a CPU (central processing unit), so as to complete the access of the single board with the CPU to the single board without the CPU;
the parallel data bus comprises a clock signal line, a starting signal line and n parallel signal lines;
the clock signal line edge is used for reading and writing n-bit parallel signal lines;
the start signal line indicates the start of a read/write state machine with a low level or a high level;
the n-bit parallel signal line is used for transmitting a read-write indicating signal, a multi-bit address signal and a 16-bit data signal; the period of a read-write state machine of the parallel signal line is related to the value of 16/n, when the value of n is larger, the period of the state machine is smaller, and when the value of n is smaller, the period of the state machine is larger;
the method for realizing the inter-board data interaction comprises a method for converting a localbus bus with a CPU single board into a 6-line parallel bus protocol and a method for converting the 6-line parallel bus protocol without the CPU single board into the localbus bus, wherein the 6-line parallel bus refers to 1 CLK signal line, 1 frame starting signal line frame and 4 parallel signal lines for transmitting a read-write flag bit, an address signal and a data signal, and the method for converting the localbus bus with the CPU single board into the 6-line parallel bus protocol comprises the following steps:
step 101, after the system is powered on, resetting and resetting the logic of the whole board, and after the resetting is released, assigning a localbus clock output by a CPU to a CLK signal line and sending the clock to other single boards, wherein the clock is used as a reference for the running of all counters and state machines;
102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 to indicate a read-write state machine, and triggering the counting of a counter by using the edges of the valid signals cs, rd and wr of localbus sent by a CPU; defining a 4-bit R _ ad [3:0] register, assigning an initial value of 0, and transmitting information such as address data to 4 parallel signal lines; defining a 1bit r _frame, with an initial value of 1, for passing the signal to the frame start signal line frame;
103, when detecting that the cs, rd signal is valid, triggering the R _ cycle _ cnt counter to add 1, and meanwhile judging that when R _ cycle _ cnt =1, R _ frame is assigned with 0 to mark the beginning of the read-write cycle, and R _ ad is assigned with a read indication signal of 4' h0 to indicate CPU to read;
in step 104, when R _cycle _cnt =2 to 6, R _ ad is assigned with register address of 5 groups of 20 bits and sent to the slave device, and when R _ cycle _ cnt =2, R _ frame is assigned with 1;
step 105, after sending the address, waiting for a certain number of clock cycles, specifically determining according to a slave device localbus reading time sequence, and after waiting for a certain period, sequentially receiving 4 groups of 16-bit data from 4 parallel signal lines to a local board CPU (central processing unit) to complete the reading operation of the CPU;
step 106, when detecting that the signal cs and wr are effective, triggering an R _ cycle _ cnt counter to add 1, and meanwhile judging that when the R _ cycle _ cnt =1, the R _ frame is assigned with 0 to mark the beginning of a read-write cycle, and the R _ ad is assigned with a write indication signal 4' h1 to indicate CPU to write;
in step 107, when R_cycle _cnt =2 to 6, R _ ad assigns a register address of 5 groups of 20 bits to the slave device;
step 108, after the address is sent, immediately when R _ cycle _ cnt =7 to 10, R _ ad assigns 4 groups of data of 16 bits, and sends the data to the slave device to complete the writing operation of the CPU;
step 109, when the read/write state machine is still running and the R _ cycle _ cnt is other value, the R _ frame is kept and the R _ ad is kept;
and step 110, ending the read-write period, entering an Idle state, and after waiting for the start of the next read-write period, assigning the value of R _ frame to 1 and keeping R _ad.
2. The method according to claim 1, wherein the method comprises the following steps: the method for converting the 6-wire parallel bus protocol to the localbus bus of the single board without the CPU comprises the following steps of:
step S101, after the system is powered on, the whole board logic is reset and subjected to reset-releasing processing, and all the counters and the state machine are operated by taking clk clocks sent by a single board with a CPU as reference;
step S102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0, which is used for indicating a read-write state machine, defining a read enable R _ rd _ en _ n, a write enable R _ wr _ en _ n, a chip select R _ lb _ cs _ n, a read valid signal R _ lb _ rd _ n, a write valid signal R _ lb _ wr _ n all assigned 1, and defining a frame start signal R _ frame _ n assigned 1; defining a register R _ ad with 4 bits to be assigned with an initial value of 0, wherein the register R _ ad is used for butting 4-wire parallel signal wires with a CPU single board;
step S103, assigning a frame starting signal frame sent by a single board with a CPU to R _ frame _ n, when the R _ frame _ n is detected to be equal to 0, assigning 1 to R _ cycle _ cnt, triggering a counter, and simultaneously judging the value of R _ ad; if R _ ad is equal to 4' h0, assigning R _ rd _ en _ n to be equal to 0, entering a read state machine, and executing S104; if R _ ad is equal to 4' h1, assigning R _ wr _ en _ n to be equal to 0, entering a write state machine, and executing S108;
step S104, entering a read state machine, wherein R _ cycle _ cnt is equal to 1 to 5, the register address of the received 5 groups of 20 bits is assigned to R _ lb _ addr [19 0], and R _ lb _ cs _ n is assigned 0 when R _ cycle _ cnt = 5;
step S105, when R _ cycle _ cnt =6, assigning R _ lb _ rd _ n =0;
step S106, after waiting a certain period, namely after meeting the address establishment time of the equipment of the board, setting the R _ lb _ cs _ n and the R _ lb _ rd _ n to be 1, simultaneously sending out the values of the corresponding address registers of the board from 1 group, and then sending out 3 groups, wherein the total number of the data is 16 bit;
step S107, when the R _ cycle _ cnt is other values, each defined register is in a holding state, and the reading cycle is finished;
step S108, entering a write state machine, assigning a register address of R _ cycle _ cnt equal to 1 to 5 to receive 5 sets of 20 bits to R _ lb _ addr [ 19;
step S109, when R _ cycle _ cnt =10, setting R _ lb _ wr _ n to 0;
step S110, after waiting a certain period, the setup holding time of the EPLD register of the board or the setup holding time of other slave devices of the board needs to be met, and then R _ lb _ wr _ n is set to 1; setting R _ lb _ cs _ n to 1 in the next clock cycle;
step S111, when the R _ cycle _ cnt is other values, each defined register is in a holding state, and the write cycle is finished;
step S112, the read-write cycle is ended, the Idle state is entered to wait for the start of the next read-write cycle, the signals R _ rd _ en _ n, R _ wr _ en _ n, R _ lb _ cs _ n, R _ lb _ rd _ n, R _ lb _ wr _ n, and R _ frame _ n are all set to 1, indicating an invalid state, and R _ lb _ addr is maintained.
3. The method according to claim 2, wherein the method comprises the following steps: n is a signal line with more than 1bit and less than or equal to 8 bits, and the assignment of n is based on the layout space and cost of the single board in the design.
4. The method according to claim 3, wherein the method comprises the following steps: n =4.
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