CN111651384B - Register reading and writing method, chip, subsystem, register set and terminal - Google Patents
Register reading and writing method, chip, subsystem, register set and terminal Download PDFInfo
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- CN111651384B CN111651384B CN202010508128.4A CN202010508128A CN111651384B CN 111651384 B CN111651384 B CN 111651384B CN 202010508128 A CN202010508128 A CN 202010508128A CN 111651384 B CN111651384 B CN 111651384B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the application discloses a register read-write method, a chip, a subsystem, a register set and a terminal, which belong to the technical field of register read-write, in the application, a central control module receives target identification information and corresponding target commands sent by a central processing unit in parallel, the central control module converts the information into serial data, the serial data is broadcast to at least two register sets which are controlled, the target commands are executed by the register set corresponding to the target identification information in the at least two register sets, the CPU is converted into serial data by adding the central control module, the register sets are connected to the central control module by signal wires when the register sets are added, the register sets and the signal wires are correspondingly removed when the register sets are reduced, the connection mode of all the register sets, a bus and the CPU does not need to be redesigned like before, and the design difficulty of the register sets is reduced.
Description
Technical Field
The embodiment of the application relates to the technical field of register reading and writing, in particular to a register reading and writing method, a chip, a subsystem, a register set and a terminal.
Background
In the field of SoC (System on Chip) design, in order to implement specified functions, a plurality of subsystems are typically designed on a Chip, and each subsystem typically includes a plurality of register sets. A Central Processing Unit (CPU) accesses the various subsystems within via a bus (bus).
In the related art, when a central processing unit needs to access a subsystem, data is sent to the subsystem in a parallel manner, and the subsystem decodes through a bus. When the bus finishes decoding, the register group can identify the information which finishes decoding, so that information can be read and written.
Disclosure of Invention
The embodiment of the application provides a register reading and writing method, a chip, a subsystem, a register set and a terminal. The technical scheme is as follows:
according to an aspect of the present application, there is provided a method for reading and writing registers, applied to a chip, where the chip includes a central processor, a central control module, and a subsystem, and the subsystem includes at least two register sets, the central control module is disposed between the central processor and the subsystem, and the central control module is configured to control data interaction between the central processor and the subsystem, and the method includes:
The central control module receives the target identification information and the corresponding target command sent by the central processor in parallel;
the central control module converts the target identification information and the corresponding target command into serial data, wherein the target identification information is positioned before the target command in the serial data;
the central control module broadcasts target identification information and a corresponding target command to a register group in the controlled subsystem in a serial mode;
and executing the target command by a first register group in the subsystem, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and the first register group is a register group corresponding to the target identification information in the at least two register groups.
According to another aspect of the present application, there is provided a method for reading and writing registers, applied to a subsystem, where the subsystem includes at least two register sets, the method includes:
the register group in the subsystem receives target identification information in a serial mode, wherein the target identification information is an identification of the register group broadcast by a central control module, the central control module is arranged between a central processor and the register group, and the central control module is used for controlling data interaction between the central processor and the register;
The register group in the subsystem receives a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and in the serial data, the target identification information is positioned before the target command;
executing the target command by a first register group in the subsystem, wherein the identification of the first register group is matched with the target identification information;
and a second register group in the subsystem does not respond to the target command, and the identification of the second register group is not matched with the target identification information.
According to another aspect of the present application, there is provided a method for reading and writing a register, applied to a register set, the method including:
receiving target identification information in a serial mode, wherein the target identification information is an identification of a register set broadcasted by a central control module, the central control module is arranged between a central processor and the register set, and the central control module is used for controlling data interaction between the central processor and the register set;
receiving a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data;
And executing the target command when the target identification information is matched with the identification of the register group.
According to another aspect of the present application, there is provided a chip comprising a central processor, a central control module and a subsystem, the subsystem comprising at least two register sets, the central control module being arranged between the central processor and the subsystem, and the central control module being arranged to control data interaction between the central processor and the subsystem,
the central control module is used for receiving the target identification information and the corresponding target command sent by the central processing unit in parallel;
the central control module is used for converting the target identification information and the corresponding target command into serial data, wherein the target identification information is positioned before the target command in the serial data;
the central control module is used for broadcasting target identification information and a corresponding target command to the at least two controlled register sets in a serial mode;
and executing the target command by a first register group in the subsystem, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and the first register group is a register group corresponding to the target identification information in the at least two register groups.
According to another aspect of the present application, there is provided a subsystem, the chip comprising at least two register sets:
the register group in the subsystem receives target identification information in a serial mode, wherein the target identification information is an identification of the register group broadcast by a central control module, the central control module is arranged between a central processor and the register group, and the central control module is used for controlling data interaction between the central processor and the register group;
the register group in the subsystem receives a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and in the serial data, the target identification information is positioned before the target command;
the first register group in the subsystem is used for executing the target command, and the identification of the first register group is matched with the target identification information;
and a second register group in the subsystem does not respond to the target command, and the identification of the second register group is not matched with the target identification information.
According to another aspect of the present application, there is provided a register set for receiving target identification information in a serial manner, the target identification information being an identification of the register set broadcast by a central control module, the central control module being disposed between a central processor and the register set, and the central control module being configured to control data interaction between the central processor and the register set;
receiving a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data;
and executing the target command when the target identification information is matched with the identification of the register group.
According to another aspect of the present application, there is provided a terminal including a chip provided in an embodiment of the present application.
According to another aspect of the present application, embodiments of the present application further provide a computer program product storing at least one instruction that is loaded and executed by a processor to implement a method for reading and writing registers as provided by embodiments of the present application.
The method for reading and writing the register is applied to a chip, the chip comprises a central control module and register groups, the central control module receives target identification information and corresponding target commands sent by a central processing unit in parallel, the central control module converts the information into serial data, in the serial data, the target identification information is positioned before the target commands, the central control module broadcasts the information to at least two controlled register groups in a serial mode, the register groups corresponding to the target identification information in the at least two register groups execute the target commands, information interaction between the register groups and the central processing unit is completed without a bus system, the CPU is converted into a serial mode by additionally arranging the central control module, the register groups are connected to the central control module through signal lines later when the register groups are added, the register groups and the signal lines are removed correspondingly when the register groups are reduced, the connection mode of all the register groups, a bus and the CPU is not required to be redesigned like before, and the design difficulty of adding new or reducing the register groups in the chip design is reduced.
Drawings
In order to more clearly describe the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a terminal according to an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram of a standard bus based register access architecture;
FIG. 3 is a schematic diagram of a register access architecture provided in an exemplary embodiment of the present application;
FIG. 4 is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application;
FIG. 5 is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application;
FIG. 6 is a flow chart of a method for reading and writing registers provided in an exemplary embodiment of the present application;
FIG. 7 is a schematic diagram of a finite state machine of a register set according to an embodiment of the present application;
FIG. 8 is a flow chart of a method for reading and writing registers provided in an exemplary embodiment of the present application;
FIG. 9 is a schematic diagram of a finite state machine of a central control module according to an embodiment of the present application;
FIG. 10 is a flow chart of a method for reading and writing registers according to another exemplary embodiment of the present application;
FIG. 11 is a flow chart of a method for reading and writing registers according to another exemplary embodiment of the present application;
FIG. 12 is a schematic diagram of a serial signal write timing based on one of the register sets shown in FIG. 4;
fig. 13 is a schematic diagram based on a timing of serially reading data from the register set shown in fig. 4.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "connected," "connected" and "connected" are to be construed broadly, and for example, can be either fixedly connected, detachably connected, or integrally connected; can be a mechanical connection or an electrical connection; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in the light of the specific circumstances. Furthermore, in the description of the present application, unless otherwise indicated, "a plurality" means two or more. "and/or", describes an association relationship of an association object, meaning that three relationships can exist, for example, a and/or B, can be represented: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
For ease of understanding of the schemes shown in the embodiments of the present application, several terms appearing in the embodiments of the present application are described below.
Serial mode: in one signal line, data is transferred from the central control module to the register set by way of a queue. For example, data "010101" would be transferred from the central control module to the register bank one by one in the signal line.
Target identification information: this information is an identification of the register set broadcast by the central control module. In one possible implementation, the target identification information includes a target keyword and identification data. For example, if the target information is "111+010", it indicates that the target keyword is "111", and the identification data is "010". In this application, different numerical target keywords are used to represent different keywords. When the target key is a value of "111", it means that the target key is a target key and the register identification is "010".
Target command: including both read and write data, the target command is used to instruct the register set to output the saved second data when the command is used to read data from the register set. When a target command is used to write data into a register set, the command is used to instruct the register set to write first data.
Optionally, the target command includes a command key. Optionally, the command key includes a write key and a read key. When the command key is a write key, the type of the target command is a write type. When the command key is a read key, the type of the target command is a read type.
Optionally, when the type of the target command is a write type, the target command includes a write key and first data. The register set can determine the data which needs to be stored in the register set, namely the first data, according to the write-in key words, and then the first data is stored in the register set.
Optionally, when the type of the target command is a read type, the target command includes a read key and second data. The register set can learn that the register set needs to output the second data outwards according to the read key words, and then the register set outputs the second data outwards.
The method for reading and writing the register shown in the embodiment of the present application can be applied to a terminal, where the terminal includes a chip shown in the embodiment of the present application, and includes a register set in the chip shown in the embodiment of the present application. Optionally, the terminal includes a mobile phone, a tablet computer, a laptop computer, a desktop computer, a computer all-in-one machine, a server, a workstation, a television, a set-top box, smart glasses, a smart watch, a digital camera, an MP4 playing terminal, an MP5 playing terminal, a learning machine, a point-to-read machine, an electronic book, an electronic dictionary, a vehicle-mounted terminal, a Virtual Reality (VR) playing terminal, an augmented Reality (Augmented Reality, AR) playing terminal, or the like.
On the other hand, the embodiment of the application can also be applied to a chip, and the chip can be applied to the terminal.
Referring to fig. 1, fig. 1 is a block diagram of a terminal according to an exemplary embodiment of the present application, and as shown in fig. 1, the terminal 10 includes a chip 100, where the chip 100 includes a processor 120, a memory 140, a subsystem 160, and a central control module 180, and at least one instruction is stored in the memory 140, where the instruction is loaded and executed by the processor 120 to implement a register read-write method according to various method embodiments of the present application. Optionally, the processor 120 is a central processor. The chip 100 includes a central processor, a central control module 180 and a subsystem 160, the central control module 180 is disposed between the central processor and the subsystem 160, and the central control module 180 is used for controlling data interaction between the central processor and the subsystem 160.
The Memory 140 can include a random access Memory (Random Access Memory, RAM) and can also include a Read-Only Memory (ROM). Optionally, the memory 140 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 140 may be used to store instructions, programs, code sets, or instruction sets. The memory 140 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described below, etc.; the storage data area may store data and the like referred to in the following respective method embodiments.
The subsystem 160 can be located external to the processor. Optionally, a central control module 180 is provided between the processor and the subsystems for controlling the data interaction of the central control module 180 with the respective subsystems, writing data in the subsystems or reading data from the subsystems. Illustratively, the subsystem 160 may be implemented as a set of physical circuitry. At least two register sets are included in subsystem 160. For example, subsystem 160 includes a register set 161 and a register set 162.
In this application, the chip 100 performs the following steps: the central control module receives the target identification information and the corresponding target command sent by the central processing unit in parallel; the central control module converts the target identification information and the corresponding target command into serial data, wherein the target identification information is positioned in front of the target command in the serial data; the central control module broadcasts target identification information and a corresponding target command to the at least two controlled register groups in a serial mode; the first register set executes a target command, wherein the target command is used for indicating the register set to write first data or indicating the register set to output stored second data, and the first register set is a register set corresponding to target identification information in at least two register sets.
In this application, subsystem 160 performs the following steps: the register group in the subsystem receives target identification information in a serial mode, wherein the target identification information is the identification of the register group broadcasted by the central control module; the register group in the subsystem receives a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and in the serial data, the target identification information is positioned before the target command; the first register set is used for executing the target command, and the identification of the first register set is matched with the target identification information; the second register set does not respond to the target command, and the identification of the second register set is not matched with the target identification information.
In this application, register set 161 or register set 162 performs the following steps: receiving target identification information in a serial mode, wherein the target identification information is an identification of a register set broadcasted by a central control module, the central control module is arranged between a central processor and the register set, and the central control module is used for controlling data interaction between the central processor and the register; receiving a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data; and executing the target command when the target identification information is matched with the identification of the register group.
Referring to fig. 2, fig. 2 is a schematic diagram of a standard bus-based register access architecture. In fig. 2, a central processor 210 interacts with various subsystems via a top bus 220. In fig. 2, subsystem 1, subsystem 2 and a total of 3 subsystems are included. Taking the subsystem 1 as an example, a process of performing data interaction between a register set in the subsystem 1 and a central processing unit is described.
When the cpu 210 needs to write data to the register set_2 in the subsystem 1, the cpu 210 adds the address of the register set_2 in the subsystem 1 to the data header to be written, sends the data to the top bus 220, and the top bus 220 transfers the data to the subsystem bus 231, the subsystem bus 241 and the subsystem bus In line 251. And the data are decoded by matching each subsystem bus with the standard bus. When the address of the decoded register set_2 is the same as the address of the register set corresponding to the standard bus, the standard bus 2A writes the data into the register set_2. Schematically, the number of cables of a standard bus is of the order of 10 1 The standard bus is relatively complex. When a new subsystem or a new register group is required to be added in the chip, the workload of debugging the corresponding subsystem bus and the standard bus is increased, so that the difficulty of modularized development of the chip is increased. Alternatively, the standard bus is an AHB (Advanced High performance Bus, high performance cable), APB (Advanced Peripheral Bus, peripheral bus) or other cable capable of performing the bus function.
Aiming at the limitation existing in the register read-write architecture, the application provides a new register read-write architecture, which is also called a register read-write control protocol and is introduced as follows.
Referring to fig. 3, fig. 3 is a schematic diagram of a register access architecture according to an exemplary embodiment of the present application. In fig. 3, central processor 210 communicates with central control module (central control) 310 via bus 3A, central control module 310 communicates with subsystem 1, subsystem 2, and subsystem k via signal line 320. The signal line 320 is a 1-bit (bit) cable. Note that the arrow points in fig. 3 indicate the data flow direction. In fig. 3, a central control module is disposed between the central processor and the register set, and the central control module is used to control data interaction between the central processor and the register.
In another possible approach, the signal line 320 is a 2 bit (bit) cable. Referring to fig. 4, fig. 4 is a schematic diagram of a register access architecture according to an exemplary embodiment of the present application. The 2-bit signal line (line) includes a Command (CMD) line 410 and a Data (DAT) line 420. Alternatively, in FIG. 4, command line 410 is bit [0], data line 420 is bit [1], and the architecture shown in FIG. 4 is a read-write architecture for a register set under a 2-bit serial control protocol. Note that the arrow points in fig. 4 indicate the data flow direction. Wherein the direction in which the command lines 410 transfer data is unidirectional from the central control module to the register set. The direction in which the data lines 420 transfer data is bi-directional between the central control module and the register set.
In another possible approach, the signal line 320 is a 3 bit (bit) cable. Referring to fig. 5, fig. 5 is a schematic diagram of a register access architecture according to an exemplary embodiment of the present application. The 3-bit signal lines (lines) include a Command (CMD) line 510, a write data line 520, and an output data line 530. The arrow in fig. 5 indicates the data flow direction. Wherein the direction in which the command lines 510 transmit data is unidirectional from the central control module to the register file. The direction in which write data lines 520 transfer data is unidirectional from the central control module to the register file. The direction in which the output data lines 530 transmit data is unidirectional from the register set to the central control module.
Alternatively, among the register sets shown in fig. 3 to 5, the respective register sets share the same reset and clock. That is, when the register set needs to be reset, all the register sets in any one of fig. 3 to 5 will be reset. Meanwhile, all register sets in any one of fig. 3 to 5 share the same clock.
Optionally, data interaction is performed between the register set and the central control module through a signal line, and the signal line is used for serially transmitting data.
Referring to fig. 6, fig. 6 is a flowchart of a method for reading and writing registers according to an exemplary embodiment of the present application. The method for reading and writing the register can be applied to the chip shown in any one of fig. 1, 3 to 5. In fig. 6, the method for reading and writing a register includes:
in step 610, the target identification information is received in a serial manner, where the target identification information is an identification of a register set broadcasted by the central control module.
In the embodiment of the application, the register set can receive the target identification information in a serial manner. The register set can obtain the target identification information broadcasted by the central control module through any one of the architectures from fig. 3 to fig. 5.
In the embodiment of the application, the central control module is arranged between the central processing unit and the register set, and the central control module is used for controlling data interaction between the central processing unit and the register set.
Alternatively, taking the architecture shown in FIG. 4 as an example, the register set will obtain the target key via command line 410 and the identification data via data line 420. The control protocol of the register set side is described by taking the register set as a slave (slave) as an example.
It should be noted that, in the embodiment of the present application, the register set is designed as an assembly including N registers, and each register includes an M-bit storage space. In the present application, the register set can read all n×m bits of data, or write data to be written into the n×m bits of space. It should be noted that, the values of N and M are positive integers, and N and M are both instantiation parameters (instantiation parameter), which are not limited in this application.
In table one, the data direction indicates the direction of data flow with the register set as a reference point. For example, a write indicates that data is written from the central control module to the register set and a read indicates that data is read out of the register set. In the present embodiment, when data "111" appears in the command line, it means that the register identification will be transferred in the data line. At this time, the register set will read the k-bit long register set identification from the data line. Note that k is also an instantiation parameter.
Alternatively, when data "101" appears in the command line, it indicates that data written in n×m bits will be transferred in the data line.
In step 620, a target command is received in a serial manner, where the target command is used to instruct the register set to write the first data, or instruct the register set to output the saved second data.
In the embodiment of the application, the register set will receive the target command in a serial manner. Optionally, the register set includes a decoding module. The decode module is capable of receiving the target identification information in a serial manner and receiving the target command when the target identification information matches the identification of the register set.
In this embodiment of the present application, optionally, when the target identification information matches with the identification of the register set and the type of the target command is a write type, the register set may write the data sent by the central control module into the storage space of the entire register set. Alternatively, the register set can output all data in the register set to the central control module when the target identification information matches the identification of the register set and the type of the target command is a read type.
Optionally, in the method for reading and writing a register provided in the present application, the register set includes a finite state machine, which is described below.
Referring to fig. 7, fig. 7 is a schematic diagram of a finite state machine of a register set according to an embodiment of the present application. In FIG. 7, the register set is in an idle state 710, capable of receiving k bits of data from the data line after receiving data "111" from the command line (i.e., step 720). When the register set does not match the identification of the register set (i.e., id_match= '0'), the register set continues to transition to the idle state. When the register set matches the identification of the register set (i.e., id_match= '1'), the reception target command is executed (i.e., step 730). Subsequently, when data "101" is received from the command line, a write data state is entered (i.e., step 740), n×m bits of data are written to the register set, and then an idle state is entered. On the other hand, when data "110" is received from the command line, a read data state is entered, the n×m bits of data in the register set are fetched (i.e., step 750), and then an idle state is entered.
In summary, in the method for reading and writing a register provided in this embodiment, the register set receives, in a serial manner, target identification information, where the target identification information is an identification of the register set broadcast by the central control module, and receives, in a serial manner, a target command, where the target command is used to instruct the register set to write first data, or instruct the register set to output stored second data, and when the target identification information matches with the identification of the register set, execute the target command. The register group can be connected to the central control module through the signal wire when the register group is added, and the connection mode of all the register groups, buses and the CPU is not required to be redesigned like the prior art when the register group is reduced, so that the design difficulty of newly adding or reducing the register group in a chip is reduced.
Optionally, because the present application provides the signal line as connecting the central control module and the register set, therefore, in the related art, the embodiment of the present application can also effectively reduce the bus bit width that is caused by data transmission through the bus, bring the space pressure to the wiring work of the register set and increase the complexity of the bus design, and effectively reduce the routing difficulty from the central control module to the register set.
Referring to fig. 8, fig. 8 is a flowchart of a method for reading and writing registers according to an exemplary embodiment of the present application. The method for reading and writing the register can be applied to the chip shown in any one of the above figures 1, 3 to 5, wherein the chip comprises a central control module and a register set. In fig. 8, the method for reading and writing a register includes:
in step 810, the central control module receives the target identification information and the corresponding target command sent by the central processor in parallel.
In the embodiment of the application, the central control module receives the data sent by the central processing unit in a parallel manner. Accordingly, when the central processing unit needs to write data into the register set or read data from the register set, the central processing unit will send the target identification information and the target command corresponding to the target identification information to the central control module in parallel.
In step 820, the central control module converts the target identification information and the corresponding target command into serial data, wherein the target identification information is located before the target command in the serial data.
In the embodiment of the application, the central control module has a data conversion function and can convert data received in parallel into serial data. In the serial data converted by the central control module, the target identification information is positioned before the target command.
In step 830, the central control module broadcasts the target identification information and the corresponding target command in a serial manner to the register set in the controlled subsystem.
Illustratively, if the central control module controls m register sets, the central control module can broadcast the target identification information and the corresponding target command to the m register sets in a serial manner. It should be noted that m register sets may belong to several subsystems, respectively. Wherein one subsystem comprises at least two register sets.
In step 840, a first register set in the subsystem executes a target command, where the target command is used to instruct the register set to write first data, or is used to instruct the register set to output stored second data, and the first register set is a register set corresponding to the target identification information in at least two register sets.
Referring to fig. 9, fig. 9 is a schematic diagram of a finite state machine of a central control module according to an embodiment of the present application. In fig. 9, the central control module starts in the idle state 910, broadcasting the target key to the controlled register set, i.e. transmitting data "111" from the command line (i.e. executing step 920); subsequently, k bits long data is sent from the data line (i.e., step 930 is performed); the target command is then broadcast to the controlled register set (i.e., step 940 is performed). When the data sent from the command line is "101", the central control module writes n×m bits of data from the data line into the register set (i.e., step 950 is performed). When the data sent from the command line is "110", the central control module reads the n×m bits of data obtained from the register set from the data line (i.e., step 960 is performed). When step 950 or step 960 is completed, the central control module returns to the idle state.
In summary, the method for reading and writing the register provided in the application is applied to a chip, the chip comprises a central control module and a register group, the central control module receives the target identification information and the corresponding target command sent by the central processing unit in parallel, the central control module converts the information into serial data, in the serial data, the target identification information is located before the target command, the central control module broadcasts the information to at least two controlled register groups in a serial mode, the register group corresponding to the target identification information in the at least two register groups executes the target command, the information interaction between the register groups and the central processing unit is completed without a bus system, the data sent by the CPU in parallel mode is converted into the serial mode by additionally arranging the central control module, the register groups are connected to the central control module through signal lines later when the register groups are added, the register groups and the signal lines are removed correspondingly when the register groups are reduced, the connection mode of all the register groups with a bus and the CPU is not needed as in the past, and the new design of the register groups in the chip design is reduced.
Optionally, since the embodiment of the present application can also identify the register set by the identifier of the register set, rather than identifying the register set by address decoding in the related art, the identifier of the register set is smaller than the data size of the address. Therefore, the embodiment of the application reduces the difficulty of finding the corresponding register group by the central processing unit, thereby improving the efficiency of reading and writing data from the corresponding register group.
Optionally, since the embodiment of the application designs a simple signal line between the register set and the central control module, the logic complexity of the decoding work of the register set is reduced, so that the design difficulty of adding the register set for a chip is greatly reduced.
Optionally, in the embodiment of the present application, the central control module performs unified read-write management on the data of the controlled register set, and performs conversion between parallel and serial data, so that it is easier for the central processor to read and write the data of the register set in the system.
Optionally, the solution provided by the embodiment of the present application designs a logically simple data read-write standard between the central control module and the register set. Therefore, the embodiment of the application is also beneficial to complicating a static control chip or a bus interface and spending a larger chip, or a chip which needs a unified central control module to control all register groups so as to realize special functions realizes higher data reading and writing efficiency, and reduces the development difficulty of the chip when the register groups are increased or decreased.
The embodiment of the application also can provide a read-write method applied to the register in the subsystem. Referring to fig. 10, fig. 10 is a flowchart of a method for reading and writing a register according to another exemplary embodiment of the present application. In fig. 10, the method for reading and writing the register includes:
in step 1001, a register set in the subsystem receives the target identification information in a serial manner.
The target identification information is an identification of a register set broadcasted by a central control module, the central control module is arranged between the central processor and the register set, and the central control module is used for controlling data interaction between the central processor and the register.
Illustratively, each register set in the subsystem receives the target identification information in a serial manner. For example, if the subsystem and central control module are connected in the manner shown in fig. 3, subsystem 2 is taken as an example. Register set_1, register set_2, and register set_3 in subsystem 2 are each capable of receiving the target identification information through the signal lines.
In step 1002, a register set in the subsystem receives a target command in a serial manner.
The target command is used for indicating the register group to write the first data or indicating the register group to output the stored second data, and the target identification information is positioned before the target command in the serial data.
Illustratively, the register set will receive the target command after receiving the target identification information. The register set in the subsystem receives serial data in which the target identification information precedes the target command.
In step 1003, a first register set in the subsystem executes the target command, and an identification of the first register set matches the target identification information.
In step 1004, the second register set in the subsystem does not respond to the target command, and the identification of the second register set does not match the target identification information.
Optionally, after the register set receives the target identification information and the target command, the register set will compare whether the own identification and the target identification information match. In the subsystem, the register group whose own identification and target identification information match is the first register group. The register set whose own identification and target identification information do not match is the second register set.
Further, the first register set and the second register set in the subsystem will react differently to the target command. Wherein a first register set in the subsystem will execute the target command and a second register set will not respond to the target command.
In summary, according to the register read-write method executed by the subsystem disclosed in the embodiments of the present application, when the register set is added in the subsystem, the register set is connected to the central control module through the signal line, and when the register set is reduced, the register set and the signal line are removed correspondingly, so that the connection mode of redesigning all the register sets, buses and CPUs in the past is not required, the design difficulty of adding or reducing the register set for the subsystem in the chip design is reduced, and the difficulty of adding or reducing the subsystem in the whole is improved.
The embodiment of the application also provides a method for reading and writing the registers in which the register group and the central control module participate simultaneously, which is described as follows.
Referring to fig. 11, fig. 11 is a flowchart of a method for reading and writing a register according to another exemplary embodiment of the present application. The method for reading and writing the register can be applied to the chip shown in any one of the above fig. 1, 3 to 5. In fig. 11, the method for reading and writing the register includes:
in step 1011, the central control module broadcasts a target key to the controlled register set during a first period.
The target key is used for indicating that the data sent in the second period represents the identifier of the specified register group, that is, the content of the data sent in the second period can be determined to be the identifier corresponding to a certain register group through the target key.
Correspondingly, the register group indicates the decoding module to receive the target keyword in the first period, and the target keyword is used for indicating the meaning represented by the data received in the second period. For example, in one possible manner, the target key is "001" for indicating that the data received during the second period represents the identification data, i.e., the data received during the second period represents the ID of the register set.
In step 1012, the central control module broadcasts identification data to the controlled register set during a second period.
Wherein the target keyword and the identification data belong to target identification information.
Correspondingly, the register group receives the identification data in the second period, and the target key words and the identification data belong to the target identification information. Illustratively, the end time of the first period is earlier than or equal to the start time of the second period.
In step 1013, the central control module broadcasts a command key to the controlled register set during a third period.
Wherein the command key is used to indicate a type of the target command, the type of the target command including one of a read type or a write type.
Accordingly, the register set, in the third period, when the identification data matches the identification of the register set, instructs the decoding module to receive a command key for indicating a type of the target command, the type of the target command including one of a read type or a write type.
In one possible embodiment, when the identification data does not match the identification of the register set, the decode module will no longer receive the subsequent command key. Or the decoding module does not decode and identify the operation key received subsequently.
In step 1014, the central control module broadcasts or reads corresponding data according to the type of the target command during the fourth period.
Correspondingly, the register group transmits data to the central control module or receives and reads the data sent by the central control module according to the type of the target command in the fourth period.
Illustratively, the end time of the first period is earlier than or equal to the start time of the second period, the end time of the second period is earlier than or equal to the start time of the third period, and the end time of the third period is earlier than or equal to the start time of the fourth period.
In the embodiment of the present application, the central control module may further implement a data writing or reading function by executing the step (1) or the step (2).
In the fourth period, when the type of the target command is a write type, the central control module broadcasts the first data to the controlled register set.
Accordingly, in the fourth period, when the type of the target command is the write type, the register set holds the first data.
And (2) in the fourth period, when the type of the target command is a reading type, the central control module reads the second data from the register group corresponding to the target identification information.
Accordingly, in the fourth period, when the type of the target command is the read type, the second data is output to the central control module.
In one possible implementation, the architecture shown in fig. 4 is taken as an example. The central control module interacts with the register set through command lines and data lines. Referring to fig. 12, fig. 12 is a schematic diagram showing a timing of writing serial signals based on the register set shown in fig. 4. The command line 410 serially transmits the target keyword "111" in the first period 11A. The data line 420 serially transmits the identification data "10100001" in the second period 11B. The command line 410 serially transmits a write key "101" indicating writing data into the register set in the third period 11C. The data line 420 serially transmits 128 bits of data in the fourth period 11D.
In another possible implementation, the architecture shown in fig. 4 is taken as an example. The central control module interacts with the register set through command lines and data lines. Referring to fig. 13, fig. 13 is a schematic diagram based on a timing of serially reading data from the register set shown in fig. 4. The command line 410 serially transmits the target keyword "111" in the first period 11E. The data line 420 serially transmits the identification data "10100001" in the second period 11F. The command line 410 serially transmits a read key "110" indicating serial reading of 128-bit data from the register set in the third period 11G. The data line 420 serially transmits 128 bits of data in the fourth period 11H.
In summary, the present embodiment can be applied to a chip, the chip includes a central control module and register sets, the central control module receives, in parallel, target identification information and a corresponding target command sent by a central processing unit, the central control module converts the information into serial data, in the serial data, the target identification information is located before the target command, the central control module broadcasts the information to at least two controlled register sets in a serial manner, the register sets corresponding to the target identification information in the at least two register sets execute the target command, information interaction between the register sets and the central processing unit is completed without using a bus system, the data sent by the CPU in a parallel manner is converted into a serial manner by adding the central control module, the register sets are connected to the central control module through signal lines when the register sets are added, the register sets and the signal lines are removed correspondingly when the register sets are reduced, the connection manner of all the register sets and the bus and the CPU does not need to be redesigned as in the past, and the design of the new or reduced in the chip design is reduced
Embodiments of the present application also provide a computer readable medium storing at least one instruction that is loaded and executed by the processor to implement the register read-write method according to the above embodiments.
Embodiments of the present application also provide a computer program product storing at least one instruction that is loaded and executed by a processor to implement a method for reading and writing registers as provided by embodiments of the present application.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
Those of ordinary skill in the art will appreciate that all or a portion of the steps implementing the above-described embodiments can be implemented by hardware, or can be implemented by a program for instructing a relevant hardware, where the program can be stored in a computer readable storage medium, and the storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is merely illustrative of the possible embodiments of the present application and is not intended to limit the present application, but any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present application are intended to be included within the scope of the present application.
Claims (10)
1. A method for reading and writing registers, which is applied to a chip, wherein the chip comprises a central processing unit, a central control module and a subsystem, the subsystem comprises at least two register groups, the central control module is arranged between the central processing unit and the subsystem, and the central control module is used for controlling data interaction between the central processing unit and the subsystem, the method comprises:
the central control module receives the target identification information sent by the central processor and a target command corresponding to the target identification information in parallel;
the central control module converts the target identification information and the target command into serial data, wherein the target identification information is positioned before the target command in the serial data;
the central control module broadcasts the target identification information and the target command to a register group in the controlled subsystem in a serial mode;
and executing the target command by a first register group in the subsystem, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and the first register group is a register group corresponding to the target identification information in the at least two register groups.
2. The method of claim 1, wherein the central control module broadcasting the destination identification information and the destination command to the controlled set of registers in the subsystem in a serial manner, comprising:
in the first period, the central control module broadcasts a target keyword to the controlled register set, wherein the target keyword is used for indicating that the data sent in the second period represents the identification of the specified register set;
in the second period, the central control module broadcasts identification data to the controlled register set, wherein the target keyword and the identification data belong to the target identification information;
in a third period, the central control module broadcasts a command keyword to the controlled register set, wherein the command keyword is used for indicating the type of the target command, and the type of the target command comprises one of a read type or a write type;
in a fourth period, the central control module broadcasts or reads corresponding data according to the type of the target command;
wherein the end time of the first period is earlier than or equal to the start time of the second period, the end time of the second period is earlier than or equal to the start time of the third period, and the end time of the third period is earlier than or equal to the start time of the fourth period.
3. The method of claim 2, wherein the central control module broadcasts or reads corresponding data according to the type of the target command during the fourth period of time, comprising:
in the fourth period, when the type of the target command is the write type, the central control module broadcasts first data to the controlled register set;
or alternatively, the first and second heat exchangers may be,
and in the fourth period, when the type of the target command is the reading type, the central control module reads second data from the register group corresponding to the target identification information.
4. A method according to any one of claims 1 to 3, wherein the register set and the central control module are data interacted with each other via a signal line for serial transmission of data.
5. A method for reading and writing registers, applied to a subsystem, the subsystem including at least two register sets, the method comprising:
the register group in the subsystem receives target identification information in a serial mode, wherein the target identification information is an identification of the register group broadcast by a central control module, the central control module is arranged between a central processor and the register group, and the central control module is used for controlling data interaction between the central processor and the register group;
The register group in the subsystem receives a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and in the serial data, the target identification information is positioned before the target command;
executing the target command by a first register group in the subsystem, wherein the identification of the first register group is matched with the target identification information;
and a second register group in the subsystem does not respond to the target command, and the identification of the second register group is not matched with the target identification information.
6. A method for reading and writing a register, which is applied to a register set, the method comprising:
receiving target identification information in a serial mode, wherein the target identification information is an identification of a register set broadcasted by a central control module, the central control module is arranged between a central processor and the register set, and the central control module is used for controlling data interaction between the central processor and the register set;
receiving a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data;
And executing the target command when the target identification information is matched with the identification of the register group.
7. A chip is characterized in that the chip comprises a central processing unit, a central control module and a subsystem, wherein the subsystem comprises at least two register groups, the central control module is arranged between the central processing unit and the subsystem and is used for controlling data interaction between the central processing unit and the subsystem,
the central control module is used for receiving the target identification information sent by the central processing unit and a target command corresponding to the target identification information in parallel;
the central control module is used for converting the target identification information and the target command into serial data, wherein the target identification information is positioned before the target command in the serial data;
the central control module is used for broadcasting the target identification information and the target command to the register group in the controlled subsystem in a serial mode;
and executing the target command by a first register group in the subsystem, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and the first register group is a register group corresponding to the target identification information in the at least two register groups.
8. A register subsystem, characterized in that the subsystem comprises at least two register sets,
the register group in the subsystem receives target identification information in a serial mode, wherein the target identification information is an identification of the register group broadcast by a central control module, the central control module is arranged between a central processor and the register group, and the central control module is used for controlling data interaction between the central processor and the register group;
the register group in the subsystem receives a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and in the serial data, the target identification information is positioned before the target command;
the first register group in the subsystem is used for executing the target command, and the identification of the first register group is matched with the target identification information;
and a second register group in the subsystem does not respond to the target command, and the identification of the second register group is not matched with the target identification information.
9. A register set, the register set being configured to:
Receiving target identification information in a serial mode, wherein the target identification information is an identification of a register set broadcasted by a central control module, the central control module is arranged between a central processor and the register set, and the central control module is used for controlling data interaction between the central processor and the register set;
receiving a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data;
and executing the target command when the target identification information is matched with the identification of the register group.
10. A terminal comprising the chip of claim 7.
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| CN112181493B (en) * | 2020-09-24 | 2022-09-13 | 成都海光集成电路设计有限公司 | Register network architecture and register access method |
| CN114625681A (en) * | 2020-12-09 | 2022-06-14 | Oppo广东移动通信有限公司 | Inter-chip communication method, multimedia chip and electronic equipment |
| CN115495408B (en) * | 2022-11-16 | 2023-09-01 | 无锡沐创集成电路设计有限公司 | Data processing method, chip module, sealing chip and electronic equipment |
| CN115994115B (en) * | 2023-03-22 | 2023-10-20 | 成都登临科技有限公司 | Chip control method, chip set and electronic equipment |
| CN116126401B (en) * | 2023-04-12 | 2023-07-25 | 此芯科技(上海)有限公司 | Register configuration circuit, method and electronic equipment |
| CN116991764B (en) * | 2023-08-03 | 2024-04-05 | 广州安凯微电子股份有限公司 | High-performance Flash controller and embedded system |
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