CN111651384A

CN111651384A - Register reading and writing method, chip, subsystem, register group and terminal

Info

Publication number: CN111651384A
Application number: CN202010508128.4A
Authority: CN
Inventors: 刘君
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-06-05
Filing date: 2020-06-05
Publication date: 2020-09-11
Anticipated expiration: 2040-06-05
Also published as: CN111651384B; WO2021244194A1

Abstract

The embodiment of the application discloses a register read-write method, a chip, a subsystem, a register group and a terminal, which belong to the technical field of register read-write, wherein a central control module receives target identification information and a corresponding target command sent by a central processing unit in parallel, the central control module converts the information into serial data, broadcasts the serial data to at least two register groups under control, the register group corresponding to the target identification information in the at least two register groups executes the target command, the data sent by the central processing unit in parallel is converted into serial data by adding the central control module, the register groups are connected to the central control module by signal wires when the register groups are increased, the register groups and the signal wires are correspondingly removed when the register groups are reduced, and the conventional method that all the register groups and a bus are redesigned is not needed, The CPU connection mode reduces the design difficulty of adding or reducing the register group in the chip design.

Description

Register reading and writing method, chip, subsystem, register group and terminal

Technical Field

The embodiment of the application relates to the technical field of register reading and writing, in particular to a register reading and writing method, a chip, a subsystem, a register group and a terminal.

Background

In the field of SoC (System on Chip) design, in order to implement each designated function, a plurality of subsystems are usually designed on one Chip, and each subsystem usually includes a plurality of register sets. The Central Processing Unit (CPU) accesses the various subsystems within via a bus (bus).

In the related art, when the central processing unit needs to access the subsystems, data are sent to the subsystems in a parallel mode, and the subsystems are decoded through the bus. When the bus finishes decoding, the register group can identify the decoded information, so that the information is read and written.

Disclosure of Invention

The embodiment of the application provides a register reading and writing method, a chip, a subsystem, a register group and a terminal. The technical scheme is as follows:

according to an aspect of the present application, there is provided a method for reading and writing a register, applied to a chip, where the chip includes a central processing unit, a central control module and a subsystem, the subsystem includes at least two register sets, the central control module is disposed between the central processing unit and the subsystem, and the central control module is configured to control data interaction between the central processing unit and the subsystem, and the method includes:

the central control module receives the target identification information and the corresponding target command sent by the central processing unit in parallel;

the central control module converts the target identification information and the corresponding target command into serial data, wherein the target identification information is positioned in front of the target command in the serial data;

the central control module broadcasts target identification information and a corresponding target command to a register group in the controlled subsystem in a serial mode;

and executing the target command by a first register group in the subsystem, wherein the target command is used for indicating the register group to write first data or indicating the register group to output saved second data, and the first register group is a register group corresponding to the target identification information in the at least two register groups.

According to another aspect of the present application, there is provided a register reading and writing method applied in a subsystem, where the subsystem includes at least two register sets, the method including:

a register group in the subsystem receives target identification information in a serial mode, wherein the target identification information is an identification of the register group broadcasted by a central control module, the central control module is arranged between a central processing unit and the register group, and the central control module is used for controlling data interaction between the central processing unit and the register;

a register group in the subsystem receives a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and in the serial data, the target identification information is positioned before the target command;

executing the target command by a first register group in the subsystem, wherein the identification of the first register group is matched with the target identification information;

a second register set in the subsystem does not respond to the target command, and the identification of the second register set does not match the target identification information.

According to another aspect of the present application, there is provided a method for reading and writing a register, which is applied to a register group, the method including:

receiving target identification information in a serial mode, wherein the target identification information is an identification of a register group broadcasted by a central control module, the central control module is arranged between a central processing unit and the register group, and the central control module is used for controlling data interaction between the central processing unit and the register group;

receiving a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data;

and when the target identification information is matched with the identification of the register group, executing the target command.

According to another aspect of the present application, there is provided a chip comprising a central processing unit, a central control module and a subsystem, the subsystem comprising at least two register sets, the central control module being disposed between the central processing unit and the subsystem, and the central control module being configured to control data interaction between the central processing unit and the subsystem,

the central control module is used for receiving the target identification information and the corresponding target command sent by the central processing unit in parallel;

the central control module is configured to convert the target identification information and the corresponding target command into serial data, where in the serial data, the target identification information is located before the target command;

the central control module is used for broadcasting target identification information and corresponding target commands to the at least two controlled register groups in a serial mode;

According to another aspect of the present application, there is provided a subsystem, the chip comprising at least two register sets:

a register group in the subsystem receives target identification information in a serial mode, wherein the target identification information is an identification of the register group broadcasted by a central control module, the central control module is arranged between a central processing unit and the register group, and the central control module is used for controlling data interaction between the central processing unit and the register group;

a first register set in the subsystem is used for executing the target command, and the identification of the first register set is matched with the target identification information;

According to another aspect of the present application, there is provided a register set for receiving target identification information in a serial manner, the target identification information being an identification of the register set broadcasted by a central control module, the central control module being disposed between a central processing unit and the register set, and the central control module being configured to control data interaction between the central processing unit and the register set;

According to another aspect of the present application, a terminal is provided, where the terminal includes the chip provided in the embodiment of the present application.

According to another aspect of the present application, an embodiment of the present application further provides a computer program product, where the computer program product stores at least one instruction, and the at least one instruction is loaded and executed by a processor to implement the register reading and writing method provided by the embodiment of the present application.

The application provides a method for reading and writing registers, which is applied to a chip, the chip comprises a central control module and register groups, the central control module receives target identification information and a corresponding target command sent by a central processing unit in parallel, the central control module converts the information into serial data, the target identification information is positioned in front of the target command in serial data, the central control module broadcasts the information to at least two register groups under control in a serial mode, the register groups corresponding to the target identification information in the at least two register groups execute the target command, the information interaction between the register groups and the central processing unit is completed under the condition of not using a bus system, the data sent by the central processing unit in the parallel mode is converted into the serial mode by additionally arranging the central control module, and then the register groups are connected to the central control module through signal lines when the register groups are added, when the register groups are reduced, the register groups and the signal lines are correspondingly removed, and the connection mode of all the register groups, the bus and the CPU is not required to be redesigned as before, so that the design difficulty of newly adding or reducing the register groups in the chip design is reduced.

Drawings

In order to more clearly describe the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to be able to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a block diagram of a terminal according to an exemplary embodiment of the present application;

FIG. 2 is a schematic diagram of a standard bus based register access architecture;

FIG. 3 is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application;

FIG. 5 is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application;

FIG. 6 is a flowchart of a method for reading and writing a register according to an exemplary embodiment of the present application;

FIG. 7 is a diagram illustrating a register set finite state machine according to an embodiment of the present disclosure;

FIG. 8 is a flowchart of a method for reading and writing a register according to an exemplary embodiment of the present application;

FIG. 9 is a diagram illustrating a finite state machine of a central control module according to an embodiment of the present disclosure;

FIG. 10 is a flowchart of a method for reading and writing a register according to another exemplary embodiment of the present application;

FIG. 11 is a flowchart of a method for reading and writing a register according to another exemplary embodiment of the present application;

FIG. 12 is a schematic diagram of a serial signal write timing based on one of the register banks shown in FIG. 4;

fig. 13 is a schematic diagram based on a timing of serially reading data from a register group shown in fig. 4.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

In the description of the present application, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g. as being able to be fixedly connected, also being able to be detachably connected, or being integrally connected; can be a mechanical connection, but also an electrical connection; can be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present application can be specifically understood by those of ordinary skill in the art. Further, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there can be three relationships, e.g., a and/or B, meaning that: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

In order to make the solution shown in the embodiments of the present application easy to understand, several terms appearing in the embodiments of the present application will be described below.

The serial mode: in one signal line, data is transmitted from the central control module to the register group in a queue manner. For example, data "010101" will be transmitted from the central control module into the register group one by one in the signal line.

Target identification information: this information is an identification of the register set broadcast by the central control module. In one possible implementation, the target identification information includes a target keyword and identification data. For example, if the target information is "111 + 010", it indicates that the target keyword is "111", and the identification data is "010". In this application, different numeric target keywords are used to represent different keywords. When the target key is the value "111", it indicates that the target key is the target key, and the register identification is "010".

Target command: the method comprises two functions of reading data and writing data, and when a target command is used for reading data from the register group, the command is used for instructing the register group to output the saved second data. When the target command is used to write data into the register group, the command is used to instruct the register group to write the first data.

Optionally, the target command includes a command key. Optionally, the command key includes a write key and a read key. When the command key is a write key, the type of the target command is a write type. When the command key is a read key, the type of the target command is a read type.

Optionally, when the type of the target command is a write type, the target command includes a write key and the first data. The register group can determine data, namely first data, which needs to be stored in the register group according to the write keyword, and then store the first data in the register group.

Alternatively, when the type of the target command is a read type, the target command includes a read key and second data. The register group can know that the register group needs to output the second data outwards according to the read key words, and then the register group outputs the second data outwards.

For example, the method for reading and writing the register shown in the embodiment of the present application can be applied to a terminal, where the terminal includes the chip shown in the embodiment of the present application, and the chip shown in the embodiment of the present application includes a register group. Alternatively, the terminal includes a mobile phone, a tablet computer, a laptop computer, a desktop computer, a personal computer, a server, a workstation, a television, a set-top box, smart glasses, a smart watch, a digital camera, an MP4 player terminal, an MP5 player terminal, a learning machine, a point-and-read machine, an electronic book, an electronic dictionary, a vehicle-mounted terminal, a Virtual Reality (VR) player terminal, an Augmented Reality (AR) player terminal, or the like.

On the other hand, the embodiment of the present application can also be applied to a chip, and the chip can be applied to the terminal.

Referring to fig. 1, fig. 1 is a block diagram of a terminal according to an exemplary embodiment of the present application, and as shown in fig. 1, the terminal 10 includes a chip 100, where the chip 100 includes a processor 120, a memory 140, a subsystem 160, and a central control module 180, where the memory 140 stores at least one instruction, and the instruction is loaded and executed by the processor 120 to implement a register reading and writing method according to various method embodiments of the present application. Optionally, the processor 120 is a central processor. The chip 100 includes a central processing unit, a central control module 180 and a subsystem 160, wherein the central control module 180 is disposed between the central processing unit and the subsystem 160, and the central control module 180 is used for controlling data interaction between the central processing unit and the subsystem 160.

Processor 120 can include one or more processing cores. The processor 120 connects various parts within the overall terminal 100 using various interfaces and lines, and performs various functions of the terminal 100 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 140 and calling data stored in the memory 140. Optionally, the processor 120 can be implemented in at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 120 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It is understood that the modem can be implemented by a single chip without being integrated into the processor 120.

The Memory 140 can include a Random Access Memory (RAM) and can also include a Read-Only Memory (ROM). Optionally, the memory 140 includes a non-transitory computer-readable medium. The memory 140 may be used to store instructions, programs, code sets, or instruction sets. The memory 140 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like; the storage data area may store data and the like referred to in the following respective method embodiments.

The subsystem 160 can be external to the processor. Optionally, a central control module 180 is disposed between the processor and the subsystems for controlling data interaction of the central control module 180 with the respective subsystems, writing data in the subsystems or reading data from the subsystems. Illustratively, the subsystem 160 may be implemented as a set of physical circuits. Subsystem 160 includes at least two register sets therein. For example, subsystem 160 includes register set 161 and register set 162.

In the present application, the chip 100 performs the following steps: the central control module receives the target identification information and the corresponding target command sent by the central processing unit in parallel; the central control module converts the target identification information and the corresponding target command into serial data, wherein the target identification information is positioned in front of the target command in the serial data; the central control module broadcasts target identification information and corresponding target commands to at least two controlled register groups in a serial mode; the first register group executes a target command, the target command is used for instructing the register group to write first data, or is used for instructing the register group to output stored second data, and the first register group is a register group corresponding to target identification information in at least two register groups.

In the present application, the subsystem 160 performs the following steps: a register group in the subsystem receives target identification information in a serial mode, wherein the target identification information is the identification of the register group broadcasted by the central control module; a register group in the subsystem receives a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and in the serial data, the target identification information is positioned before the target command; the first register group is used for executing the target command, and the identification of the first register group is matched with the target identification information; the second register set does not respond to the target command, and the identification of the second register set does not match the target identification information.

In the present application, the register set 161 or the register set 162 performs the following steps: receiving target identification information in a serial mode, wherein the target identification information is an identification of a register group broadcasted by a central control module, the central control module is arranged between a central processing unit and the register group, and the central control module is used for controlling data interaction between the central processing unit and the register; receiving a target command in a serial mode, wherein the target command is used for indicating the register group to write first data or indicating the register group to output stored second data; and when the target identification information is matched with the identification of the register group, executing the target command.

Referring to fig. 2, fig. 2 is a diagram of a register access architecture based on a standard bus. In fig. 2, a central processor 210 interacts with various subsystems via a top-level bus 220. In fig. 2, 3 subsystems including subsystem 1, subsystem 2 and subsystem are included. Taking the subsystem 1 as an example, a process of data interaction between a register set and a central processing unit in the subsystem 1 is introduced.

When the central processing unit 210 needs to write data into the register set _2 in the subsystem 1, the central processing unit 210 adds the address of the register set _2 in the subsystem 1 to the header of the data needing to be written, and sends the data to the top-level bus 220, and the top-level bus 220 transfers the data to the subsystem bus 231, the subsystem bus 241 and the subsystem bus 251 respectively. Each subsystem bus is matched with the standard bus to decode the data. When the address of the register set _2 obtained by decoding is the same as the address of the register set corresponding to the standard bus, the standard bus 2A writes data into the register set _ 2. Illustratively, the number of wires of a standard bus is on the order of 10¹The standard bus is complex. When a new subsystem or a new register set needs to be added to the chip, the workload of debugging the corresponding subsystem bus and the standard bus is increased, so that the difficulty of modular development of the chip is improved. Alternatively, the standardized Bus may be an AHB (Advanced High performance Bus), an APB (Advanced Peripheral Bus), or another cable capable of implementing a Bus function.

In view of the limitations of the above register read/write architecture, the present application proposes a new architecture for reading/writing registers, also called a control protocol for reading/writing registers, which is introduced as follows.

Referring to fig. 3, fig. 3 is a diagram illustrating a register access architecture according to an exemplary embodiment of the present application. In fig. 3, central processor 210 communicates with central control module (center control)310 via bus 3A, and central control module 310 communicates with subsystem 1, subsystem 2, and subsystem k via signal line 320. The signal line 320 is a 1-bit (bit) cable. Note that the arrow in fig. 3 indicates the data flow direction. In fig. 3, the central control module is disposed between the central processor and the register set, and the central control module is used for controlling data interaction between the central processor and the register.

In another possible approach, the signal line 320 is a 2-bit (bit) cable. Referring to fig. 4, fig. 4 is a diagram illustrating a register access architecture according to an exemplary embodiment of the present application. Among them, the 2-bit signal line (line) includes a Command (CMD) line 410 and a Data (DAT) line 420. Alternatively, in FIG. 4, the command line 410 is bit [0], the data line 420 is bit [1], and the architecture shown in FIG. 4 is a read-write architecture for a register bank under a 2-bit serial control protocol. Note that the arrow in fig. 4 indicates the data flow direction. The direction of the data transmission from the command line 410 is unidirectional from the central control module to the register set. The direction in which data is transmitted by the data lines 420 is bi-directional between the central control module and the register sets.

In another possible approach, the signal line 320 is a 3-bit (bit) cable. Referring to fig. 5, fig. 5 is a diagram illustrating a register access architecture according to an exemplary embodiment of the present application. Among them, the 3-bit signal line (line) includes a Command (CMD) line 510, a write data line 520, and an output data line 530. Note that the arrow in fig. 5 indicates the data flow direction. The direction of the data transmission from the command line 510 is unidirectional from the central control module to the register set. The write data line 520 transfers data in a single direction from the central control module to the register set. The direction in which the output data line 530 transmits data is unidirectional from the register set to the central control module.

Alternatively, in the register groups shown in fig. 3 to 5, the respective register groups share the same reset and clock. That is, when the register set needs to be reset, all the register sets in any one of fig. 3 to 5 are reset. Meanwhile, all register sets in any one of fig. 3 to 5 share the same clock.

Optionally, data interaction is performed between the register set and the central control module through a signal line, and the signal line is used for serial data transmission.

Referring to fig. 6, fig. 6 is a flowchart of a method for reading and writing a register according to an exemplary embodiment of the present application. The read-write method of the register can be applied to the chip shown in any one of fig. 1, 3 to 5. In fig. 6, the method for reading and writing the register includes:

step 610, receiving the target identification information in a serial manner, where the target identification information is the identification of the register group broadcasted by the central control module.

In the embodiment of the present application, the register group can receive the target identification information in a serial manner. The register group can obtain the target identification information broadcasted by the central control module through any one of the architectures in fig. 3 to 5.

In the embodiment of the application, the central control module is disposed between the central processing unit and the register set, and the central control module is used for controlling data interaction between the central processing unit and the registers.

Alternatively, taking the architecture shown in FIG. 4 as an example, the register set will obtain the target key via command line 410 and the identification data via data line 420. In which, taking the register group as a slave (slave) as an example, a control protocol at the register group side is introduced.

It should be noted that, in the embodiment of the present application, the register group is designed as an assembly including N registers, and each register includes M bits of storage space. In the present application, the register group can read all the N × M bits of data, or write data to be written into the N × M bit space. It should be noted that values of N and M are positive integers, and both N and M are instantiation parameters (instantiation parameters), and specific values of N and M are not limited in the present application.

In table one, the data direction represents the direction of data flow with the register set as the reference point. For example, writing means writing data from the central control module to the register set, and reading means reading data from the register set to the outside. In the embodiment of the present application, when data "111" appears in the command line, it indicates that the register identification is to be transferred in the data line. At this time, the register set reads a k-bit long register set identifier from the data line. It should be noted that k is also an instantiation parameter.

Alternatively, when data "101" appears in the command line, it indicates that data written in N × M bits will be transferred in the data line.

Step 620, receiving a target command in a serial manner, where the target command is used to instruct the register set to write the first data, or to instruct the register set to output the saved second data.

In the embodiment of the present application, the register set receives the target command in a serial manner. Optionally, the register set includes a decoding module. The decoding module can receive the target identification information in a serial manner and receive the target command when the target identification information matches the identification of the register set.

In step 630, the target command is executed when the target identification information matches the identification of the register set.

In this embodiment of the application, optionally, the register group can write data sent by the central control module into a storage space of the entire register group when the target identification information matches an identification of the register group and the type of the target command is a write type. Alternatively, the register group can output all data existing in the register group to the central control module when the target identification information matches the identification of the register group and the type of the target command is a read type.

Optionally, the register set includes a finite state machine in the register reading and writing method provided in the present application, which is described as follows.

Referring to fig. 7, fig. 7 is a schematic diagram of a register set finite state machine according to an embodiment of the present disclosure. In FIG. 7, the register set is in an idle state 710, capable of receiving k bits long data from the data line after receiving data "111" from the command line (i.e., step 720). When the k-bit data of the register set does not match the identifier of the register set (i.e. ID _ match ═ 0'), the register set continues to transition to the idle state. When the k-bit data of the register set matches the identifier of the register set (i.e., ID _ match ═ 1'), the receive target command is executed (i.e., step 730). Subsequently, when the data "101" is received from the command line, the write data state is entered (i.e., step 740), the N × M bits of data are written into the register group, and then the idle state is entered. On the other hand, when data "110" is received from the command line, the read data state is entered, and the N × M bits of data in the register set are fetched (i.e., step 750), and then the idle state is entered.

In summary, in the method for reading and writing a register provided in this embodiment, the register set receives the target identification information in a serial manner, where the target identification information is an identification of the register set broadcasted by the central control module, and receives the target command in the serial manner, where the target command is used to instruct the register set to write the first data in, or to instruct the register set to output the stored second data, and when the target identification information matches the identification of the register set, the target command is executed. The method can enable the register group to receive the identification broadcasted by the central control module in a serial mode, receive the read-write command in the serial mode and execute the read-write command when the identification is matched, convert the data sent by the CPU in the parallel mode into the serial mode, and subsequently connect the register group to the central control module through the signal wire when the register group is added.

Optionally, since the present application provides a signal line as a connection for connecting the central control module and the register set, in the related art, the embodiment of the present application can also effectively reduce the problem that in the related art, the bit width of the bus is too high due to data transmission through the bus, which brings a spatial pressure to the wiring work of the register set and increases the complexity of the flat cable design, and effectively reduce the routing difficulty from the central control module to the register set.

Referring to fig. 8, fig. 8 is a flowchart of a method for reading and writing a register according to an exemplary embodiment of the present application. The read-write method of the register can be applied to the chip shown in any one of the above fig. 1, fig. 3 to fig. 5, and the chip includes a central control module and a register group. In fig. 8, the method for reading and writing the register includes:

step 810, the central control module receives the target identification information and the corresponding target command sent by the central processing unit in parallel.

In the embodiment of the present application, the data sent by the central processing unit is received by the central control module in a parallel manner. Correspondingly, when the central processing unit needs to write data into the register group or read data from the register group, the central processing unit sends target identification information and a target command corresponding to the target identification information to the central control module in parallel.

In step 820, the central control module converts the target identification information and the corresponding target command into serial data, wherein the target identification information is located before the target command in the serial data.

In the embodiment of the application, the central control module has a data conversion function and can convert data received in parallel into serial data. In the serial data after the conversion of the central control module, the target identification information is positioned before the target command.

In step 830, the central control module broadcasts the target identification information and the corresponding target command to the register set in the controlled subsystem in a serial manner.

Illustratively, if the central control module controls m register groups, the central control module can broadcast the target identification information and the corresponding target command to the m register groups in a serial manner. It should be noted that m register sets may belong to a plurality of subsystems respectively. Wherein a subsystem comprises at least two register sets.

In step 840, a first register set in the subsystem executes a target command, where the target command is used to instruct the register set to write first data, or to instruct the register set to output stored second data, and the first register set is a register set corresponding to target identification information in at least two register sets.

Referring to fig. 9, fig. 9 is a schematic diagram of a finite state machine of a central control module according to an embodiment of the present disclosure. In FIG. 9, the central control module begins in the idle state 910 by broadcasting a target key to the set of registers being controlled, i.e., transferring data "111" from the command line (i.e., performing step 920); subsequently, data of k bits length is transmitted from the data line (i.e., step 930 is performed); the target command is then broadcast to the controlled register set (i.e., step 940 is performed). When the data sent from the command line is "101", the central control module writes N × M bits of data from the data line into the register set (i.e., step 950 is performed). When the data sent from the command line is "110", the central control module reads the N × M bits of data obtained from the register set from the data line (i.e., step 960 is performed). When step 950 or step 960 is completed, the central control module returns to an idle state.

To sum up, the method for reading and writing a register provided by the present application is applied to a chip, the chip comprises a central control module and a register set, the central control module receives target identification information and a corresponding target command sent by a central processing unit in parallel, the central control module converts the information into serial data, in serial data, the target identification information is located before the target command, the central control module broadcasts the information to at least two register sets under control in a serial mode, the register set corresponding to the target identification information in the at least two register sets executes the target command, thereby realizing information interaction between the register sets and the central processing unit under the condition of not using a bus system, converting data sent by the central processing unit in a parallel mode into a serial mode by additionally arranging the central control module, and subsequently connecting the register sets to the central control module through signal lines when the register sets are added, when the register groups are reduced, the register groups and the signal lines are correspondingly removed, and the connection mode of all the register groups, the bus and the CPU is not required to be redesigned as before, so that the design difficulty of newly adding or reducing the register groups in the chip design is reduced.

Optionally, since the embodiment of the present application can also identify the register group by the identifier of the register group, rather than identifying the register group by address decoding in the related art, the identifier of the register group is smaller than the data size of the address. Therefore, the embodiment of the application reduces the difficulty of the central processing unit for finding the corresponding register group, thereby improving the efficiency of reading and writing data from the corresponding register group.

Optionally, in the embodiment of the present application, a simple signal line is designed between the register set and the central control module, so that the logic complexity of the decoding operation of the register set is reduced, and the design difficulty of adding a new register set to the chip is greatly reduced.

Optionally, in the embodiment of the present application, the central control module performs uniform read-write management on the data of the controlled register group, and performs conversion between parallel and serial of the data, so that it is easier for the central processing unit to read and write the data of the register group in the system.

Optionally, in the scheme provided by the embodiment of the present application, a data read-write standard with simple logic is designed between the central control module and the register set. Therefore, the embodiment of the application is also beneficial to making a chip with static control or a chip with a complicated bus interface and high cost, or a chip which needs a unified central control module to control all register groups to realize special functions to realize high data read-write efficiency, and reducing the difficulty of chip development when increasing or decreasing the register groups.

The embodiment of the application can also provide a reading and writing method applied to the register in the subsystem. Referring to fig. 10, fig. 10 is a flowchart of a method for reading and writing a register according to another exemplary embodiment of the present application. In fig. 10, the method for reading and writing the register includes:

in step 1001, a register set in the subsystem receives target identification information in a serial manner.

The target identification information is an identification of a register group broadcasted by the central control module, the central control module is arranged between the central processing unit and the register group, and the central control module is used for controlling data interaction between the central processing unit and the register.

Illustratively, each register set in the subsystem receives the target identification information in a serial manner. For example, if the subsystem and the central control module are connected in the manner shown in fig. 3, and the subsystem 2 is taken as an example. The register group _1, the register group _2 and the register group _3 in the subsystem 2 can receive the target identification information through signal lines.

In step 1002, a register set in a subsystem receives a target command in a serial manner.

The target command is used for indicating the register group to write first data or indicating the register group to output stored second data, and in serial data, target identification information is positioned before the target command.

Illustratively, the register set will receive the target command after receiving the target identification information. The register set in the subsystem receives serial data in which the target identification information precedes the target command.

In step 1003, a first register set in the subsystem executes the target command, and the identifier of the first register set is matched with the target identifier information.

In step 1004, the second register set in the subsystem does not respond to the target command, and the identifier of the second register set does not match the target identification information.

Optionally, after the register set receives the target identification information and the target command, the register set compares whether the own identification and the target identification information match. In the subsystem, the register group whose own identification matches the target identification information is the first register group. The register group whose own identification and target identification information do not match is the second register group.

Furthermore, the first and second register sets in the subsystem will react differently to the target command. The first register group in the subsystem executes the target command, and the second register group does not respond to the target command.

To sum up, the register read-write method executed by the subsystem disclosed in the embodiment of the present application can connect the register group to the central control module through the signal line when the register group is added to the subsystem, and can correspondingly remove the register group and the signal line when the register group is reduced, without redesigning the connection mode of all the register groups, the bus and the CPU as in the prior art, thereby reducing the design difficulty of adding or reducing the register group to the subsystem in the chip design, and improving the difficulty of adding or reducing the subsystem in the whole.

The embodiment of the application can also provide a register reading and writing method in which the register group and the central control module participate simultaneously, which is introduced as follows.

Referring to fig. 11, fig. 11 is a flowchart of a method for reading and writing a register according to another exemplary embodiment of the present application. The read-write method of the register can be applied to the chip shown in any one of the above fig. 1, fig. 3 to fig. 5. In fig. 11, the method for reading and writing the register includes:

in step 1011, the central control module broadcasts the target keyword to the controlled register set in the first time period.

The target keyword is used to indicate that the data transmitted in the second time interval represents the identifier of the specified register group, that is, the target keyword can determine that the content of the data transmitted in the second time interval is the identifier corresponding to a certain register group.

Accordingly, the register set instructs the decoding module to receive the target key during the first period, and the target key is used for indicating the meaning represented by the data received during the second period. For example, in one possible approach, the target key is "001" to indicate that the data received during the second period represents identification data, i.e., the data received during the second period represents the ID of the register set.

In step 1012, the central control module broadcasts identification data to the controlled register sets during a second time period.

Wherein the target keyword and the identification data belong to target identification information.

Accordingly, the register group receives the identification data in the second period, and the target keyword and the identification data belong to the target identification information. Illustratively, the end time of the first period is earlier than or equal to the start time of the second period.

Step 1013, the central control module broadcasts the command keyword to the controlled register set in the third time period.

The command key is used for indicating the type of the target command, and the type of the target command comprises one of a read type or a write type.

Correspondingly, the register group instructs the decoding module to receive a command key when the identification data matches the identification of the register group in the third period, wherein the command key is used for indicating the type of the target command, and the type of the target command comprises one of a read type or a write type.

In one possible embodiment, when the identification data does not match the identification of the register set, the decode module will not receive a subsequent command key. Or the decoding module does not decode and identify the subsequently received operation key any more.

And 1014, broadcasting or reading corresponding data by the central control module according to the type of the target command in the fourth time period.

Correspondingly, the register group transmits data to the central control module or receives and reads the data sent by the central control module according to the type of the target command in the fourth time period.

Illustratively, the end time of the first period is earlier than or equal to the start time of the second period, the end time of the second period is earlier than or equal to the start time of the third period, and the end time of the third period is earlier than or equal to the start time of the fourth period.

In the embodiment of the present application, the central control module may further implement a data writing or reading function by executing step (1) or step (2).

And (1) in a fourth period, when the type of the target command is a writing type, the central control module broadcasts first data to the controlled register group.

Accordingly, in the fourth period, when the type of the target command is the write type, the register group holds the first data.

And (2) in a fourth period, when the type of the target command is a reading type, the central control module reads second data from the register group corresponding to the target identification information.

Accordingly, in the fourth period, when the type of the target command is the read type, the second data is output to the central control module.

In one possible implementation, the architecture shown in fig. 4 is taken as an example. The central control module and the register group are interacted through a command line and a data line. Referring to fig. 12, fig. 12 is a schematic diagram of a serial signal writing timing based on the register set shown in fig. 4. The command line 410 serially transfers the target keyword "111" during the first period 11A. The data line 420 serially transmits identification data "10100001" in the second period 11B. The command line 410 serially transfers a write key "101" indicating writing of data into the register group in the third period 11C. The data line 420 serially transfers 128 bits of data in the fourth period 11D.

In another possible implementation, the architecture shown in fig. 4 is taken as an example. The central control module and the register group are interacted through a command line and a data line. Referring to fig. 13, fig. 13 is a schematic diagram of a timing sequence for serially reading data from a register set based on the timing sequence shown in fig. 4. The command line 410 serially transfers the target keyword "111" during the first period 11E. The data line 420 serially transmits identification data "10100001" in the second period 11F. The command line 410 serially transfers a read key "110" indicating serial reading of 128 bits of data from the register bank in the third period 11G. The data line 420 serially transfers 128 bits of data in the fourth period 11H.

In summary, the present embodiment can be applied to a chip, where the chip includes a central control module and register groups, the central control module receives target identification information and a corresponding target command sent by a central processing unit in parallel, the central control module converts the information into serial data, in serial data, the target identification information is located before the target command, the central control module broadcasts the information to at least two register groups under control in a serial manner, the register groups corresponding to the target identification information in the at least two register groups execute the target command, so as to implement information interaction between the register groups and the central processing unit without using a bus system, by adding the central control module, the data sent by the central processing unit in a parallel manner is converted into a serial manner, and then when adding a register group, the register group is connected to the central control module through a signal line, when the register groups are reduced, the register groups and the signal wires are correspondingly removed, the connection mode of all the register groups, the bus and the CPU is not required to be redesigned as before, and the design difficulty of newly adding or reducing the register groups in the chip design is reduced

The embodiment of the present application further provides a computer-readable medium, where at least one instruction is stored, and the at least one instruction is loaded and executed by the processor to implement the method for reading and writing the register according to the above embodiments.

The embodiment of the present application further provides a computer program product, where the computer program product stores at least one instruction, and the at least one instruction is loaded and executed by a processor to implement the method for reading and writing the register according to the embodiment of the present application.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments can be implemented by hardware, and can also be implemented by a program for instructing relevant hardware, wherein the program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

The above description is only exemplary of the implementation of the present application and is not intended to limit the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A read-write method of a register is characterized in that the read-write method is applied to a chip, the chip comprises a central processing unit, a central control module and a subsystem, the subsystem comprises at least two register groups, the central control module is arranged between the central processing unit and the subsystem, and is used for controlling data interaction between the central processing unit and the subsystem, and the method comprises the following steps:

2. The method of claim 1, wherein the central control module broadcasts target identification information and corresponding target commands to register sets in the subsystems under control in a serial manner, comprising:

in a first period, the central control module broadcasts a target keyword to the controlled register group, wherein the target keyword is used for indicating that data sent in a second period represents the identifier of the specified register group;

in the second time period, the central control module broadcasts identification data to the controlled register group, wherein the target keywords and the identification data belong to the target identification information;

in a third time period, the central control module broadcasts a command key to the controlled register group, wherein the command key is used for indicating the type of the target command, and the type of the target command comprises one of a read type or a write type;

in a fourth period, the central control module broadcasts or reads corresponding data according to the type of the target command;

wherein the ending time of the first time period is earlier than or equal to the starting time of the second time period, the ending time of the second time period is earlier than or equal to the starting time of the third time period, and the ending time of the third time period is earlier than or equal to the starting time of the fourth time period.

3. The method according to claim 2, wherein during the fourth period, the central control module broadcasts or reads corresponding data according to the type of the target command, including:

in the fourth period, when the type of the target command is the write type, the central control module broadcasts first data to the controlled register group;

or the like, or, alternatively,

in the fourth period, when the type of the target command is the read type, the central control module reads second data from a register group corresponding to the target identification information.

4. The method according to any one of claims 1 to 3, wherein data interaction is performed between the register set and the central control module through a signal line, and the signal line is used for serial data transmission.

5. A method for reading and writing registers is applied to a subsystem, wherein the subsystem comprises at least two register groups, and the method comprises the following steps:

6. A method for reading and writing a register is applied to a register group, and the method comprises the following steps:

7. A chip is characterized in that the chip comprises a central processing unit, a central control module and a subsystem, the subsystem comprises at least two register sets, the central control module is arranged between the central processing unit and the subsystem and is used for controlling data interaction between the central processing unit and the subsystem,

the central control module is used for broadcasting target identification information and corresponding target commands to the register group in the controlled subsystem in a serial mode;

8. A sub-system, characterized in that the sub-system comprises at least two register sets,

9. A register file, the register file being configured to:

10. A terminal characterized in that it comprises a chip according to claim 7.