CN116820867A

CN116820867A - Chip debugging method and device and chip

Info

Publication number: CN116820867A
Application number: CN202311095698.5A
Authority: CN
Inventors: 陈德炜; 黄彬; 李泽祥
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2023-08-29
Filing date: 2023-08-29
Publication date: 2023-09-29
Anticipated expiration: 2043-08-29
Also published as: CN116820867B

Abstract

The embodiment of the application provides a chip debugging method, a chip debugging device and a chip; the method comprises the following steps: the control system controller broadcasts a first data signal to at least one subsystem through a four-wire serial interface; the subsystem to be debugged is controlled to report a second data signal to the system controller through a four-wire serial interface according to the indication of the first data signal; the control system controller debugs the subsystem to be debugged based on the second data signal. The embodiment of the application can improve the chip debugging performance.

Description

Chip debugging method and device and chip

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a chip debugging method, a chip debugging device, and a chip.

Background

Chip debugging refers to the process of detecting whether the chip function can normally run.

Currently, chip debug techniques can be broadly divided into external debug and internal debug. The external debugging depends on an external modulator, such as JTAG technology and SWD technology, which are required to be provided with exclusive I/O interfaces in a chip, and an interconnection structure is required to be designed in the chip, so that the chip can be debugged only by the exclusive debugging software and simulator equipment outside the chip in the debugging process; the debugging technology has the defects of dependence on a system debugging clock, low specific debugging speed, inconvenient use, high cost and the like. Internal debugging relies on the bus of the chip to access each subsystem in the chip for detection or debugging, and when the bus of the chip works abnormally, the chip cannot be debugged.

Therefore, how to realize debugging for the chip function has a crucial effect on the normal use of the chip.

Disclosure of Invention

The embodiment of the application provides a chip debugging method and device and a chip, which can improve the chip debugging performance.

In one aspect, an embodiment of the present application provides a method for debugging a chip, where the chip includes a system controller and at least one subsystem, and the system controller communicates with any subsystem based on a four-wire serial interface; the method comprises the following steps:

the control system controller broadcasts a first data signal to at least one subsystem through a four-wire serial interface; the first data signal is used for indicating a subsystem to be debugged in at least one subsystem;

the subsystem to be debugged is controlled to report a second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, and the second data signal carries the state data of the subsystem to be debugged;

the control system controller debugs the subsystem to be debugged based on the second data signal.

On the other hand, the embodiment of the application provides a chip debugging device, which comprises a system controller and at least one subsystem, wherein the system controller is communicated with any subsystem based on a four-wire serial interface; the device comprises:

A transmitting unit for controlling the system controller to broadcast a first data signal to at least one subsystem through a four-wire serial interface; the first data signal is used for indicating a subsystem to be debugged in at least one subsystem;

the sending unit is also used for controlling the subsystem to be debugged to report a second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, wherein the second data signal carries the state data of the subsystem to be debugged;

and the processing unit is used for controlling the system controller to debug the subsystem to be debugged based on the second data signal.

In one implementation, a four-wire serial interface includes: an enable signal line, a clock signal line, an output data line, and an input data line; the signal flow direction of the data signals on the enable signal line, the clock signal line and the output data line is: broadcast from the system controller to each of the at least one subsystem; the signal flow direction of the data signal on the input data line is: transmitting from the subsystem to the system controller;

an enable signal line for controlling on and off of a debug mode for the chip; when the level state of the enabling signal line is high level, the debug mode is started; when the level state of the enable signal line is a low level, the debug mode is turned off;

The clock signal line is used for controlling data receiving and transmitting synchronization between the system controller and the subsystem; when the level state of the clock signal line is high level, the system controller and the subsystem sample the data signal;

an output data line for controlling data signal transmission from the system controller to the subsystem direction;

and the input data line is used for controlling the data signal transmission from the subsystem to the system controller.

In one implementation, the sending unit is further configured to:

the control system controller broadcasts an enable signal to at least one subsystem through an enable signal line; the method comprises the steps of,

the control system controller broadcasts continuous clock pulses to at least one subsystem through a clock signal line;

wherein the rising edge of the high level of the enable signal is aligned with the rising edge of the first clock pulse of the succession of clock pulses.

In one implementation, a first data signal carries a data frame including a control field segment, a buffer field segment, and a data field segment; the sending unit is used for controlling the system controller to broadcast the first data signal to at least one subsystem through the four-wire serial interface, and is specifically used for:

the control system controller broadcasts the control field segment, the buffer field segment, and the data field segment to at least one subsystem in sequence, starting from a rising edge of the clock pulse, via the output data line.

In one implementation manner, the sending unit is configured to control the subsystem to be debugged to report the second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, where the sending unit is specifically configured to:

after the control to-be-debugged subsystem finishes aiming at the control domain segment sampling, the control to-be-debugged subsystem acquires state data of the to-be-debugged subsystem from a register set at the side of the to-be-debugged subsystem;

the subsystem to be debugged is controlled to package the state data of the subsystem to be debugged into a second data signal;

and controlling the subsystem to be debugged to report a second data signal carrying the state data of the subsystem to be debugged to the system controller through the input data line.

In one implementation, the control domain segment at least includes a device identification domain segment, where the device identification domain segment includes a device identification of the subsystem to be debugged;

the processing unit is further used for:

starting from the rising edge of the clock pulse, controlling each subsystem in at least one subsystem to sample a control domain segment carried by the first data signal through the output data line;

controlling each subsystem to read the equipment identification domain segment included in the control domain segment;

and determining a subsystem to be debugged, of which the equipment identifier is the same as the equipment identifier included in the equipment identifier field section, from at least one subsystem based on the equipment identifier included in the equipment identifier field section, and triggering and executing the step of controlling the subsystem to be debugged to acquire the state data of the subsystem to be debugged from a register group at the side of the subsystem to be debugged.

In one implementation, the register set on the side of the subsystem to be debugged includes a plurality of registers, where the registers are at least used to cache state data of the subsystem to be debugged; the control domain section at least comprises a register domain section and an operation domain section;

the processing unit is used for controlling the subsystem to be debugged to acquire the state data of the subsystem to be debugged from the register group at the side of the subsystem to be debugged, and is specifically used for:

the subsystem to be debugged is controlled to analyze the register field segment to obtain a register address; the register address refers to the address of a register which is to be accessed by a system controller in a register group at the side of a subsystem to be debugged; the method comprises the steps of,

the subsystem to be debugged is controlled to analyze the operation domain segment to obtain an operation code;

and if the operation code indicates that the operation type is a read operation, controlling the subsystem to be debugged to read the state data of the subsystem to be debugged from the register indicated by the register address based on the operation code.

In one implementation, the enable signal line, the clock signal line, and the output data line are inserted with the same number of stages of register delays; the number of stages of register delay inserted in the input data line corresponding to different subsystems in at least one subsystem is the same or different;

The first data signal carries a data frame, the data frame including a buffer field segment for adjusting a timing sequence between the system controller and each of the at least one subsystem;

the transmission time length Nsck of the buffer domain segment on the output data line is greater than or equal to the sum of the first register delay Nfp and the second register delay Nbp; wherein the first register delay Nfp is determined based on the number of stages of register delays inserted in the direction of the system controller to the at least one subsystem; the second register delay Nbp is determined based on the number of stages of register delays inserted in the direction of the subsystem to be debugged to the system controller.

In one implementation, the first data signal carries a data frame including a buffer field segment for adjusting timing between the system controller and each of the at least one subsystem; the processing unit is used for controlling the system controller to debug the subsystem to be debugged based on the second data signal, and is specifically used for:

starting from the rising edge of the first clock pulse after the buffer domain segment is broadcasted, the control system controller samples a second data signal reported by the subsystem to be debugged through an input data line;

The control system controller analyzes the second data signal to obtain state data of the subsystem to be debugged;

and debugging the subsystem to be debugged based on the state data of the subsystem to be debugged.

In one implementation, the chip is connected to the computer device using a universal serial port; the processing unit is used for debugging the subsystem to be debugged based on the state data of the subsystem to be debugged, and is specifically used for:

and sending the state data of the subsystem to be debugged to the computer equipment through the universal serial port, so that the computer equipment adopts a debugging program to debug the subsystem to be debugged based on the state data of the subsystem to be debugged.

In one implementation, the chip is an SOC chip that follows a target bus protocol; the protocol conversion process of the SOC chip comprises the following steps:

a sender of the data signal generates a target data signal based on a target bus protocol;

performing protocol conversion on the target data signal to obtain an intermediate data signal conforming to a data frame protocol corresponding to the four-wire serial interface;

after a receiving party of the data signal receives an intermediate data signal conforming to a data frame protocol, carrying out protocol conversion on the intermediate data signal to obtain a target data signal conforming to a target bus protocol;

When the sender of the data signal is a system controller, the receiver of the data signal is a subsystem to be debugged, and the intermediate data signal is a first data signal; when the sender of the data signal is the subsystem to be debugged, the receiver of the data signal is a system controller, and the intermediate data signal is a second data signal.

In one implementation, the first data signal carries a data frame comprising, in order: a control field section, a buffer field section and a data field section; the control domain section comprises a device identification domain section, a register domain section and an operation domain section; wherein,

the equipment identification field section comprises equipment identifications of the subsystems to be debugged;

the register field section comprises the address of a target register in a register group at the side of the subsystem to be debugged, wherein the target register is a register which is needed to be accessed by a system controller in the register group;

the operation domain section comprises an operation code, and the operation code is used for indicating the operation type of the system controller aiming at the subsystem to be debugged;

the buffer domain segment comprises redundant bits, and the redundant bits are used for adjusting the circuit time sequence;

the data field includes transfer data, which is data that the system controller wants to transfer to the subsystem to be debugged.

In yet another aspect, an embodiment of the present application provides a chip, where the chip includes a system controller and at least one subsystem, and the system controller communicates with any one subsystem based on a four-wire serial interface; the system controller and at least one subsystem in the chip are used for realizing the chip debugging method.

In yet another aspect, embodiments of the present application provide a computer readable storage medium storing a computer program adapted to be loaded by a processor and to perform the above-described chip debugging method.

In yet another aspect, an embodiment of the present application provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described chip debugging method.

The embodiment of the application supports the communication between the system controller in the chip and each subsystem in at least one subsystem in the chip based on the four-wire serial interface. Thus, when the chip needs to be debugged, such as abnormal or dead chip bus (or subsystem, etc.), the system controller can be controlled to broadcast a first data signal to at least one subsystem through the four-wire serial interface, wherein the first data signal is used for indicating the subsystem to be debugged in the at least one subsystem. Then, the subsystem to be debugged can be controlled to report a second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, wherein the second data signal carries the state data of the subsystem to be debugged. Finally, the control system controller debugs the subsystem to be debugged based on the second data signal. It can be seen that embodiments of the present application provide a chip debug technique that is intermediate between external debug (such as JTAG/SWD debug methods) and internal debug (debug methods that access registers via a bus); the debug technique is capable of traversing inside the chip using a four-wire serial interface to interconnect the system controller and at least one subsystem into one debug system that is decoupled and independent from the chip bus. In this way, on one hand, compared with the external debugging technology, the debugging technology provided by the embodiment of the application does not need an external debugger, and can adopt the reference clock of the chip, so that higher debugging speed is ensured, and the debugging by directly utilizing the original structure of the chip has the advantage of convenient debugging without extra cost, and the automatic debugging detection and the like can be realized through software. On the other hand, compared with the internal debugging technology, the debugging technology provided by the embodiment of the application can isolate the chip bus, namely, when the chip is debugged by adopting the debugging technology, the chip bus is not required to be relied on, so that the chip can be debugged even when the chip bus is abnormal or is suspended, the dependence of the chip debugging on the chip bus is reduced, and the practicability of the chip debugging is improved.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a chip debug system provided by an exemplary embodiment of the present application;

FIG. 2 is a schematic diagram of a chip to computer device connection provided in accordance with an exemplary embodiment of the present application;

FIG. 3 is a flow chart of a method for debugging a chip according to an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of a data frame format provided by an exemplary embodiment of the present application;

FIG. 5 is a schematic diagram of a host side register provided in accordance with an exemplary embodiment of the present application;

FIG. 6 is a schematic diagram of a slave-side register provided by an exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a circuit timing diagram provided by an exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of a circuit timing sequence after a register insertion delay according to an exemplary embodiment of the present application;

FIG. 9a is a flow chart of a protocol conversion provided by an exemplary embodiment of the present application;

FIG. 9b is a schematic diagram of a deployment location of a protocol converter within a chip according to an exemplary embodiment of the present application;

FIG. 10 is a flow chart of another protocol conversion provided by an exemplary embodiment of the present application;

FIG. 11 is a schematic diagram of a chip debug apparatus according to an exemplary embodiment of the present application;

fig. 12 is a schematic diagram of a chip according to an exemplary embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The embodiment of the application relates to chip debugging, which is a process of detecting the chip function to find out the chip fault. In practical application, chip debugging technology or means can be adopted to debug the chip in the stages of chip test or chip abnormality and the like so as to find out the chip faults. The Chip according to the embodiment of the application may include a System On Chip (SOC), which refers to a technology of integrating a complete System On a single Chip and grouping all or part of electronic circuits. That is, the SOC chip may integrate a plurality of functional modules into an integrated circuit on one chip; the integrated circuit may include, but is not limited to, the following functional modules: processors (e.g., central processing units (Central Processing Unit, CPU) or graphics processors (Graphics Processing Unit, GPU), etc.), memory, peripheral interfaces, communication interfaces, clock management, and peripheral circuits. It should be understood that the chip according to the embodiments of the present application is not limited to the above-mentioned SOC chip, and the functional modules included in the SOC chip are not limited to the above-mentioned several types; for convenience of explanation, the following embodiments will be described with reference to a SOC chip as an example, and this is specifically described herein.

Conventional chip debug techniques mainly include two kinds, external debug techniques and internal debug techniques, respectively, where the external and internal are for the chip structure. Wherein: (1) the external debugging technique can be simply understood as: techniques for chip debugging through external debugging software or equipment independent and exclusive of the chip are needed; common external debugging techniques include: international standard test protocol (Join Test Action Group, JTAG) and serial debug protocol (Serial Wire Debug, SWD) techniques. The external debugging technology needs to be provided with a special I/O interface inside the chip, and the chip is internally provided with an interconnection structure and can be debugged by combining with a simulator or a facsimile machine and the like. Such external debugging techniques not only require the connection of external debugging software or equipment, resulting in inconvenient use and increased debugging costs, but also require the use of a system clock to synchronize the working timing of the external debugging software with the chip, resulting in a lower frequency of the system clock, resulting in a lower debugging rate. (2) The internal debugging technique can be simply understood as: the system controller inside the chip is used to access the registers of the subsystems inside the chip by the chip bus for detection or debugging. It can be seen that the internal debugging technique needs to rely on a chip bus (or called a chip bus, a bus, etc. which is a data transmission path between devices (or subsystems, functional modules) in the chip), so that the internal debugging technique breaks down when the chip bus works abnormally, and the practicability of the internal debugging technique is reduced.

Based on the above, the embodiment of the application provides a new chip debugging scheme or technology; the chip debugging technology is a debugging technology between an external debugging technology and an internal debugging technology, can be used for detecting and debugging the semi-black box state when a chip is in a bus and/or subsystem abnormality or is hung up, and a system controller in the chip can still work normally. The chip debugging scheme is characterized in that a four-wire serial interface is adopted in the chip to be respectively connected with a system controller and each subsystem, so that when the chip is required to be debugged, the system controller can be controlled to communicate with any subsystem (such as a subsystem to be debugged in at least one subsystem in the chip) based on the four-wire serial interface, so that the subsystem to be debugged can report own state data to the system controller, and the system controller can conveniently debug the subsystem to be debugged based on the state data of the subsystem to be debugged.

Therefore, the chip debugging scheme provided by the embodiment of the application does not depend on external debugging software, so that a special peripheral interface, a design interconnection structure and the like do not need to be deployed in the chip; the method can realize chip debugging without using peripheral debugging software, greatly reduces chip debugging cost, improves chip debugging speed, and ensures higher debugging speed by adopting a reference clock of the chip instead of external debugging software. In addition, the chip debugging scheme is used for communication between the system controller and each subsystem based on a four-wire serial interface, and a chip bus inside a chip is not required to be used; the debugging technology of the isolated chip bus can also realize the debugging of the chip under the condition that the chip bus cannot work normally, reduce the dependency of the chip debugging on the chip bus and improve the practicability of the chip debugging.

In order to better understand the chip debugging scheme provided by the embodiment of the present application, a chip debugging system provided by the embodiment of the present application is provided below in conjunction with fig. 1; the chip debugging system is deployed in a chip, such as a SOC chip. As shown in fig. 1, it is assumed that the SOC chip includes 5 subsystems, namely, subsystem 0, subsystem 1, subsystem 2, subsystem 3, and subsystem 4; the SOC chip also comprises a system controller; the system controller and subsystems may be interconnected as a separate debug system decoupled from the bus by a four-wire serial interface (e.g. a four-wire low speed serial interface) traversing the entire SOC chip. Wherein:

(1) embodiments of the present application support the designation of a system controller in a SOC chip as a host or Master device (Master). The system controller in the SOC chip may refer to: an integrated circuit (or device, component) having control over the overall structure and system of the chip.

(2) The embodiment of the application supports the fact that each subsystem in the SOC chip is called a Slave or Slave (Slave). The subsystem in the SOC chip may refer to a functional module integrated inside the chip to implement a chip function; the subsystem may include the aforementioned IP (intellectual property core ) cores (e.g., CPU and GPU, etc.) with independent functions like processors, etc., and may also include functional blocks within the chip, such as memory and peripheral interfaces, etc. It should be understood that embodiments of the present application are not limited in terms of the type of subsystem within a chip (e.g., a SOC chip).

(3) The serial interface, serial communication interface, etc. is an expansion interface adopting serial communication mode. The four-wire serial interface (or 4-wire serial interface) according to the embodiment of the present application refers to a serial interface technology implemented by using 4 signal wires or data wires. The 4-wire serial interface includes: an enable signal line SEN, a clock signal line SCK, a data line SDO, and a data line SDI; wherein: an enable signal line SEN or serial interface data frame enable for controlling the on and off of debug mode for the chip; when the level state of the enabling signal on the enabling signal line is high level, the debug mode is started; when the level state of the enable signal on the enable signal line is a low level, the debug mode is turned off. The clock signal line SCK or serial interface data adopts pulses for controlling the data receiving and transmitting synchronization between the system controller and the subsystem; when the level state of the clock signal or the clock pulse on the clock signal line is high level, the system controller and the subsystem can sample data signals, for example, the system controller samples a second data signal reported by the slave device to be debugged through the data line SDI, and the subsystem to be debugged samples a first data signal broadcast by the system controller through the data line SDO. The data line SDO refers to a data line for outputting data from a system controller (i.e., a host), and is mainly used for controlling data signal transmission from the system controller to a subsystem. The data line SDI refers to a data line for outputting data from a subsystem to be debugged (i.e., a slave), and is mainly used for controlling data signal transmission from the subsystem to the system controller. For convenience of explanation, when the data lines are defined in a direction of a signal flow of the data signals from the master to the slave, the data lines SDO may be referred to as output data lines SDO, and the data lines SDI may be referred to as input data lines SDI.

Further, the signal flow directions of the data signals on the enable signal line SEN, the clock signal line SCK, and the output data line SDO are: broadcast from the system controller (i.e., the master) to each of the at least one subsystem (i.e., the slaves) within the chip. Conversely, the signal flow direction of the data signal on the input data line SDI is: from the subsystem to the system controller. That is, the SCK data signal, the SEN data signal, and the SDO data signal sent by the system controller are directly broadcast to the subsystems in the chip, where the SDI data signals sent by the subsystems are converged at the system controller side and then connected to the system controller (specifically, when the number of the subsystems to be debugged is at least two, the SDI data signals sent by the subsystems to be debugged are input to the system controller after performing an or logic operation at the system controller side).

Furthermore, the 4-wire serial interface provided by the embodiment of the application realizes communication based on the synchronous serial transmission specification. Among them, the synchronous serial transmission specification is alternatively called synchronous serial transmission protocol or data frame protocol, etc. Serial communication in the synchronous serial transmission specification refers to: two communication parties carry out data transmission according to bits and observe a communication mode of time sequence. That is, data is sequentially transmitted in serial communication by bits, and each bit of data occupies a fixed time length, that is, information exchange between systems can be completed using a small number of communication lines (called data lines or signal lines, etc.). Serial communication can be applied to serial transmission of communication (such as a main control CPU and a functional chip) among systems (such as a multi-main control system), between devices (such as a main device and a reset device) and among devices in a chip, so that data transmission and sharing are realized. Similarly, synchronous communication in the synchronous serial transmission specification refers to: under the agreed communication rate, the clock signals and phases of the sending end and the receiving end are always consistent (i.e. synchronous), so that the two parties of communication have a completely consistent data transmission relationship when sending and receiving data. Therefore, when communication is performed in compliance with the synchronous serial transmission specification, a clock signal needs to be transmitted while data is transmitted so that a receiving side can determine information bits based on the clock signal, thereby realizing synchronous serial transmission between a transmitting side and a receiving side.

In addition, in the chip debug system provided by the embodiment of the application, a register delay can be inserted into each data line, as shown in a "D" shown in fig. 1, where the "D" may be specifically a device (such as a register) with a delay function of an entity, and the number of "D" of one data line is used to represent the duration of the register delay on the data line. This is considered that in a chip debug system based on synchronous serial transmission, there is often a possibility that inconsistency of signal timing, i.e., timing problem, may occur for various reasons (e.g., SOC chip or even a large chip in which a communication distance between a master and each slave is long, etc.). Timing problems refer to problems that occur in timing control and data transmission in debug systems, such as timing errors, timing failures, or timing distortions. Therefore, to overcome timing issues in debug systems, embodiments of the present application support inserting register delays in a 4-wire serial interface; in this way, the register delay can ensure consistency of time sequence control and data transmission, thereby avoiding various transmission problems caused by hysteresis of any data signals (such as time sequence signals or signals of data transmission).

Based on the above exemplary description of the circuit structure of the chip debug system, the general flow of the chip debug scheme is described below with reference to the schematic circuit structure shown in fig. 1. In the specific implementation, when the chip has a debugging requirement, the chip can control the system controller to start a debugging mode of the chip debugging system by changing the enabling signal line from a low level to a high level; and the control system controller sends clock pulses or clock periods to all subsystems of the chip debugging system through the clock signal line; and, the system controller may also encapsulate the data transmission frame format (or simply the data frame format) provided by the embodiment of the present application into the first data signal based on the information such as the device identifier and the register address of the subsystem to be debugged that wants to debug. The control system controller then broadcasts a first data signal to at least one subsystem within the chip debug system via a four-wire transport interface (specifically an output data line in the four-wire transport interface). In this way, after each subsystem in at least one subsystem samples the first data signal through the output data line, whether the subsystem is a subsystem needing to report data can be judged; if yes, and the first data signal indicates that the read operation (or simply referred to as the read operation) is performed on the subsystem to be debugged, the subsystem to be debugged can be controlled to report a second data signal to the system controller through a four-wire serial interface (particularly an input data line in the four-wire serial interface) according to the indication of the first data signal, wherein the second data signal carries the state data of the subsystem to be debugged. Finally, after the control system controller samples the second data signal through the input data line, the subsystem to be debugged can be debugged based on the second data signal.

Based on the above simple introduction of the chip debug scheme and the chip debug system, it is also to be noted that:

(1) in the above exemplary debugging process, the system controller may send the state data of the subsystem to be debugged to the universal serial port or the USB interface originally set in the chip after obtaining the state data of the subsystem to be debugged. Furthermore, the chip is connected with the computer equipment (such as through a data line) by adopting a general serial port or a USB interface which is originally arranged; in this way, the chip can send the subsystem to be debugged to the computer equipment through the universal serial port or the USB interface, so that the computer equipment adopts a debugging program (such as universal serial port debugging software or debugging program written by a debugger) to realize automatic debugging on the chip (particularly, debugging the subsystem to be debugged) based on the state data of the subsystem to be debugged after acquiring the state data of the subsystem to be debugged, which is transmitted by the chip. In addition, if the computer device is provided with a display screen, the embodiment of the application also supports the visual presentation of the status data of the subsystem to be debugged and the debugging result to the debugging personnel; through the visual debugging mode, the chip debugging process is transparent and visual, and the accuracy and the chip debugging performance of the chip debugging are improved to a certain extent. An exemplary diagram of outputting state data of a subsystem to be debugged to a computer device for visual presentation may be seen in fig. 2.

The computer device according to the embodiment of the application may be a terminal or a server. Terminals may include, but are not limited to: smartphones (such as smartphones deployed with Android systems or smartphones deployed with internet operating systems (Internetworking Operating System, IOS)), tablet computers, portable personal computers, mobile internet devices (Mobile Internet Devices, MID), vehicle devices, headsets, smart homes, and other terminal devices. The server may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), basic cloud computing services such as big data and artificial intelligent platforms, and the like. The embodiments of the present application are not limited to the specific type of computer device described herein.

(2) The circuit configuration of the debug system shown in fig. 1 and 2 is exemplary. For example, the number of register delays "D" inserted on different signal lines or data lines in the debug system shown in fig. 1 is not fixed. For another example, the number of subsystems shown in fig. 1 is 5, but the number of subsystems may be other numbers in practical applications.

(3) The circuit structure or circuit traces shown in fig. 1 are cured in the chip at the time of chip production; therefore, in the use process of the chip, the chip can be debugged by directly using the circuit connection of the cured debugging system inside the chip as long as the chip has debugging requirements; and debugging software and the like are not required to be externally connected, so that the debugging cost and the debugging time are saved to a certain extent, and the debugging efficiency and performance are improved.

Based on the above described chip debugging scheme and chip debugging system, the embodiment of the application provides a more detailed chip debugging method, and the chip debugging method provided by the embodiment of the application will be described in detail with reference to the accompanying drawings.

FIG. 3 is a flow chart of a method for debugging a chip according to an exemplary embodiment of the present application; the chip debugging method shown in fig. 3 may be performed by a chip, and the chip debugging method may include, but is not limited to, steps S301 to S303:

s301: the control system controller broadcasts a first data signal to at least one subsystem via the four-wire serial interface.

When the chip is specifically required to debug, for example, the chip is an SOC chip, and when the SOC chip cannot work normally, the system controller in the chip can be controlled to package the chip debugging requirement (specifically, information required to respond to the chip debugging requirement) into the first data signal by adopting the data transmission frame format provided by the embodiment of the present application. The first data signal is then broadcast over a four-wire serial interface to each of at least one subsystem within the chip to enable debugging of all or a portion of one or more subsystems included within the chip.

Specifically, the first data signal according to the embodiment of the present application carries a data frame, and the format of the data frame meets the data transmission frame format provided by the embodiment of the present application. Wherein, the length of the data frame meeting the data transmission frame format provided by the embodiment of the application is fixed; and one data frame is independently accessed, and no dependence exists on the front and back data frames, namely, one data frame is required for each access of the system controller to the subsystem direction, and the data frames accessed before and after are not required for each access.

The following describes the data transmission frame format mentioned in connection with fig. 4; as shown in fig. 4, the data frame satisfying the data transmission frame format includes 5 field segments; according to the sequence of the sending time of each domain segment, the data frames comprise the following steps in sequence: a control domain segment, a buffer domain segment, and a data domain segment, the control domain segment comprising a device identification domain segment, a register domain segment, and an operation domain segment. The following describes the field segments included in the data frame in conjunction with table 1, as shown in table 1:

TABLE 1

As shown in table 1: (1) The device identification field (Slave ID) in the data frame includes a device identification of a subsystem to be debugged in at least one subsystem included in the chip. In this way, the first data signal carrying the device identification field (Slave ID) may be used to indicate a subsystem to be debugged in at least one subsystem, which is referred to as a subsystem to be debugged, and indicates that the subsystem indicated by the device identification carried by the device identification field (Slave ID) is to be debugged. That is, the host according to the embodiment of the present application addresses each Slave in the chip through a device identification field (Slave ID), and the Slave determines whether to respond to the access of the host by identifying the device identification in the device identification field (Slave ID).

(2) The register field (CSR ID) in the data frame includes the address of the target register in the register set on the side of the subsystem to be debugged, where the target register is the register in the register set that the system controller wants to access. That is, the system controller (i.e., the host) performs status acquisition and detection of the subsystem to be debugged (i.e., the slave) by performing read and write operations on the command and status register (Command and Status Register, CSR) registers of the subsystem to be debugged. Wherein, the host side and the slave side related to the embodiment of the application are both provided with a transmission protocol register set (or simply referred to as a register set); the register set includes a plurality of registers, such as 32 registers on both the master side and the slave side in the embodiment of the present application. The 32 registers define 4 underlying registers CSR for implementing data processing for a device (e.g., a system controller or subsystem); such as status data for at least the caching device (e.g., a system controller or subsystem), which may be used to reflect the operational status of the device (e.g., normal operation, or abnormal points in the case of abnormal operation). The remaining 28 registers CSR, except for the 4 underlying registers, of the 32 registers are used for protocol expansion; the user can customize the device according to the protocol requirements of the user under different chip scenes.

For example, taking a register group including 32 registers as an example, a schematic diagram of a register set at the host side can be seen in fig. 5. As shown in fig. 5, the register set on the system controller side includes 32 registers, which are respectively: WCSR read register, RCSR write register, CMD register, GTSP register, and 28 Reserved registers. The registers are described below in conjunction with table 2, as shown in table 2:

TABLE 2

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As shown in table 2, (1) the register identifier of the WCSR register in the register set at the system controller side is 0, that is, when the register identifier 0 is identified, it can be determined that access is realized to the WCSR register; and the WCSR register is mainly used for storing the register content read by the system controller from the subsystem side. (2) The register mark of the RCSR register in the register group of the system controller side is 1, namely when the register mark 1 is identified, the access to the RCSR register can be determined; and the RCSR register is mainly used for storing the register content of the write subsystem side of the system controller. (3) When the register identifier of the CMD register in the register group on the system controller side is 2, that is, when the register identifier 2 is identified, it can be determined that the CMD register is accessed. Reserved field sections with positions of 31:18 bits and 15:13 bits in the CMD register are Reserved, namely, data are not written; the OP field segment with the position of 17:16 bits in the CMD register is used for storing the operation code; the CSRID field with the position of 12:8 bits in the CMD register is used for storing the address CSRIndex of the accessed slave register; the Slave ID field with the position of 7:0 bits in the CMD register is used for storing the device identification Slave ID of the accessed Slave. (4) The register identifier of the GTSP register in the register group at the system controller side is 3, that is, when the register identifier 3 is identified, it can be determined that access is implemented to the GTSP register. The GTSDIFF domain segment with the position of 31:16 bits in the GTSP register is used for storing a GTSD operation result, and the GTSD operation result is used for measuring the number of register stages inserted between each slave machine and the host machine and determining whether the Timestamp synchronization between the slave machine and the host machine is correct or not; the GTSSDLY field with the position of 15:0 bits in the GTSP register is used for storing the delay result of the GTSS, and the master synchronizes the time stamp to the slave in operation. (5) The Reserved register with the register mark of 4-31 in the register group of the system controller side does not store data; in practical application, the method is used for customizing the data in the registers according to protocol requirements.

By way of example, a schematic diagram of registers set from the slave side can be seen in fig. 6, with 32 registers included in the register set. As shown in fig. 6, the register set on the subsystem side includes 32 registers, which are respectively: RDATA read registers, WDATA write registers, CON registers, ST registers, and 28 Reserved registers. The registers are described below in conjunction with table 3, as shown in table 3:

TABLE 3 Table 3

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As shown in table 3, (1) the register identifier of the RDATA register in the register group at the subsystem side is 0, that is, when the register identifier 0 is identified, it can be determined that the access to the RDATA register is realized; and the RDATA register is mainly used for indirectly accessing the read data register of the bus. (2) The register mark of the WDATA register in the register group at the subsystem side is 1, namely when the register mark 1 is identified, the WDATA register can be identified to be accessed; and WDATA registers are used primarily for indirectly accessing the write data registers of the bus. (3) The register identifier of the CON (control) register in the register group at the subsystem side is 2, that is, when the register identifier 2 is identified, it can be determined that the access to the CON register is realized. The Reserved domain segment with the positions of 31:30 bits and 1 bit in the CON register is Reserved, namely, data is not written; ADDR field segment with 29:2 bits in CON register is used to indirectly access the address register of bus, unit 4-byte; the WRITE field segment with 0 bit in the CON register is used for indicating the WRITE operation of the indirect access bus, when the WRITE field segment takes the value bit 1, the WRITE operation of the indirect access bus is indicated, and when the WRITE field segment takes the value bit 0, the read operation of the indirect access bus is indicated. (4) When the register identifier 3 is identified, that is, the register identifier 3 of the ST register in the register group on the subsystem side, it can be determined that the access to the ST (status) register is to be realized. The Reserved domain segment with the position of 31:2 bits in the ST register is Reserved, namely, data is not written in; the READY domain segment with the position of 1 bit in the ST register is a bus access completion flag, when the READY domain segment is 1, the completion of the bus access is indicated, and when the READY domain segment is 0, the incompletion of the bus access is indicated; the SLVERR domain segment with 1 bit in the ST register is a bus access error mark, when the value of the SLVERR domain segment is 1, the bus access is wrong, and when the value of the SLVERR domain segment is 0, the bus access is normal. (5) The Reserved register with the register mark of 4-31 in the register group at the subsystem side does not store data; in practical application, the method is used for customizing the data in the registers according to protocol requirements.

It is noted that the above-mentioned Bus is a Bus protocol to which the chip originally communicates, such as a standard on-chip Bus protocol (Advanced Peripheral Bus, APB), a standard on-chip Bus protocol (Advanced eXtensible Interface, AXI), or a standard on-chip Bus protocol (Advanced High-performance Bus, AHB). In addition, when the chip works under the APB bus protocol, the name of each register can be added with a prefix P so as to intuitively perceive that the register works under the APB bus protocol; as RDATA registers are denoted as PRDATA registers, WDATA registers are denoted as PWDATA registers, CON registers are denoted as PCON registers and ST registers are denoted as PST registers. Similarly, the name of the domain segment contained in the register may also be added with the prefix "P"; the RDATA field in the PRDATA register is denoted as the PRDATA field, the WDATA field in the PWDATA register is denoted as the PWDATA field, the ADDR field in the PCON register is denoted as the PADR field, the WRITE field is denoted as the PWRITE field, the READY field in the PST register is denoted as the PRADY field, and the SLVERR field is denoted as the PSLVERR field.

Based on the above-described fig. 5, 6, table 2, and table 3, the contents of the register group on the master side and the register group on the slave side are respectively related. In the actual accessing process, the accessing to a certain register in the register group is mainly realized through the register field CSR ID in the data frame format. For example: if the host wants to read slave-side data or write data to the slave, the host may generate a data signal based on information such as the register identification of a register in the register set of the slave side and the addresses of different field segments in the register; thus, after receiving the data signal, the slave can perform operations such as data reading or data writing on the registers in the register set based on the address carried by the data signal and the instruction. And the following steps: if the slave wants to read host-side data or write data to the host, the slave may generate a data signal based on information such as the register identification of a register in the register set on the host side and the addresses of different field segments in the register; thus, after receiving the data signal, the host can perform operations such as data reading or data writing on the registers in the register set based on the address carried by the data signal and the indication.

(3) The operation field section in the data frame comprises an operation code, and the operation code is used for indicating the operation type of the system controller for executing the operation aiming at the subsystem to be debugged. Wherein, the value of the operation code comprises any one of the following: the first value 0, the second value 1, the third value 2 and the fourth value 3. When the value of the operation code is the first value 0, the operation type of the system controller for executing the operation on the subsystem to be debugged is as follows: read operations for registers on the side of the subsystem to be debugged. When the value of the operation code is the second value 1, the operation type of the system controller for executing the operation on the subsystem to be debugged is as follows: write operations to registers on the side of the subsystem to be debugged. When the value of the operation code is the third value 2, the operation type of the system controller for executing the operation on the subsystem to be debugged is as follows: a read operation for a timestamp of the subsystem side to be debugged. When the value of the operation code is the fourth value 3, the operation type of the system controller for executing the operation on the subsystem to be debugged is as follows: synchronizing the timestamp of the system controller to the subsystem to be debugged.

(4) The buffer field section in the data frame comprises redundancy bits, and the redundancy bits are used for adjusting the circuit time sequence; i.e. the buffer field segment is used to adjust the timing between the system controller and each of the at least one subsystem. That is, the data field segment in the data frame includes redundant bits; the data line buffers a transmission time interval of the content of the field segment before and after the data field segment by transmitting the one or more bits, and the slave receiving the buffer field segment does not parse the buffer field segment. The embodiment of the application introduces the buffer domain segment into the data frame, so that the data frame protocol can accommodate a certain response time delay of the Slave.

(5) The data field in the data frame includes transfer data that the system controller wants to transfer to the subsystem to be debugged. When the value of the operation code filled in the operation field section in the data frame is the first value 0 or the second value 1, the transfer data included in the data field section is as follows: 32 bits of register data. When the value of the operation code filled in the operation field section in the data frame is the third value 2 or the fourth value 3, the transfer data included in the data field section is as follows: 64-bit timestamp.

Therefore, the embodiment of the application designs a data transmission frame protocol (or simply referred to as a data frame protocol), realizes a debugging system which is globally threaded and interconnected in a large chip and is in butt joint with each subsystem and a system controller, and can be suitable for detection and debugging under the condition that the IP and the bus in the chip are in a non-response state, and the debugging system is also called an escape channel (Escape Channel Interface, ECI) of the chip.

Further, in the actual chip debugging process, the system controller may be controlled to generate the first data signal based on the data transmission frame format described in the foregoing (1) - (5), and broadcast the first data signal to each subsystem inside the chip. It should be noted that, the 4-wire serial interface provided by the embodiment of the application realizes synchronous serial communication between the host and the slave based on the data frame transmission time sequence; compared with the system clock, the 4-wire serial interface can effectively improve the chip debugging rate when working under the self-contained reference clock of the chip.

For example, a timing chart of the system controller side (i.e., the host side) can be seen in fig. 7; as shown in fig. 7, the four-wire serial interface operates under the reference clock of the chip itself, i.e., the clock pulses of the clock signal lines in the four-wire serial interface are counted with reference to the reference clock. When the system controller needs to broadcast the first data signal, the system controller can be controlled to broadcast an enabling signal to at least one subsystem through an enabling signal line; i.e., the level state of the enable signal on the enable signal line is changed from a low level to a high level, indicating that the debug mode of the chip is turned on. Then, when the level state of the enable signal line is at a high level, that is, when the debug mode of the chip is started, the system controller may be controlled to broadcast continuous clock pulses to at least one subsystem through the clock signal line; in this way, the system controller communicates with the subsystems within the chip based on the same clock pulses, ensuring synchronous serial communication between the master and the slaves. Wherein the rising edge of the high level of the enable signal is aligned with the rising edge of the first clock pulse of the successive clock pulses on the clock signal line. Wherein one clock pulse on the clock signal line may refer to one clock period including a high level and a low level; as shown in fig. 7, the clock 701 includes a high level 702 and a low level 703, and a rising edge of the high level 702 is a rising edge 7021.

Further, in a state that the enabling signal between the system controller and each subsystem is at a high level and the clock signal line works normally; when the clock pulse on the clock signal line is at a high level, the system controller may be controlled to generate a first data signal for the system controller and, starting from the rising edge of the clock pulse, to broadcast the first data signal to at least one subsystem inside the chip via the output data line SDO. As can be seen from the foregoing description, the data frame carried by the first data signal includes a control field segment, a buffer field segment and a data field segment in sequence, and then the control field segment, the buffer field segment and the data field segment are broadcast to at least one subsystem in sequence when the first data signal is broadcast; as shown in fig. 7, a control field segment (abbreviated CMD) is broadcast on the output DATA line with 4 clock pulses, a buffer field segment (abbreviated GAP) is broadcast after the control field segment broadcast is finished, and a DATA field segment (abbreviated DATA, including mainly WCSR/GTS DATA) is broadcast with 4 clock pulses after the buffer field segment broadcast is finished. It should be noted that the number of clock pulses (i.e., the transmission duration) specifically consumed when each field segment included in the data frame is broadcast via the output data line is related to the data amount of the data included in each field segment, and the number of the above-described exemplary clock pulses is not limited.

S302: and the subsystem to be debugged is controlled to report a second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal.

The control system controller broadcasts the control domain segment, the register domain segment and the operation domain segment in sequence through the output data line based on the steps shown in the previous step S301; for each of at least one subsystem within the chip, the process of sampling the first data signal and generating the second data signal may include, but is not limited to:

(1) each subsystem samples the first data signal and determines whether itself is the subsystem to be debugged that the system controller accesses. Specifically, starting from the rising edge of the clock pulse, each subsystem is controlled to sample the control domain segment carried by the first data signal through the output data line in the high level state of the clock pulse. And controlling each subsystem to analyze and read the equipment identification domain segment included in the control domain segment to obtain the equipment identification included in the equipment identification domain segment, wherein the equipment identification is the equipment identification of the subsystem with debugging requirements (namely the subsystem to be debugged) in at least one subsystem. Then, based on the device identifier included in the device identifier field section obtained through analysis, determining a subsystem to be debugged, wherein the device identifier is identical to the device identifier included in the device identifier field section, from at least one subsystem. That is, after resolving the device identifier contained in the device identifier field, each subsystem compares the device identifier with its own device identifier; and determining the response host only when the parsed device identification is the same as the self device identification, namely executing the subsequent operation.

(2) After determining the subsystem to be debugged from at least one subsystem based on the steps, after the control domain segment of the subsystem to be debugged carried by aiming at the first data signal is controlled to be sampled, the control domain segment of the subsystem to be debugged can be controlled to respond to the control domain segment to acquire the state data of the subsystem to be debugged from the register set at the side of the subsystem to be debugged. In detail, as can be seen from the foregoing description, the to-be-debugged subsystem side is provided with a register set, the register set of the to-be-debugged subsystem side includes a plurality of registers, and the registers are at least used for caching state data of the to-be-debugged subsystem; the control domain section comprises a register domain section and an operation domain section besides the equipment identification domain section; the register field segment records the register address of the register set on the side of the subsystem to be debugged, which the system controller wants to access, and the operation code contained in the operation field segment indicates the operation type (such as read operation or write operation) of the register indicated by the register address. Therefore, after sampling the control domain segment, the subsystem to be debugged can be controlled to analyze the register domain segment contained in the control domain segment to obtain the register address; the register address refers to the address of a register which is to be accessed by a system controller in a register group at the side of a subsystem to be debugged; and controlling the subsystem to be debugged to analyze the operation domain segment to obtain an operation code; and then, if the operation code indicates that the operation type is a read operation, controlling the subsystem to be debugged to read the state data of the subsystem to be debugged from the register indicated by the register address based on the operation code.

(3) And controlling the subsystem to be debugged to package the state data of the subsystem to be debugged into a second data signal, and controlling the subsystem to be debugged to report the second data signal carrying the state data of the subsystem to be debugged to the system controller through the input data line. It is noted that the data frame format of the second data signal is not the same as the data frame format of the first data signal; taking the subsystem to be debugged as a slave, reporting the second data signal to a host 'system controller' by default, so that only state data (such as RCSR and GTS data) of the subsystem to be debugged need to be carried in the second data signal; thus, not only transmission resources can be saved, but also transmission speed and efficiency can be improved.

S303: the control system controller debugs the subsystem to be debugged based on the second data signal.

As can be seen from the foregoing description, after controlling the to-be-debugged subsystem to sample the control domain segment carried by the first data signal sent by the system controller through the output data line, the to-be-debugged subsystem may report the second data signal generated based on the first data signal to the system controller through the input data line SDI from the rising edge of the first clock pulse after sampling the control domain segment. Then, after the system controller samples the second data signal, the system controller can be controlled to analyze the second data signal to obtain the state data of the subsystem to be debugged; and debugging the subsystem to be debugged based on the state data of the subsystem to be debugged. In the above process, it is considered that in the data signal transmission process, there is often hysteresis on the data line or the signal line; in order to enable the system controller to completely sample the second data signal through the input data line, the embodiment of the application supports that the interval between the adjacent high levels of the clock signal line SCK is adjustable, that is, the SCK duty ratio (that is, the proportion of the high level to the clock pulse) is customizable, so as to accommodate the register delay of different stages when the enable signal line SEN, the clock signal line SCK, the output data line SDO and the input data line SDI are wired globally, and avoid the problems of incomplete signal sampling caused by hysteresis.

Specifically, considering that the data signals from the system controller to the direction of the enable signal line SEN, the clock signal line SCK, and the output data line in at least one subsystem direction are uniformly issued by the system controller, it is supported to insert the same number of register delays in the enable signal line SEN, the clock signal line SCK, and the output data line SDO in the direction of the system controller to the at least one subsystem direction, which may be referred to as a first register delay, denoted as Nfp; i.e. the first register delay Nfp is determined based on the number of stages of register delays inserted in the direction of the system controller to at least one subsystem. Similarly, considering that the data signals from each subsystem to the direction of the system controller are sent out by each subsystem separately, the number of stages of the register delays inserted in different input data lines from at least one subsystem to the direction of the system controller is allowed to be the same or different, and the register delays can be called as second register delays and recorded as Nbp; i.e. the second register delay Nbp is determined based on the number of stages of register delays inserted in the direction of the subsystem to be debugged to the system controller. The larger the number of stages of the register inserted on any one data line or signal line is, the longer the register delay on any one data line or signal line is; the number of register stages is determined according to the number of devices (e.g., registers) having a delay function inserted on the data line or the signal line. In the circuit diagram shown in fig. 1, 4 devices "D" having a delay function are inserted into the enable signal line SEN, the clock signal line SCK, and the output data line SDO from the system controller to each subsystem, and thus the delay of the registers on the enable signal line SEN, the clock signal line SCK, and the output data line SDO is considered to be the delay caused by the 4 devices "D".

The transmission duration of the buffer field segment carried by the first data signal on the output data line SDO (or the time interval between the broadcast end time of the control field segment carried by the first data signal and the broadcast start time of the data field segment) is denoted Nsck, which is greater than or equal to the sum of the first register delay Nfp and the second register delay Nbp, i.e. Nsck is ≡ Nfp +nbp. Therefore, the normal operation of the four-wire serial interface can be ensured, namely, after the control system controller sends out the buffer domain segment through the output data line, the control system controller can sample the second data signal reported by the subsystem to be debugged through the input data line SDI in the four-wire serial interface from the rising edge of the first clock pulse after the buffer domain segment is broadcasted. The problem that the system controller cannot sample the complete second data signal due to hysteresis caused by that the second data signal does not reach the system controller yet when the first clock pulse is sent out by the buffer field GAP is avoided.

For example, an exemplary circuit timing chart after inserting a register delay in the enable signal line SEN, the clock signal line SCK, the output data line SDO, and the input data line SDI may be seen in fig. 8. As shown in fig. 8, the host "system controller" issues a control field segment (denoted CW or CMD) carried in the first data information through the output data line SDO, starting at the rising edge of the first clock pulse of the clock signal line SCK; since the enable signal line SEN, the clock signal line SCK and the output data line SDO have the same number of register delays inserted, when the slave "to-be-debugged subsystem" delays the rising edge of the first register delay Nfp and the high level of the clock signal line SCK, after sampling the control domain segment through the output data line SDO, the second data signal generated based on the control domain segment can be reported to the host through the input control line SDI at the rising edge of the first clock pulse after the sampling is completed. Similarly, a register delay is inserted in the input data line SDI in the slave-to-host direction, and then it starts to receive the second data signal after delaying the second register delay Nbp for the host. To ensure that the rising edge of the first clock pulse of the host after sending out the buffer field segment can sample the second data signal, it is necessary to ensure that Nsck is equal to or greater than Nfp +nbp; in this way, the rising edge of the first clock pulse after the host sends out the buffer domain segment can sample the second data signal, so that the integrity of the second data information sampling is ensured, and the debugging is facilitated based on the state data of the relatively complete subsystem to be debugged, and the debugging accuracy is improved.

In addition, it should be noted that, when the whole SOC chip is operated under a standard bus protocol (such as APB protocol, AXI protocol or AHB protocol, etc.), in order to not destroy the original communication mechanism (i.e., bus protocol) of the SOC chip when the chip debug system deployed in the chip is to access the SOC chip, a protocol converter needs to be introduced to implement conversion between the original bus protocol of the SOC chip and the data frame protocol (i.e., the protocol containing the content of the foregoing data frame format and circuit timing, etc.) related to the embodiment of the present application. Therefore, the conversion of the two protocols can be realized quickly by introducing the protocol converter without destroying the original communication mechanism of the SOC chip. A schematic flow chart of the mutual conversion of the data frame protocol and the native bus protocol of the SOC chip, which is described in an exemplary embodiment of the present application, may be seen in fig. 9a. As shown in fig. 9a, assume that a Master "system controller" is to read status data of a subsystem to be debugged, which is recorded in a certain real register in the subsystem to be debugged; considering that the SOC chip only recognizes the original bus protocol, the Master needs to first initiate a read request of one bus protocol following the original bus protocol (e.g., APB). The read request conforming to the bus protocol is then converted by the protocol converter into a first data signal under the data frame protocol provided by the embodiment of the application for transmission. Further, after receiving a first data signal conforming to a data frame protocol, the Slave "subsystem to be debugged" may convert the first data signal into data under a bus protocol through a protocol converter; and performs operations such as reading the contents of the registers based on data conforming to the bus protocol. It should be understood that, in the scenario where the Slave needs to transmit data to the Master, two protocol conversions are required, and the specific implementation process of the protocol conversion is similar to the process of the two protocol conversions from the Master to the Slave described above, which is not described herein.

It should be noted that, the protocol converter in the protocol conversion process shown in fig. 9a is disposed at the interface entrance of the master "system controller" and the slave "subsystem", as shown in fig. 9 b. Thus, for the host, the protocol converter is required to convert the data originally conforming to the bus protocol into the data conforming to the data frame protocol provided by the embodiment of the application, and then the data is transmitted. For the slave, after receiving the data conforming to the data frame protocol provided by the embodiment of the application, the slave adopts a protocol converter to convert the data into the data conforming to the bus protocol, so that the slave can realize the reading and writing of the register according to the bus protocol originally conforming to. Therefore, the embodiment of the application introduces the protocol converter at the interface of the host computer and the slave computer, so that the original communication mechanism of the host computer and the slave computer can be adapted after the debugging system is introduced into the chip, and the debugging is not needed to be carried out by depending on the system bus inside the chip, so that the debugging of the chip can be realized when the system bus does not work.

In a specific implementation, it is assumed that the SOC chip complies with a target bus protocol (e.g., APB bus protocol); the protocol conversion process of the debug system (or SOC chip) may include, but is not limited to: a sender of the data signal generates a target data signal based on a target bus protocol; then, carrying out protocol conversion on the target data signal to obtain an intermediate data signal conforming to a data frame protocol corresponding to the four-wire serial interface; finally, after the receiving side of the data signal receives the intermediate data signal conforming to the data frame protocol, the intermediate data signal is subjected to protocol conversion to obtain a target data signal conforming to the target bus protocol. When the sender of the data signal is a system controller, the receiver of the data signal is a subsystem to be debugged, and the intermediate data signal is a first data signal; when the sender of the data signal is the subsystem to be debugged, the receiver of the data signal is a system controller, and the intermediate data signal is a second data signal.

In order to facilitate understanding the above-described protocol conversion process, a specific process of initiating the protocol conversion of APB writing and reading by the host is given below by taking the original protocol of the SOC chip as an APB protocol as an example.

1) As in the first figure shown in fig. 10, the protocol conversion process for host initiated APB writing may include, but is not limited to:

(1) when the host computer needs to write data into a write data register PWDATA of the slave side, the host computer initiates a write request based on an original bus protocol APB of the SOC chip; the write request is then converted into data PWDATACSR that complies with the data frame protocol to which embodiments of the present application relate.

(2) The host computer also generates an address register of a register to be accessed based on an original bus protocol APB of the SOC chip; and converted into data of a data frame protocol. Specifically, setting the value of the field PWRITE in the register PCON to 1, i.e., pcon.pwrite=1, indicates a write operation instruction for indirectly accessing the APB bus. And, an address register, specifically, a control word address accessed by the APB, is set for a field PADDR in PCON (as expressed as PCON.

(3) After receiving the write operation to the register PWDATACSR, the slave converts the write operation into data conforming to the APB bus protocol; and initiates a write transaction WriteTransaction of the APB bus based on the APB bus protocol compliant data while clearing the value of the domain segment PREADY in the register PST (i.e., clearing pst.pready).

(4) After the slave responds to the write operation, it writes pst.pready= 1 and latches PSLVERR of the APB bus to pst.pslverr, indicating that the slave has completed the access (specifically the write operation).

(5) When the host queries pst.pready= 1, it is determined that the slave side has completed the write operation, thereby determining that writing to the APB register is completed.

2) As in the second figure shown in fig. 10, the protocol conversion process for the host to initiate APB reading may include, but is not limited to:

(1) when the host needs to read the data in the slave side register, the host initiates a read request based on the original bus protocol APB of the SOC chip; the read request is then converted into data following the data frame protocol to which embodiments of the present application relate. Specifically, pcon.pwrite=0 is written after conversion, and pcon.paddr is set as the control word address for APB bus access.

(2) After receiving the write operation of the register PCONCSR, the slave machine firstly performs the protocol conversion, namely converting the data frame protocol into the APB bus protocol; then, a read transaction ReadTransaction of the APB bus is initiated while pst.pready is cleared.

(3) The slave sets pst.pready to 1 and latches PSLVERR to pst.pslverr and PRDATA to PRDATA of the APB bus, indicating that the APB access has been completed.

(4) The master determines that the slave completes the read operation when it queries pst.pready= 1.

(5) The host reads the read data register PRDATA CSR and completes reading the data in the APB register.

It should be understood that the above-described protocol conversion process for initiating APB writing/reading by the host is exemplary and not limited to the protocol conversion process, and is specifically described herein.

In summary, the embodiments of the present application provide a chip debug technique between external debug (such as JTAG/SWD debug method) and internal debug (debug method by accessing registers through bus); the debug technique is capable of traversing inside the chip using a four-wire serial interface to interconnect the system controller and at least one subsystem into one debug system that is decoupled and independent from the chip bus. On one hand, the reference clock of the chip is supported, so that higher debugging speed is ensured, the original structure of the chip is directly utilized for debugging, the advantage of convenient debugging is realized, no extra cost is generated, and automatic debugging detection and the like can be realized through software. On the other hand, the chip debugging method provided by the embodiment of the application isolates the chip bus, namely, when the chip is debugged by adopting the debugging technology, the chip bus is not required to be relied on, so that the chip can be debugged even when the chip bus is abnormal or is suspended, the dependence of the chip debugging on the chip bus is reduced, and the practicability of the chip debugging is improved.

The foregoing details of the method of embodiments of the present application are provided for the purpose of better implementing the foregoing aspects of embodiments of the present application, and accordingly, the following provides an apparatus of embodiments of the present application.

FIG. 11 is a schematic diagram showing a chip debug apparatus according to an exemplary embodiment of the present application; the chip debugging means may be a computer program (including program code) running on the computer device, for example the chip debugging means may be an application of the computer device or a computer program in the chip; the chip debugging means may be used to perform some or all of the steps in the method embodiment shown in fig. 3. Referring to fig. 11, the chip includes a system controller and at least one subsystem, and the system controller communicates with any subsystem based on a four-wire serial interface; the chip debugging device comprises the following units:

a transmitting unit 1101 for controlling the system controller to broadcast a first data signal to at least one subsystem via the four-wire serial interface; the first data signal is used for indicating a subsystem to be debugged in at least one subsystem;

the sending unit 1101 is further configured to control the subsystem to be debugged to report a second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, where the second data signal carries status data of the subsystem to be debugged;

And the processing unit 1102 is used for controlling the system controller to debug the subsystem to be debugged based on the second data signal.

In one implementation, the sending unit 1101 is further configured to:

In one implementation, a first data signal carries a data frame including a control field segment, a buffer field segment, and a data field segment; the transmitting unit 1101 is configured to control the system controller to broadcast the first data signal to the at least one subsystem through the four-wire serial interface, specifically:

In one implementation manner, the sending unit 1101 is configured to control the subsystem to be debugged to report the second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, where the sending unit is specifically configured to:

the processing unit 1102 is further configured to:

The processing unit 1102 is configured to control the to-be-debugged subsystem to obtain state data of the to-be-debugged subsystem from a register set on the to-be-debugged subsystem side, where the to-be-debugged subsystem is specifically configured to:

In one implementation, the first data signal carries a data frame including a buffer field segment for adjusting timing between the system controller and each of the at least one subsystem; the processing unit 1102 is configured to control the system controller to debug the subsystem to be debugged based on the second data signal, specifically configured to:

In one implementation, the chip is connected to the computer device using a universal serial port; the processing unit 1102 is configured to, when the to-be-debugged subsystem is debugged based on state data of the to-be-debugged subsystem, specifically:

According to an embodiment of the present application, each unit in the chip debug apparatus shown in fig. 11 may be separately or completely combined into one or several other units, or some unit(s) thereof may be further split into a plurality of units with smaller functions, which may achieve the same operation without affecting the implementation of the technical effects of the embodiment of the present application. The above units are divided based on logic functions, and in practical applications, the functions of one unit may be implemented by a plurality of units, or the functions of a plurality of units may be implemented by one unit. In other embodiments of the present application, the chip debug apparatus may also include other units, and in practical applications, these functions may also be implemented with assistance from other units, and may be implemented by cooperation of a plurality of units. According to another embodiment of the present application, a chip debugging device as shown in fig. 11 may be constructed by running a computer program (including program code) capable of executing the steps involved in the respective methods as shown in fig. 3 on a general-purpose computing device such as a computer including a processing element such as a Central Processing Unit (CPU), a random access storage medium (RAM), a read only storage medium (ROM), and the like, and a storage element, and implementing the chip debugging method of the embodiment of the present application. The computer program may be recorded on, for example, a computer-readable recording medium, and loaded into and run in the above-described computing device through the computer-readable recording medium.

The embodiment of the application supports the communication between the system controller in the chip and each subsystem in at least one subsystem in the chip based on the four-wire serial interface. Thus, when the chip needs to be debugged, such as abnormal or dead chip bus (or subsystem, etc.), the system controller can be controlled to broadcast a first data signal to at least one subsystem through the four-wire serial interface, wherein the first data signal is used for indicating the subsystem to be debugged in the at least one subsystem. Then, the subsystem to be debugged can be controlled to report a second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, wherein the second data signal carries the state data of the subsystem to be debugged. Finally, the control system controller debugs the subsystem to be debugged based on the second data signal. It can be seen that embodiments of the present application provide a chip debug technique that is intermediate between external debug (such as JTAG/SWD debug methods) and internal debug (debug methods that access registers via a bus); the debug technique is capable of traversing inside the chip using a four-wire serial interface to interconnect the system controller and at least one subsystem into one debug system that is decoupled and independent from the chip bus. In this way, on one hand, compared with the external debugging technology, the debugging technology provided by the embodiment of the application does not need an external debugger, and can adopt the reference clock of the chip, so that higher debugging speed is ensured, the original structure of the chip is directly utilized for debugging, the debugging is convenient and fast, no extra cost is generated, and automatic debugging detection and the like can be realized through software. On the other hand, compared with the internal debugging technology, the debugging technology provided by the embodiment of the application can isolate the chip bus, namely, when the chip is debugged by adopting the debugging technology, the chip bus is not required to be relied on, so that the chip can be debugged even when the chip bus is abnormal or is suspended, the dependence of the chip debugging on the chip bus is reduced, and the practicability of the chip debugging is improved.

Fig. 12 is a schematic diagram showing the structure of a chip according to an exemplary embodiment of the present application. Referring to fig. 12, the chip includes a processor 1201, a communication interface 1202, and a computer readable storage medium 1203. Wherein the processor 1201, the communication interface 1202, and the computer readable storage medium 1203 may be connected by a bus or other means. Wherein the communication interface 1202 is for receiving and transmitting data. The computer readable storage medium 1203 may be stored in a memory of a chip, the computer readable storage medium 1203 is for storing a computer program comprising program instructions, and the processor 1201 is for executing the program instructions stored by the computer readable storage medium 1203. The processor 1201 (or CPU (Central Processing Unit, central processing unit)) is a computational core as well as a control core of a chip adapted to implement one or more instructions, in particular to load and execute one or more instructions to implement a corresponding method flow or a corresponding function.

The embodiment of the application also provides a computer readable storage medium (Memory), which is a Memory device in a chip and is used for storing programs and data. It is understood that the computer readable storage medium herein may include a built-in storage medium in a chip, and may include an extended storage medium supported by a chip. The computer readable storage medium provides a memory space that stores a processing system of the chip. Also stored in this memory space are one or more instructions, which may be one or more computer programs (including program code), adapted to be loaded and executed by the processor 1201. Note that the computer readable storage medium can be either a high-speed RAM memory or a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory; alternatively, it may be at least one computer-readable storage medium located remotely from the aforementioned processor.

In one embodiment, the computer-readable storage medium has one or more instructions stored therein; loading and executing, by the processor 1201, one or more instructions stored in a computer-readable storage medium to implement the corresponding steps in the chip debugging method embodiments described above; in a specific implementation, the chip comprises a system controller and at least one subsystem, wherein the system controller is communicated with any subsystem based on a four-wire serial interface; one or more instructions in a computer-readable storage medium are loaded by the processor 1201 and perform the steps of:

In one implementation, one or more instructions in a computer-readable storage medium are loaded by the processor 1201 and further perform the steps of:

In one implementation, a first data signal carries a data frame including a control field segment, a buffer field segment, and a data field segment; when one or more instructions in the computer-readable storage medium are loaded by the processor 1201 and executed to control the system controller to broadcast a first data signal to at least one subsystem over the four-wire serial interface, the following steps are specifically performed:

In one implementation, when one or more instructions in the computer-readable storage medium are loaded and executed by the processor 1201 to control the subsystem to be debugged to report the second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, the following steps are specifically performed:

one or more instructions in the computer-readable storage medium are loaded by the processor 1201 and further perform the steps of:

When one or more instructions in the computer-readable storage medium are loaded and executed by the processor 1201 to control the to-be-debugged subsystem to acquire state data of the to-be-debugged subsystem from the register set at the to-be-debugged subsystem side, the following steps are specifically executed:

In one implementation, the first data signal carries a data frame including a buffer field segment for adjusting timing between the system controller and each of the at least one subsystem; when one or more instructions in the computer-readable storage medium are loaded by the processor 1201 and executed to control the system controller to debug the subsystem to be debugged based on the second data signal, the following steps are specifically performed:

In one implementation, the chip is connected to the computer device using a universal serial port; when one or more instructions in the computer-readable storage medium are loaded by the processor 1201 and executed to debug the subsystem to be debugged based on the state data of the subsystem to be debugged, the following steps are specifically performed:

The embodiment of the application provides a chip debugging technology between external debugging (such as JTAG/SWD debugging method) and internal debugging (the debugging method of accessing a register through a bus); the debug technique is capable of traversing inside the chip using a four-wire serial interface to interconnect the system controller and at least one subsystem into one debug system that is decoupled and independent from the chip bus. In this way, on one hand, compared with the external debugging technology, the debugging technology provided by the embodiment of the application does not need an external debugger, and can adopt the reference clock of the chip, so that higher debugging speed is ensured, the original structure of the chip is directly utilized for debugging, the debugging is convenient and fast, no extra cost is generated, and automatic debugging detection and the like can be realized through software. On the other hand, compared with the internal debugging technology, the debugging technology provided by the embodiment of the application can isolate the chip bus, namely, when the chip is debugged by adopting the debugging technology, the chip bus is not required to be relied on, so that the chip can be debugged even when the chip bus is abnormal or is suspended, the dependence of the chip debugging on the chip bus is reduced, and the practicability of the chip debugging is improved.

The embodiment of the application also provides a computer program product, which comprises a computer program, and the computer program realizes the chip debugging method when being executed by a processor.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable devices. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data processing device, such as a server, data center, or the like, that contains an integration of one or more of the available media. The usable medium may be a magnetic medium (e.g., a floppy Disk, a hard Disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily appreciate variations or alternatives within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. The chip debugging method is characterized in that the chip comprises a system controller and at least one subsystem, and the system controller is communicated with any subsystem based on a four-wire serial interface; the method comprises the following steps:

controlling the system controller to broadcast a first data signal to the at least one subsystem through the four-wire serial interface; the first data signal is used for indicating a subsystem to be debugged in the at least one subsystem;

the subsystem to be debugged is controlled to report a second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, and the second data signal carries state data of the subsystem to be debugged;

and controlling the system controller to debug the subsystem to be debugged based on the second data signal.

2. The method of claim 1, wherein the four-wire serial interface comprises: an enable signal line, a clock signal line, an output data line, and an input data line; the signal flow directions of the data signals on the enable signal line, the clock signal line and the output data line are as follows: broadcasting from the system controller to each of the at least one subsystem; the signal flow direction of the data signal on the input data line is as follows: transmitting from a subsystem to the system controller;

the enabling signal line is used for controlling the on and off of a debugging mode aiming at the chip; when the level state of the enabling signal line is high level, the debugging mode is started; when the level state of the enabling signal line is a low level, the debug mode is turned off;

the clock signal line is used for controlling data receiving and transmitting synchronization between the system controller and the subsystem; when the level state of the clock signal line is high level, the system controller and the subsystem sample data signals;

the output data line is used for controlling the data signal transmission from the system controller to the subsystem direction;

the input data line is used for controlling the data signal transmission from the subsystem to the system controller.

3. The method of claim 2, wherein the method further comprises:

controlling the system controller to broadcast an enable signal to the at least one subsystem through the enable signal line; the method comprises the steps of,

controlling the system controller to broadcast successive clock pulses to the at least one subsystem via the clock signal line;

wherein a rising edge of a high level of the enable signal is aligned with a rising edge of a first clock pulse of the consecutive clock pulses.

4. The method of claim 3, wherein the first data signal carries a data frame comprising a control field segment, a buffer field segment, and a data field segment; the controlling the system controller to broadcast a first data signal to the at least one subsystem over the four-wire serial interface includes:

and starting from the rising edge of the clock pulse, controlling the system controller to sequentially broadcast the control domain segment, the buffer domain segment and the data domain segment to the at least one subsystem through the output data line.

5. The method of claim 4, wherein controlling the to-be-debugged subsystem to report a second data signal to the system controller via the four-wire serial interface as indicated by the first data signal comprises:

After the control of the subsystem to be debugged aiming at the control domain segment is finished, the control of the subsystem to be debugged acquires the state data of the subsystem to be debugged from a register group at the side of the subsystem to be debugged;

controlling the subsystem to be debugged to package the state data of the subsystem to be debugged into a second data signal;

6. The method of claim 5, wherein the control field includes at least a device identification field including a device identification of a subsystem to be debugged;

before the controlling the subsystem to be debugged obtains the state data of the subsystem to be debugged from the register set at the side of the subsystem to be debugged, the method further comprises:

starting from the rising edge of the clock pulse, controlling each subsystem in the at least one subsystem to sample a control domain segment carried by the first data signal through the output data line;

And determining a subsystem to be debugged, of which the equipment identifier is the same as the equipment identifier included in the equipment identifier field section, from the at least one subsystem based on the equipment identifier included in the equipment identifier field section, and triggering and executing the step of controlling the subsystem to be debugged to acquire the state data of the subsystem to be debugged from a register group at the side of the subsystem to be debugged.

7. The method of claim 5, wherein the register set on the side of the subsystem to be debugged includes a plurality of registers, the registers being at least used to cache state data of the subsystem to be debugged; the control domain section at least comprises a register domain section and an operation domain section;

the controlling the subsystem to be debugged to acquire the state data of the subsystem to be debugged from the register set at the side of the subsystem to be debugged, including:

the subsystem to be debugged is controlled to analyze the register field segment to obtain a register address; the register address refers to the address of a register which the system controller wants to access in the register group of the subsystem side to be debugged; the method comprises the steps of,

8. The method of claim 2, wherein the enable signal line, the clock signal line, and the output data line have the same number of stages of register delays inserted therein; the number of stages of register delay inserted in the input data line corresponding to different subsystems in the at least one subsystem is the same or different;

the first data signal carries a data frame, the data frame including a buffer field segment therein for adjusting timing between the system controller and each of the at least one subsystem;

the transmission time length Nsck of the buffer domain segment on the output data line is greater than or equal to the sum of the first register delay Nfp and the second register delay Nbp; wherein the first register delay Nfp is determined based on the number of stages of register delays inserted in the system controller to the at least one subsystem direction; the second register delay Nbp is determined based on the number of stages of register delays inserted in the direction from the subsystem to be debugged to the system controller.

9. The method of claim 2, wherein the first data signal carries a data frame, the data frame including a buffer field segment therein for adjusting timing between the system controller and each of the at least one subsystem; the controlling the system controller to debug the subsystem to be debugged based on the second data signal includes:

starting from the rising edge of the first clock pulse after the buffer domain segment is broadcasted, controlling the system controller to sample a second data signal reported by the subsystem to be debugged through the input data line;

the system controller is controlled to analyze the second data signal to obtain state data of the subsystem to be debugged;

10. The method of claim 9, wherein the chip is connected to a computer device using a universal serial port; the debugging the subsystem to be debugged based on the state data of the subsystem to be debugged comprises the following steps:

11. The method of claim 1, wherein the chip is a SOC chip that complies with a target bus protocol; the protocol conversion process of the SOC chip comprises the following steps:

a sender of the data signal generates a target data signal based on the target bus protocol;

after a receiving party of the data signal receives the intermediate data signal conforming to the data frame protocol, carrying out protocol conversion on the intermediate data signal to obtain a target data signal conforming to the target bus protocol;

when the sender of the data signal is the system controller, the receiver of the data signal is the subsystem to be debugged, and the intermediate data signal is the first data signal; when the sender of the data signal is the subsystem to be debugged, the receiver of the data signal is the system controller, and the intermediate data signal is the second data signal.

12. The method of claim 1, wherein the first data signal carries a data frame, the data frame comprising in sequence: a control field section, a buffer field section and a data field section; the control domain section comprises a device identification domain section, a register domain section and an operation domain section; wherein,

the register field section comprises the address of a target register in a register group of the subsystem side to be debugged, wherein the target register is a register which is to be accessed by the system controller in the register group;

the operation field section comprises an operation code, wherein the operation code is used for indicating the operation type of the system controller aiming at the subsystem to be debugged;

the buffer domain segment comprises redundancy bits, and the redundancy bits are used for adjusting the circuit time sequence;

the data field section includes transfer data, wherein the transfer data is data which the system controller wants to transfer to the subsystem to be debugged.

13. The chip debugging device is characterized in that the chip comprises a system controller and at least one subsystem, and the system controller is communicated with any subsystem based on a four-wire serial interface; the device comprises:

a transmitting unit for controlling the system controller to broadcast a first data signal to the at least one subsystem through the four-wire serial interface; the first data signal is used for indicating a subsystem to be debugged in the at least one subsystem;

The sending unit is further configured to control the to-be-debugged subsystem to report a second data signal to the system controller through the four-wire serial interface according to the indication of the first data signal, where the second data signal carries state data of the to-be-debugged subsystem;

14. A chip, wherein the chip comprises a system controller and at least one subsystem, and the system controller and any subsystem are communicated based on a four-wire serial interface; the system controller and the at least one subsystem in the chip are configured to implement the chip debug method as claimed in any one of claims 1-12.