CN110910921A - Command read-write method and device and computer storage medium - Google Patents
Command read-write method and device and computer storage medium Download PDFInfo
- Publication number
- CN110910921A CN110910921A CN201911205765.8A CN201911205765A CN110910921A CN 110910921 A CN110910921 A CN 110910921A CN 201911205765 A CN201911205765 A CN 201911205765A CN 110910921 A CN110910921 A CN 110910921A
- Authority
- CN
- China
- Prior art keywords
- read
- write
- command
- bus
- cache region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000000872 buffer Substances 0.000 claims abstract description 159
- 230000005540 biological transmission Effects 0.000 claims description 7
- 238000004590 computer program Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000000977 initiatory effect Effects 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
According to the command reading and writing method and device provided by the embodiment of the invention, a bus reading/writing command is received; writing the received bus write commands belonging to the same Burst DDR Burst access into the same write cache region; directly returning data of a read cache region which belongs to the same DDR Burst access with the bus read command; then reading the read buffer area or the write buffer area to execute DDR Burst read or write operation. The method only needs to increase a certain buffer area and scribe, combines the read/write commands of the bus interface through the control logic, and executes the combined bus read/write commands by the DDR SRAM port, thereby achieving the purpose of improving the efficiency. For multiple small data access, it is only necessary to send a bus read/write command in a combined manner, so that the efficiency is remarkably improved.
Description
Technical Field
The embodiment of the invention relates to the field of DDR (double data rate) memory data reading and writing, in particular to a command reading and writing method, a command reading and writing device and a computer storage medium.
Background
DDR SDRAM is a synchronous dynamic random access memory, which adopts double-rate access, and data are sampled at the rising edge and the falling edge of a working clock, so that the access rate is effectively improved.
The data access of DDR SDRAM is in Burst unit, when the data access amount is less than 1 Burst, the data access is still in Burst unit. The Burst access characteristic of the DDR SDRAM makes the DDR controller of the AXI bus or similar bus interface very inefficient for multiple small data accesses from the host to non-consecutive addresses. The AXI bus, unlike the AHB bus, can support the continuous transmission of multiple read and write commands.
Taking reading and writing 1Byte data as an example, the DDR controller receives reading and writing commands of three non-consecutive addresses 0x01, 0x03 and 0x05 of the bus, the three commands are all used for completing reading and writing of 1Byte, and the data access amount is less than one DDR Burst. And the conventional DDR controller only realizes the direct conversion of time sequences, and for the read-write commands of the three addresses, the DDR controller needs to initiate 3 DDR Burst transmissions to complete data access.
In the related art, one method for improving the read-write efficiency of the DDR is to achieve seamless read-write of data. The premise of seamless reading and writing is that the burst length of DDR is a fixed value, and the interval between two reading commands is well controlled. For the case that the burst length is set to 4, one NOP command needs to be inserted between two read commands to achieve seamless reading and writing of data. For the case where the burst length is set to 8, three NOP commands need to be inserted between two read commands. The method has no obvious improvement on efficiency for small data volume read-write access of non-continuous addresses, and 3 DDR Burst transmissions still need to be sent for the above-mentioned scenes of reading and writing 1Byte commands of three non-continuous addresses 0x01, 0x03 and 0x05, and only the effective data of the data line is continuous and uninterrupted. In addition, in order to realize seamless transmission, the complexity of the control logic of the DDR controller for initiating the read-write command is increased.
Disclosure of Invention
The command read-write method, the command read-write device and the computer storage medium provided by the embodiment of the invention mainly solve the technical problems of low read/write efficiency caused by continuous multiple small data volume read/write commands of DDR and the condition that the efficiency is not obviously improved by related technologies.
To solve the foregoing technical problem, an embodiment of the present invention provides a command read/write method, which is applied to a command read/write apparatus, where the command read/write apparatus includes: reading the cache region and writing the cache region; the command reading and writing method comprises the following steps:
receiving a bus read/write command;
writing the received bus write commands belonging to the same Burst DDR Burst access into the same write cache region;
returning data of a read cache region which belongs to the same DDR Burst access with the bus read command;
and reading the read cache region or the write cache region to execute DDR Burst read or write operation.
Optionally, writing the received bus write commands belonging to the same DDR Burst access into the same write buffer area includes:
receiving a first bus write command, and writing the first bus write command into a first write cache region, so that the first write cache region and the first bus write command belong to the same DDR Burst access;
receiving a second bus write command, and judging whether the second bus write command and the first write cache region belong to the same DDR Burst access;
if so, writing the second bus write command into the first write cache region;
and if not, writing the second write command of the bus into a second write cache region.
Optionally, returning the data of the read buffer area accessed by the same DDR Burst as the bus read command includes:
judging whether a used read cache region which belongs to the same DDR Burst access with the bus read command exists or not;
if yes, the used read buffer area which belongs to the same DDR Burst access with the bus read command is used as a first read buffer area, and data of the first read buffer area are returned.
Optionally, the used read buffer includes: and any one of the data valid identifier or the command valid identifier is a valid read buffer.
The method comprises the following steps of taking a used read buffer area which belongs to the same DDR Burst access with the bus read command as a first read buffer area, and returning data of the first read buffer area to the read buffer area, wherein the read buffer area comprises the following steps:
judging whether the data valid identification of the first read cache region is valid;
if yes, returning the data of the first read cache region;
if not, returning the data of the first read cache region when the data valid identification becomes valid.
Optionally, when there is no used read buffer area belonging to the same DDR Burst access as the bus read command;
and the effective mark of the bus read command write command is an invalid read cache region, the read cache region written in the bus read command is used as a second read cache region, and the effective mark of the command of the second read cache region written in the bus read command is effective.
Optionally, after receiving the bus read/write command, the method includes:
judging whether the bus read/write command crosses DDR Burst transmission or not;
if yes, the bus read/write command is split into a plurality of sub-bus read/write commands according to the DDR Burst address rule, and the split sub-bus read/write commands are not transmitted across the DDR Burst
Optionally, after reading the write buffer, before performing the DDR Burst write operation, the method further includes:
judging whether the read cache region with the effective data identification belongs to the same DDR Burst access as the read write cache region;
if yes, setting the data valid identification of the read buffer area which belongs to the same DDR Burst access with the read write buffer area and is valid as the valid data valid identification as the invalid data valid identification.
Further, this embodiment also provides a command read/write device, which includes: the system comprises a bus interface module, a cache control module, a cache module and a read-write module; the cache module comprises: reading the cache region and writing the cache region;
the bus interface module is used for receiving a bus read/write command;
the cache control module is used for writing the received bus write commands which belong to the same Burst DDR Burst access into the same write cache region;
the cache control module is also used for returning the data of the read cache region which belongs to the same DDR Burst access with the bus read command;
the read-write module is used for reading the read cache region or the write cache region to execute DDR Burst read or write operation
Further, this embodiment also provides a computer-readable storage medium, where the computer-readable storage medium stores one or more programs, and the one or more programs are executable by one or more processors to implement the steps of the command read-write method described above.
The invention has the beneficial effects that:
according to the command reading and writing method and device provided by the embodiment of the invention, a bus reading/writing command is received; writing the received bus write commands belonging to the same Burst DDR Burst access into the same write cache region; directly returning data of a read cache region which belongs to the same DDR Burst access with the bus read command; then reading the read buffer area or the write buffer area to execute DDR Burst read or write operation. The method only needs to increase a certain buffer area and scribe, combines the read/write commands of the bus interface through the control logic, and executes the combined bus read or write commands by the DDR SRAM port, thereby achieving the purpose of improving the efficiency. For multiple small data access, it is only necessary to send a bus read/write command in a combined manner, so that the efficiency is remarkably improved.
Drawings
Fig. 1 is a schematic basic flowchart of a command read/write method according to an embodiment of the present invention;
fig. 2 is a schematic basic flowchart illustrating a process of writing a bus write command into a write buffer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a basic flow chart of writing a bus read command into a read buffer according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a combination of bus commands into a bus command according to a second embodiment of the present invention;
FIG. 5 is a diagram illustrating a read command transmitted across DDR bursts being split into two DDR Burst transmission read commands according to a third embodiment of the present invention;
fig. 6 is a schematic structural diagram of a command read/write apparatus according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The first embodiment is as follows:
the method aims to solve the problem that the efficiency of reading and writing a plurality of continuous small data volumes is low and the condition that the efficiency is not obviously improved by related technologies.
Referring to fig. 1, fig. 1 is a basic flowchart of a command read/write method according to an embodiment of the present invention, where the command read/write method is applied to a command read/write device, and the command read/write device includes: reading the cache region and writing the cache region; the command reading and writing method comprises the following steps:
s10, receiving a bus read/write command;
it is to be understood that buses include, but are not limited to: an AXI bus; the embodiment is not limited to the AXI bus, and may be a bus that can be used to send a read/write command to a cache region; it should be noted that the data length of each command in each read/write command sent by the bus is not limited; for example: the AXI bus may send a command with a data length of 2 first, and then the bus sends a command with a data length of 4; i.e. the data length of the commands sent by the bus may vary. In this embodiment, a bus read/write command is received, and it is necessary to determine whether the received command is transmitted across DDR Burst, if so, the received bus command is split into a plurality of sub-bus commands according to the DDR Burst address rule, and each split sub-bus command is no longer transmitted across DDRBurst; specifically, for example, when the length of the DDR Burst data stored in the buffer is 8, the received bus command is to read 3 Byte data sequentially from an address starting from 0x06, and at this time, it is determined that the command is transmitted across the DDR Burst, and the command is split into: sequentially reading 2 Byte data to the address starting from 0x 06; and sequentially reading 1Byte datum from the address starting at 0x08, wherein the split command is not transmitted across DDR Burst. And executing the subsequent steps of the split command in sequence.
It is to be understood that the DDR Burst length of the read-write module may be any one of 4, 8, and 16, and it is only necessary to meet the DDRBurst length setting rule, and it is to be understood that the DDR Burst length of the read-write module remains unchanged after the DDR Burst length setting is completed; it should be understood that the length of the DDR Burst data stored in the cache region may be any one of 4, 8 and 16, the length of the DDR Burst data stored in each cache region is the same, and meanwhile, the length of the DDR Burst data stored in each cache region is also kept unchanged after the setting of the length of the DDR Burst data stored in each cache region is completed; preferably, the DDR Burst data length stored in each cache region is consistent with the DDR Burst length of the read-write module.
S20, writing the received bus write commands which belong to the same Burst DDR Burst access into the same write buffer area;
it should be understood that the number of write buffers in the DDR controller is not limited, and preferably there may be 16 write buffers, each write buffer including but not limited to the following information: the starting address addr, a command valid identifier c _ valid, a data register data and a data valid identifier d _ valid; the data register data and the data valid flag d _ valid have an association relationship, and specifically, for example, when valid data exists in the data register data2, the data valid flag d _ valid2 is correspondingly set to be valid.
In this embodiment, as shown in fig. 2, writing the received bus write commands belonging to the same Burst DDR Burst access into the same write buffer includes the following steps:
s201, receiving a first bus write command, and writing the first bus write command into a first write cache region to enable the first write cache region and the first bus write command to belong to the same DDR Burst access;
in this embodiment, specifically, for example, when the DDR Burst data length stored in the buffer is 8, the bus first write command is received: writing data d1 of 1Byte to 0x01 address; at this time, the bus first write command is to initiate a DDR Burst access to the address segment 0x0-0x07, that is, the DDR Burst initial address of the bus first write command is 0x 0; when it is judged that no write cache region belonging to the same DDR burst access as the first write command exists, the first write command of the bus is written into the first write cache region, and the following steps need to be executed, it needs to be understood that the following steps do not need to be in sequence, and the specific execution sequence can be flexibly set by related designers, and the steps are as follows:
setting a command valid identifier c _ valid of the first write cache area as valid; setting the start address addr of the first write buffer to the same start address as the first write command of the bus: 0x 0; setting the data register data1 of the first write buffer to d 1; setting the data valid identification d _ valid1 to valid; and after the operation is finished, the first write command of the bus is successfully written into the first write cache region.
It should be understood that, when setting each valid flag, it may be: when the level of the effective mark is low, the effective mark is judged to be effective, and when the level of the effective mark is high, the effective mark is judged to be invalid; the following steps can be also included: when the level of the valid flag is low, it is determined as invalid, and when the level of the valid flag is high, it is determined as valid. And are not limited herein.
S202, receiving a second write command of the bus, and judging whether the second write command of the bus and the first write cache region belong to the same DDR Burst access, if so, turning to S203, and if not, turning to S204;
in this embodiment, when the second write command of the bus and the first write buffer belong to the same DDR Burst access, go to S203; specifically, for example, when the data length of the DDR Burst stored in the cache region is 8, the starting address addr of the first write cache region is: at 0x0, the second write command is to write 1Byte of data d3 to the address 0x03, and the starting address of the second write command is: 0x 0; after receiving the second write command of the bus, judging that the second write command of the bus is overlapped with the initial address of the first write cache region, namely that the second write command of the bus and the first write cache region belong to the same DDR Burst access, and at this time, turning to S203;
in this embodiment, when the second write command of the bus and the first write buffer do not belong to the same DDR Burst access, go to S204; specifically, for example, when the length of the DDR Burst data stored in the cache region is 8, the starting address addr of the first write cache region is: at 0x0, the second write command is to write 1Byte of data d3 to the address 0x09, and the starting address of the second write command is: 0x 8; after receiving the second write command of the bus, judging that the second write command of the bus is not overlapped with the initial address of the first write cache region, and the second write command of the bus and the first write cache region do not belong to the same DDR Burst access, and at the moment, turning to S204;
s203, writing a second bus write command into the first write cache region;
in the embodiment, a second bus write command is written into the first write cache region; in particular, the method comprises the following steps of,
for example, when the length of the DDR Burst data stored in the buffer is 8, the starting address of the first write buffer is: 0x 0; receiving a bus second write command: writing data d2 of 1Byte to 0x06 address; at this time, the bus second write command is to initiate DDR Burst access to the address segment 0x0-0x07, that is, the starting address of the bus second write command is 0x 0; when the second write command of the bus is written into the first write cache region, the following steps need to be executed, it should be understood that the following steps do not have a sequence, and the specific execution sequence can be flexibly set by a relevant designer, and the steps are as follows:
setting the data register data6 of the first write buffer to d 2; setting the data valid identification d _ valid6 to valid; and after the operation is finished, the second write command of the bus is successfully written into the first write cache region. It should be understood that, in the second write of the bus write command, the same write buffer does not need to set the command valid id c _ valid and the start address of the write buffer again.
And S204, writing the second write command of the bus into a second write cache region.
In this embodiment, specifically, for example, when the DDR Burst data length stored in the buffer area is 8, the bus second write command is received: writing data d9 of 1Byte to 0x09 address; at this time, the bus second write command is to initiate DDR Burst access to the address segment 0x08-0x0f, that is, the starting address of the bus second command is 0x 08; when the second write command of the bus is written into the second write cache region, the following steps need to be executed, it should be understood that the following steps do not have a sequence, and the specific execution sequence can be flexibly set by a relevant designer, and the steps are as follows:
setting the command valid identifier c _ valid of the second write cache area as valid; setting the starting address addr of the second write cache region as the same starting address as the bus second write command: 0x 08; setting the data register data1 of the second write buffer to d 9; setting the data valid identification d _ valid1 to valid; and after the operation is finished, the second write command of the bus is successfully written into the second write cache region.
It needs to be understood that when a bus write command is received, whether initial addresses of all write cache regions with valid command flags c _ valid are overlapped or not needs to be sequentially judged until the write cache regions with the same initial addresses are found, and the received bus write command is added to the write cache regions with overlapped initial addresses; or adding the received bus write command to the write cache area with the invalid command valid flag c _ valid until the write cache area with the valid command valid flags c _ valid is judged, and when the write cache area with the overlapped starting address of the bus write command does not exist. For example, when 16 write cache regions exist in the DDR controller, wherein the command valid identifiers c _ valid of the first to eighth write cache regions are valid, when a third bus write command is received, whether the start address of the third bus write command overlaps with the start addresses of the first to eighth write cache regions in sequence needs to be determined, and if the same start address, that is, the overlapping write cache regions are found, the third bus write command is added to the write cache region with the same start address; or if the starting address of the third bus write command is sequentially overlapped with the starting addresses of the first to eighth write cache regions, and if the write cache region with the same starting address is not found, adding the third bus write command to the unused ninth to sixteenth write cache region.
S30, returning data of a read cache area accessed by the same DDR Burst with the bus read command;
it should be understood that the number of read buffers in the DDR controller is not limited, and preferably, the number of read buffers is equal to the number of write buffers, and there are 16 read buffers; each read buffer includes, but is not limited to, the following information: the starting address addr, a command valid identifier c _ valid, a data register data and a data valid identifier d _ valid; it should be understood that only one data valid id d _ valid exists in one read buffer.
In this embodiment, as shown in fig. 3, returning the data of the read buffer belonging to the same DDR Burst access as the bus read command comprises the following steps:
s301, judging whether a used read cache region which belongs to the same DDR Burst access with a bus read command exists; if so, go to S302, if not, go to S303.
In this embodiment, the read buffers that are used include, but are not limited to, any of the following read buffers: the data valid id d _ valid is a valid read buffer, and the command valid id c _ valid is a valid read buffer. That is, when a bus read command is received, it is only compared with the start address of the used read buffer, and not with the start address of the unused read buffer.
S302, the used read cache region which belongs to the same DDR Burst access with the bus read command is used as a first read cache region, and data of the first read cache region are returned.
In this embodiment, taking a used read buffer that belongs to the same DDR Burst access as the bus read command as the first read buffer, and returning data of the first read buffer includes: judging whether the data valid identification of the first read cache region is valid; if yes, returning the data of the first read cache region. If not, when the data valid identification becomes valid, returning the data of the first read cache region.
In this embodiment, before taking a used read buffer that belongs to the same DDR Burst access as the bus read command as the first read buffer and returning data of the first read buffer, the method further includes: judging whether the data valid identifier d _ valid of the first read cache area is valid or not; if so, returning data corresponding to the read address of the bus read command message in the first read cache region immediately; if not, returning the data corresponding to the read address of the bus read command message in the first read cache region after the data valid flag of the first read cache region is valid. Specifically, for example, when the DDR Burst data length stored in the buffer is 8, the received bus read command is to read 1Byte of data to an address of 0x03, where the starting address of the bus read command is: 0x 0; after receiving the bus read command, judging that the bus read command is overlapped with the initial address of the first read cache region, namely when the bus read command and the first read cache region belong to the same DDR Burst access, judging that a data valid identifier d _ valid of the first read cache region is valid, and directly returning data of a data register data3 in the first read cache region as read data; if the data valid identifier d _ valid of the first read cache region is determined to be invalid, waiting for the data valid identifier d _ valid of the first read cache region to become valid, and then returning the data of the data register data3 in the first read cache region as read data.
S303, effectively marking the bus read command write command as an invalid read cache region, taking the read cache region written with the bus read command as a second read cache region, and effectively marking the command valid mark of the second read cache region written with the bus read command as valid;
in this embodiment, when there is no used read buffer area that belongs to the same DDR Burst access as the bus read command, the valid identifier of the bus read command write command is an invalid read buffer area, the read buffer area into which the bus read command is written is used as a second read buffer area, and the valid identifier of the command of the second read buffer area after the bus read command is written is valid; specifically, for example, when the DDR Burst data length stored in the buffer is 8, a bus read command is received: sequentially reading 3 Byte data from 0x01 address, wherein the bus read command initiates DDR Burst access to 0x0-0x07 address segment, and the starting address of the bus read command is 0x 0; when it is determined that there is no used read cache with a start address of 0x0, the bus read command needs to be added with a read cache with an invalid command valid identifier c _ valid; when a bus read command is written into a read cache, the following steps need to be executed, it should be understood that the following steps are not in sequence, the specific execution sequence can be flexibly set by a relevant designer, and the steps are as follows:
setting a command valid identifier c _ valid of the second read cache area as valid; setting the start address addr of the second read cache region to be the same start address as the first read command of the bus: 0x 0.
It should be understood that, in some embodiments, when the bus read command is added to a read cache area whose command valid identifier c _ valid is invalid, the read cache area is preferentially written into the unused read cache area; when there is no unused read buffer in the DDR controller, the write command valid flag c _ valid is an invalid used read buffer.
S40, the read buffer area or the write buffer area executes DDR Burst read or write operation.
It should be understood that, at the same time, only the read buffers in the read buffers or the write buffers in the read/write buffers can be read, for example, one write buffer in the read/write buffers performs a corresponding DDR Burst write operation; or one read buffer area in the read buffer areas is read to execute corresponding DDR Burst read operation.
In this embodiment, when the read write buffer executes DDR Burst write operation, only the read command valid identifier c _ valid is valid; specifically, for example, there are 16 write buffers, where only the command valid id c _ valid of the first write buffer is valid, and the read command valid id c _ valid is valid in the first write buffer, when the data valid ids d _ valid1 and d _ valid3 in the first write buffer are valid, the data of the read data registers data1 and data3 execute a DDR Burst write operation, after the read is completed, the command valid id c _ valid of the first write buffer is set to invalid, and the data valid ids d _ valid1 and d _ valid3 of the first write buffer are set to invalid.
In this embodiment, when the read cache region executes DDR Burst read operation, only the read command valid identifier c _ valid is valid, specifically, for example, 16 read cache regions exist, where only the command valid identifier c _ valid of the first read cache region is valid, the read command valid identifier c _ valid is valid in the first read cache region, the read operation is executed according to the start address addr of the first read cache region, and the following steps need to be executed after the read operation is completed, it is understood that the following steps are not divided into orders, and the specific execution order may be flexibly set by related designers, and the steps are as follows:
and sequentially adding the read data into a data register data of the first read cache region, setting a command valid identifier c _ valid of the first read cache region as invalid, and setting a data valid identifier d _ valid of the first read cache region as valid.
It should be understood that the read cache region executes DDR Burst read operation, the read data are sequentially added to the data register data of the first read cache region, the command valid identifier c _ valid of the first read cache region is set to be invalid, and after the command valid identifier d _ valid of the first read cache region is set to be valid, the data corresponding to each read command in the data register data need to be returned.
It should be understood that, the information of the valid command identifier c _ valid is taken away as an effective cache region, when a corresponding DDR Burst read or write operation is executed, the information of the valid command identifier c _ valid as an effective cache region may be taken away according to the sequence of setting the valid command identifier c _ valid of each cache region to execute a corresponding command, or the information of the valid command identifier c _ valid as an effective cache region may be taken away according to the sequence of other bus-tagged commands to execute a corresponding command; it should be understood that, this embodiment is not used to limit the fetching sequence of the cache area in which the specific fetching command valid identifier c _ valid is valid, and may be flexibly set by the relevant designer.
In this embodiment, when the fetch command valid identifier c _ valid is a valid write buffer, it is further determined whether the write buffer and any read buffer having a valid data identifier belong to the same DDR Burst access; if yes, clearing the data valid identification of the read cache region which belongs to the same DDR Burst access with the write cache region. Specifically, for example, when the first write cache region is taken away, the start address addr of the first write cache region is compared with the start address addr of the read cache region, and when it is determined that the start address addr of the read cache region is the same as the taken-away start address addr of the write cache region and the data valid flag of the read cache region is valid, the data valid flag of the read cache region is cleared or set to be invalid.
The command read-write method provided by the embodiment of the invention receives a bus read/write command; writing the received bus write commands belonging to the same DDR Burst access into the same write cache region; directly returning data of a read cache region which belongs to the same DDR Burst access with the bus read command; then reading the read buffer area or the write buffer area to execute DDR Burst read or write operation. By the method, a plurality of small data read-write operation commands are combined together, so that the frequency of DDR Burst read-write operation is reduced, the data read-write efficiency of the DDR memory is improved, and the waste of system resources is reduced.
Example two:
for convenience of understanding, the present embodiment describes a command reading/writing method with a specific example, where the command reading/writing method includes:
receiving a bus write command, judging whether a write address area in the bus write command is overlapped with an address area in a write buffer area write slice when the read-write control logic of the DDR memory is in a non-idle state, setting the write buffer area write slice used according to the bus write command when the overlap exists with the write buffer area write slice address area used, and setting the write buffer area write slice unused according to the bus write command when the overlap does not exist. Preferably, in this implementation, there are 16 write buffer areas write slice, and each write buffer area write slice stores therein DDR Burst write operation information, where the DDR Burst write operation information includes: the starting address addr, the command valid identifier c _ valid, the data register data and the data valid identifier d _ valid; the write buffer write slice with the valid command identifier c _ valid being valid is a valid write buffer write slice, i.e. the write buffer write slice is used, the write buffer write slice with the invalid command valid identifier c _ valid being invalid is an invalid write buffer write slice, i.e. the write buffer write slice is not used, and the total number of the used write buffer write slice and the unused write buffer write slice is 16.
In this embodiment, the following may be specifically mentioned: when the DDR SDRAM read-write control logic is in a busy state, for example, in a phase of sending an active command, bus write commands of three discontinuous addresses are received successively, the first bus write command is to write 1Byte data d1 to 0x01 address, the second bus write command is to write 1Byte data d3 to 0x03 address, and the third bus write command is to write 1Byte data d5 to 0x05 address. As shown in fig. 4, the multiple bus write commands are merged into 1 DDR Burst write command, which is as follows: judging that a write buffer write slice0 overlapping with the address area of the first bus write command exists, when the starting address addr of the write buffer write slice0 is 0x00, storing the data register data of 0x01 address in the write buffer write slice0 into data d1 and setting the data valid flag d _ valid1 of 0x 84 address as valid according to the first bus write command, judging that the write address area of the second bus write command overlaps with the address area of the write buffer write slice0, storing the data register data of 0x03 address in the write buffer write slice0 into data d3 according to the second bus write command, setting the data valid flag d _ valid3 of 0x03 address as valid according to the second bus write command, judging that the write address area of the third bus write command overlaps with the write buffer 0 address area, storing the write data register data 0 of the third bus write command into the write buffer 05 data. And setting the data valid identifier d _ valid5 of the address 0x05 as valid, when the DDR SDRAM read-write control logic is in an idle state, recognizing that the command valid identifier c _ valid of the write buffer 0 is valid, acquiring data in the data register data according to each valid data valid identifier d _ valid in the write buffer write slice0, and controlling the analog circuit PHY to implement the write of the DDR Burst according to the write buffer write slice0, where after the DDR SDRAM read-write control logic takes the write buffer information, immediately setting the valid data valid identifier d _ valid in the write buffer write slice0 as invalid, and simultaneously setting the command valid identifier c _ valid as invalid. The DDR Burst write operation is initiated once, the original write command needing to initiate three DDR bursts is processed, and the efficiency is greatly improved;
it should be noted that, when there is no address region overlapping with the write address region of the first bus write command in the write buffer, the unused write buffer 1 is set according to the first bus write command, so that the start address of the write buffer write slice1 is 0x00, and at this time, it can be determined that the write address regions of the second and third bus write commands overlap with the write buffer write slice1 address region.
The DDR memory data read-write method provided by the embodiment of the invention receives a bus write command; judging whether a write address area in the bus write command is overlapped with an address area in a write buffer area write slice; if so, adding the information in the bus write command into a write buffer write slice to generate a new DDR Burst write command; by the method, when the DDRSDRAM read-write control logic is in a busy state, a plurality of small data write operation commands are combined together, the number of times of DDR Burst write operation needs to be initiated is reduced, the data read-write efficiency of the DDR memory is improved, and the waste of system resources is reduced.
EXAMPLE III
For convenience of understanding, the present embodiment describes a command reading/writing method with a specific example, where the command reading/writing method includes:
receiving a bus read command, judging whether a read address region in the bus read command is overlapped with an address region in a read slice of a read cache region, setting the read slice of the used read cache region according to the bus read command when the read address region is overlapped with the read slice of the used read cache region, and setting the read slice of the unused read cache region according to the DDR Burst read command when the read address region is not overlapped with the read slice of the used read cache region. Preferably, in this implementation, there are 16 read buffers, and each read buffer stores DDR Burst read operation information, where the DDR Burst read operation information includes: the starting address addr, the command valid identifier c _ valid, the data register data and the data valid identifier d _ valid; the method includes that a command valid identifier c _ valid or a data valid flag d _ valid in a read slice of a read cache is valid read slice, namely the read slice of the read cache is used, the command valid identifier c _ valid and the data valid flag d _ valid are both invalid read slice of the invalid read cache, namely the read slice of the unused read cache, and the sum of the number of the used read slice and the number of the unused read slice of the read cache is 16.
In this embodiment, the following may be specifically mentioned: two bus read commands are received successively, the first bus read command is to read 3 bytes of data sequentially from the address beginning at 0x06, and the second bus read command is to read 1Byte of data from the address 0x 03.
As shown in fig. 5, after receiving the two commands, it is determined that the address of the first bus read command is transmitted across the DDR Burst, so that the first bus read command is split into sub-bus read commands 1: reading the data of 2 bytes in sequence to the address starting at 0x06, sub-bus read command 2: reading 1Byte of data to an address of 0x 08;
judging that a read buffer read slice with an address area overlapped with the read address area of the sub-bus read command 1 does not exist, and judging that a read buffer read slice0 with an address area overlapped with the read address area of the sub-bus read command 2 exists;
setting a read slice1 of an unused read buffer zone according to a sub-bus read command 1, setting a command valid identifier c _ valid of a read buffer zone readslice1 to be valid, and setting the starting address of the read buffer zone read slice1 to be 0x 00; according to the sub-bus read command 2, after the read operation of the read buffer 0 is completed, the data in the buffer is returned as read data.
And if the address area of the read buffer slice1 is judged to be overlapped with the read address area of the second read command of the bus, returning the data of the buffer as read data after the read operation of the read buffer slice1 is finished.
When the DDR SDRAM read-write control logic is in an idle state, recognizing that c _ valid of a read buffer slice0 is valid, taking away DDR Burst read information, initiating a read operation with a DDR Burst length of 8 and an initial address of 0x00 to the DDR SDRAM according to the DDR Burst read information, setting a command valid identifier c _ valid in the read buffer slice0 to be invalid after the read operation is completed, setting a data valid identifier d _ valid in the read buffer slice0 to be valid, and sequentially adding the read data to data registers data of the read buffer slice 0. Then, the DDR SDRAM read-write control logic determines that c _ valid of the read slice1 buffer is valid, so a read operation with a DDR Burst length of 8 and an initial address of 0x08 is initiated again, after the read operation is completed, the command valid identifier c _ valid in the read buffer readslice1 is set to invalid, and meanwhile, the data valid identifier d _ valid in the read buffer readslice1 is set to valid, and the read data are sequentially added to the data register data of the read buffer readslice 1. Thus, the data of the first bus read command and the second bus read command are all read back.
The command reading and writing method provided by the embodiment of the invention receives the bus reading command; judging whether a read address area in the bus read command is overlapped with an address area in a read slice of a read cache area; if so, returning the data serving as read data after judging that the data in the overlapped buffer area is valid, and not repeatedly initiating a DDR read command; by the method, the small data read operation commands are combined together, the number of times of DDR Burst read operation needs to be initiated is reduced, the data read-write efficiency of the DDR memory is improved, the occupation of a DDR port is reduced, the read efficiency is improved, and the waste of system resources is reduced.
Example four
The present embodiment further provides a command read/write apparatus, where the command read/write apparatus is configured to implement at least one step of the command read/write method according to any one of the first embodiment, the second embodiment, and the third embodiment; as shown in fig. 6, the command read/write device includes a bus interface module, a command cache control module, and a read/write module;
the bus interface module is used for receiving a bus read/write command;
the bus interface module is also used for judging whether the bus read/write command is transmitted across DDR Burst; if so, splitting the bus command into a plurality of sub-bus commands according to the DDR Burst address rule, and enabling the split sub-bus read/write commands not to be transmitted across the DDR Burst.
The cache control module is used for writing the received bus write commands which belong to the same DDR Burst access into the same write cache region;
the cache control module is also used for returning the data of the read cache region which belongs to the same DDR Burst access with the bus read command;
the read-write module is used for reading the read cache region or the write cache region to execute DDR Burst read or write operation.
The present embodiments also provide a computer-readable storage medium including volatile or non-volatile, removable or non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, computer program modules or other data. Computer-readable storage media include, but are not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash Memory or other Memory technology, CD-ROM (Compact disk Read-Only Memory), Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer.
The computer-readable storage medium in this embodiment may be used to store one or more computer programs, and the stored one or more computer programs may be executed by a processor to implement at least one step of the command reading and writing method in the first embodiment, the second embodiment, and the third embodiment.
It will be apparent to those skilled in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software (which may be implemented in computer program code executable by a computing device), firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.
In addition, communication media typically embodies computer readable instructions, data structures, computer program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to one of ordinary skill in the art. Thus, the present invention is not limited to any specific combination of hardware and software.
The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A command read-write method is applied to a command read-write device, and the command read-write device comprises: reading the cache region and writing the cache region; the command reading and writing method comprises the following steps:
receiving a bus read/write command;
writing the received bus write commands belonging to the same Burst DDR Burst access into the same write cache region;
returning data of a read cache region which belongs to the same DDR Burst access with the bus read command;
and reading the read cache region or the write cache region to execute DDR Burst read or write operation.
2. The command read-write method according to claim 1, wherein the writing the received bus write commands belonging to the same DDR Burst access into the same write buffer includes:
receiving a first bus write command, and writing the first bus write command into a first write cache region, so that the first write cache region and the first bus write command belong to the same DDR Burst access;
receiving a second bus write command, and judging whether the second bus write command and the first write cache region belong to the same DDR Burst access;
if so, writing the second bus write command into the first write cache region;
and if not, writing the second write command of the bus into a second write cache region.
3. The command read-write method according to claim 1, wherein the returning the data of the read buffer area accessed by the same DDRBurst as the bus read command comprises:
judging whether a used read cache region which belongs to the same DDR Burst access with the bus read command exists or not;
if yes, the used read buffer area which belongs to the same DDR Burst access with the bus read command is used as a first read buffer area, and data of the first read buffer area are returned.
4. A method for reading and writing commands as claimed in claim 3, wherein said used read buffer comprises: and any one of the data valid identifier or the command valid identifier is a valid read buffer.
5. The command read-write method according to claim 4, wherein before taking a used read buffer that belongs to the same DDRBurst access as the bus read command as a first read buffer and returning data of the first read buffer, the method includes:
judging whether the data valid identification of the first read cache region is valid;
if yes, returning the data of the first read cache region;
if not, returning the data of the first read cache region when the data valid identification becomes valid.
6. The command read/write method according to claim 5, wherein when there is no used read buffer area belonging to the same DDRBurst access as the bus read command;
and the effective mark of the bus read command write command is an invalid read cache region, the read cache region written in the bus read command is used as a second read cache region, and the effective mark of the command of the second read cache region written in the bus read command is effective.
7. The method according to any one of claims 1 to 6, wherein the receiving of the bus read/write command includes:
judging whether the bus read/write command crosses DDR Burst transmission or not;
if so, splitting the bus read/write command into a plurality of sub-bus read/write commands according to the DDR Burst address rule, wherein the split sub-bus read/write commands are not transmitted across the DDR Burst.
8. The method as claimed in claim 7, wherein after reading the write buffer, before performing the DDR Burst write operation, the method further comprises:
judging whether the read cache region with the effective data identification belongs to the same DDR Burst access as the read write cache region;
if yes, setting the data valid identification of the read buffer area which belongs to the same DDR Burst access with the read write buffer area and is valid as the valid data valid identification as the invalid data valid identification.
9. A command read/write apparatus, comprising: the system comprises a bus interface module, a cache control module, a cache module and a read-write module; the cache module comprises: reading the cache region and writing the cache region;
the bus interface module is used for receiving a bus read/write command;
the cache control module is used for writing the received bus write commands which belong to the same Burst DDR Burst access into the same write cache region;
the cache control module is also used for returning the data of the read cache region which belongs to the same DDR Burst access with the bus read command;
the read-write module is used for reading the read cache region or the write cache region and executing DDR Burst read or write operation.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores one or more programs which are executable by one or more processors to implement the steps of the command read-write method according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911205765.8A CN110910921A (en) | 2019-11-29 | 2019-11-29 | Command read-write method and device and computer storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911205765.8A CN110910921A (en) | 2019-11-29 | 2019-11-29 | Command read-write method and device and computer storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110910921A true CN110910921A (en) | 2020-03-24 |
Family
ID=69820902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911205765.8A Pending CN110910921A (en) | 2019-11-29 | 2019-11-29 | Command read-write method and device and computer storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110910921A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111399781A (en) * | 2020-04-21 | 2020-07-10 | 中国科学院光电技术研究所 | Storage method for improving reliability of real-time image recording system |
| CN111984551A (en) * | 2020-08-21 | 2020-11-24 | 苏州浪潮智能科技有限公司 | Cache consistency processing method, device, equipment and readable medium |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN113643326A (en) * | 2021-06-07 | 2021-11-12 | 深圳市智绘科技有限公司 | KNN calculating device and path planning system based on SoC |
| CN113821470A (en) * | 2020-06-19 | 2021-12-21 | 平头哥(上海)半导体技术有限公司 | Bus device, embedded system and system on chip |
| CN113836238A (en) * | 2021-09-30 | 2021-12-24 | 杭州数梦工场科技有限公司 | Batch processing method and device for data commands |
| CN114036096A (en) * | 2021-11-04 | 2022-02-11 | 珠海一微半导体股份有限公司 | Read controller based on bus interface |
| CN114281723A (en) * | 2020-09-28 | 2022-04-05 | 马来西亚瑞天芯私人有限公司 | Memory controller system and memory scheduling method of storage device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123113A (en) * | 2007-09-20 | 2008-02-13 | 上海交通大学 | Access method and control device for synchronous dynamic random access memory |
| CN102567241A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | Memory controller and memory access control method |
| WO2017157110A1 (en) * | 2016-03-18 | 2017-09-21 | 深圳市中兴微电子技术有限公司 | Method of controlling high-speed access to double data rate synchronous dynamic random access memory, and device |
| CN108491168A (en) * | 2018-03-30 | 2018-09-04 | 北京联想核芯科技有限公司 | A kind of processing method and solid state disk of reading and writing command stream |
| CN109446125A (en) * | 2018-10-09 | 2019-03-08 | 武汉正维电子技术有限公司 | DDR reads and writes moderator and method |
| CN211376201U (en) * | 2019-11-29 | 2020-08-28 | 深圳市国微电子有限公司 | Command read-write device and memory |
-
2019
- 2019-11-29 CN CN201911205765.8A patent/CN110910921A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123113A (en) * | 2007-09-20 | 2008-02-13 | 上海交通大学 | Access method and control device for synchronous dynamic random access memory |
| CN102567241A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | Memory controller and memory access control method |
| WO2017157110A1 (en) * | 2016-03-18 | 2017-09-21 | 深圳市中兴微电子技术有限公司 | Method of controlling high-speed access to double data rate synchronous dynamic random access memory, and device |
| CN108491168A (en) * | 2018-03-30 | 2018-09-04 | 北京联想核芯科技有限公司 | A kind of processing method and solid state disk of reading and writing command stream |
| CN109446125A (en) * | 2018-10-09 | 2019-03-08 | 武汉正维电子技术有限公司 | DDR reads and writes moderator and method |
| CN211376201U (en) * | 2019-11-29 | 2020-08-28 | 深圳市国微电子有限公司 | Command read-write device and memory |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111399781A (en) * | 2020-04-21 | 2020-07-10 | 中国科学院光电技术研究所 | Storage method for improving reliability of real-time image recording system |
| CN111399781B (en) * | 2020-04-21 | 2023-09-19 | 中国科学院光电技术研究所 | Storage method for improving reliability of real-time image recording system |
| CN113821470A (en) * | 2020-06-19 | 2021-12-21 | 平头哥(上海)半导体技术有限公司 | Bus device, embedded system and system on chip |
| CN111984551B (en) * | 2020-08-21 | 2022-07-12 | 苏州浪潮智能科技有限公司 | Cache consistency processing method, device, equipment and readable medium |
| CN111984551A (en) * | 2020-08-21 | 2020-11-24 | 苏州浪潮智能科技有限公司 | Cache consistency processing method, device, equipment and readable medium |
| CN114281723A (en) * | 2020-09-28 | 2022-04-05 | 马来西亚瑞天芯私人有限公司 | Memory controller system and memory scheduling method of storage device |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112416823B (en) * | 2020-11-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN113643326A (en) * | 2021-06-07 | 2021-11-12 | 深圳市智绘科技有限公司 | KNN calculating device and path planning system based on SoC |
| CN113643326B (en) * | 2021-06-07 | 2022-04-08 | 深圳市智绘科技有限公司 | KNN calculating device and path planning system based on SoC |
| CN113836238A (en) * | 2021-09-30 | 2021-12-24 | 杭州数梦工场科技有限公司 | Batch processing method and device for data commands |
| CN114036096A (en) * | 2021-11-04 | 2022-02-11 | 珠海一微半导体股份有限公司 | Read controller based on bus interface |
| CN114036096B (en) * | 2021-11-04 | 2024-05-03 | 珠海一微半导体股份有限公司 | Read controller based on bus interface |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110910921A (en) | Command read-write method and device and computer storage medium | |
| CN211376201U (en) | Command read-write device and memory | |
| US9110669B2 (en) | Power management of a storage device including multiple processing cores | |
| CN110941395B (en) | Dynamic random access memory, memory management method, system and storage medium | |
| US8996788B2 (en) | Configurable flash interface | |
| KR102517685B1 (en) | Memory block recovery method and device | |
| CN102566939B (en) | Solid state disk (SSD) and read-modify-write operation data management method thereof | |
| TWI403897B (en) | Memory device and data management method thereof | |
| US20240086332A1 (en) | Data processing method and system, device, and medium | |
| US20220253252A1 (en) | Data processing method and apparatus | |
| CN114371814B (en) | Data processing method and device and solid state disk | |
| US20130290621A1 (en) | Ddr controller, method for implementing the same, and chip | |
| CN116679887B (en) | Universal control module and method for NAND Flash | |
| CN111176566B (en) | eMMC read-write control method supporting queue command and storage medium | |
| US10203962B2 (en) | Tigersharc DSP boot management chip and method | |
| CN107943413B (en) | Method for improving reading performance of solid state disk | |
| CN113010236B (en) | Program execution method, device, equipment and storage medium | |
| US11199998B2 (en) | Non-volatile dual in-line memory module (NVDIMM) device assisted operations management | |
| CN107748678A (en) | A kind of system and method for improving heterogeneous system starting up speed | |
| WO2021159608A1 (en) | Protocol buffers-based mirror cache method | |
| CN105205017A (en) | Storage controller based on PCIE SSD | |
| US8166228B2 (en) | Non-volatile memory system and method for reading and storing sub-data during partially overlapping periods | |
| WO2022126534A1 (en) | Data processing method and related device | |
| CN110781118B (en) | Method and device for realizing parallel bus slave mode, computer equipment and medium | |
| US20080104307A1 (en) | Multi-sector to single-sector request mapping |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |